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tcg/riscv: Implement vector roti/v/x ops

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Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20241007025700.47259-12-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
TANG Tiancheng 2024-10-07 10:56:59 +08:00 committed by Richard Henderson
parent cbde22f18b
commit d1843219a1
2 changed files with 39 additions and 3 deletions
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36
tcg/riscv/tcg-target.c.inc
View File

@ -2488,6 +2488,34 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
set_vtype_len_sew(s, type, vece);
tcg_out_vshifti(s, OPC_VSRA_VI, OPC_VSRA_VX, a0, a1, a2);
break;
case INDEX_op_rotli_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, TCG_REG_V0, a1, a2);
tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1,
-a2 & ((8 << vece) - 1));
tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0);
break;
case INDEX_op_rotls_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vx(s, OPC_VSLL_VX, TCG_REG_V0, a1, a2);
tcg_out_opc_reg(s, OPC_SUBW, TCG_REG_TMP0, TCG_REG_ZERO, a2);
tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, TCG_REG_TMP0);
tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0);
break;
case INDEX_op_rotlv_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0);
tcg_out_opc_vv(s, OPC_VSRL_VV, TCG_REG_V0, a1, TCG_REG_V0);
tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2);
tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0);
break;
case INDEX_op_rotrv_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0);
tcg_out_opc_vv(s, OPC_VSLL_VV, TCG_REG_V0, a1, TCG_REG_V0);
tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2);
tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0);
break;
case INDEX_op_cmp_vec:
tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2,
-1, true, 0, true);
@ -2537,6 +2565,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shri_vec:
case INDEX_op_shli_vec:
case INDEX_op_sari_vec:
case INDEX_op_rotls_vec:
case INDEX_op_rotlv_vec:
case INDEX_op_rotrv_vec:
case INDEX_op_rotli_vec:
case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec:
return 1;
@ -2695,6 +2727,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
case INDEX_op_rotli_vec:
return C_O1_I1(v, v);
case INDEX_op_add_vec:
case INDEX_op_and_vec:
@ -2715,10 +2748,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
case INDEX_op_rotlv_vec:
case INDEX_op_rotrv_vec:
return C_O1_I2(v, v, v);
case INDEX_op_shls_vec:
case INDEX_op_shrs_vec:
case INDEX_op_sars_vec:
case INDEX_op_rotls_vec:
return C_O1_I2(v, v, r);
case INDEX_op_cmp_vec:
return C_O1_I2(v, v, vL);

6
tcg/riscv/tcg-target.h
View File

@ -154,9 +154,9 @@ typedef enum {
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0
#define TCG_TARGET_HAS_roti_vec 1
#define TCG_TARGET_HAS_rots_vec 1
#define TCG_TARGET_HAS_rotv_vec 1
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec 1