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hw/intc: Don't clear pending bits on IRQ lowering

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According to PLIC specification (chapter 5), there
is only one case, when interrupt is claimed. Fix
PLIC controller to match this behavior.

Signed-off-by: Sergey Makarov <s.makarov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240918140229.124329-3-s.makarov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit a84be2baa9)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Sergey Makarov 2024-09-18 17:02:29 +03:00 committed by Michael Tokarev
parent 17eedf2aea
commit 3b83646541
1 changed files with 4 additions and 2 deletions
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6
hw/intc/sifive_plic.c
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@ -349,8 +349,10 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
{
SiFivePLICState *s = opaque;
sifive_plic_set_pending(s, irq, level > 0);
sifive_plic_update(s);
if (level > 0) {
sifive_plic_set_pending(s, irq, true);
sifive_plic_update(s);
}
}
static void sifive_plic_realize(DeviceState *dev, Error **errp)