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target/loongarch: Use gen_helper_gvec_3_ptr for 3OP + env vector instructions

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Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-6-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-09-14 10:25:53 +08:00
parent eb48ab2256
commit 3b286753c9
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
3 changed files with 91 additions and 73 deletions
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48
target/loongarch/helper.h
View File

@ -519,14 +519,14 @@ DEF_HELPER_4(vfrstp_h, void, env, i32, i32, i32)
DEF_HELPER_4(vfrstpi_b, void, env, i32, i32, i32)
DEF_HELPER_4(vfrstpi_h, void, env, i32, i32, i32)
DEF_HELPER_4(vfadd_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfadd_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfsub_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfsub_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfmul_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmul_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfdiv_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfdiv_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(vfadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfmadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfmadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
@ -537,15 +537,15 @@ DEF_HELPER_FLAGS_6(vfnmadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i3
DEF_HELPER_FLAGS_6(vfnmsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfnmsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vfmax_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmax_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfmin_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmin_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(vfmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vfmaxa_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmaxa_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfmina_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmina_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(vfmaxa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmaxa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmina_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmina_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_3(vflogb_s, void, env, i32, i32)
DEF_HELPER_3(vflogb_d, void, env, i32, i32)
@ -564,8 +564,8 @@ DEF_HELPER_3(vfcvtl_s_h, void, env, i32, i32)
DEF_HELPER_3(vfcvth_s_h, void, env, i32, i32)
DEF_HELPER_3(vfcvtl_d_s, void, env, i32, i32)
DEF_HELPER_3(vfcvth_d_s, void, env, i32, i32)
DEF_HELPER_4(vfcvt_h_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfcvt_s_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(vfcvt_h_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfcvt_s_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_3(vfrintrne_s, void, env, i32, i32)
DEF_HELPER_3(vfrintrne_d, void, env, i32, i32)
@ -592,11 +592,11 @@ DEF_HELPER_3(vftintrz_wu_s, void, env, i32, i32)
DEF_HELPER_3(vftintrz_lu_d, void, env, i32, i32)
DEF_HELPER_3(vftint_wu_s, void, env, i32, i32)
DEF_HELPER_3(vftint_lu_d, void, env, i32, i32)
DEF_HELPER_4(vftintrne_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vftintrz_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vftintrp_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vftintrm_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vftint_w_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(vftintrne_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vftintrz_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vftintrp_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vftintrm_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vftint_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_3(vftintrnel_l_s, void, env, i32, i32)
DEF_HELPER_3(vftintrneh_l_s, void, env, i32, i32)
DEF_HELPER_3(vftintrzl_l_s, void, env, i32, i32)
@ -614,7 +614,7 @@ DEF_HELPER_3(vffint_s_wu, void, env, i32, i32)
DEF_HELPER_3(vffint_d_lu, void, env, i32, i32)
DEF_HELPER_3(vffintl_d_w, void, env, i32, i32)
DEF_HELPER_3(vffinth_d_w, void, env, i32, i32)
DEF_HELPER_4(vffint_s_l, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(vffint_s_l, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vseqi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vseqi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)

66
target/loongarch/insn_trans/trans_vec.c.inc
View File

@ -52,6 +52,24 @@ static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a,
return gen_vvvv_vl(ctx, a, 16, fn);
}
static bool gen_vvv_ptr_vl(DisasContext *ctx, arg_vvv *a, uint32_t oprsz,
gen_helper_gvec_3_ptr *fn)
{
tcg_gen_gvec_3_ptr(vec_full_offset(a->vd),
vec_full_offset(a->vj),
vec_full_offset(a->vk),
cpu_env,
oprsz, ctx->vl / 8, 0, fn);
return true;
}
static bool gen_vvv_ptr(DisasContext *ctx, arg_vvv *a,
gen_helper_gvec_3_ptr *fn)
{
CHECK_SXE;
return gen_vvv_ptr_vl(ctx, a, 16, fn);
}
static bool gen_vvv(DisasContext *ctx, arg_vvv *a,
void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
{
@ -3648,14 +3666,14 @@ TRANS(vfrstp_h, LSX, gen_vvv, gen_helper_vfrstp_h)
TRANS(vfrstpi_b, LSX, gen_vv_i, gen_helper_vfrstpi_b)
TRANS(vfrstpi_h, LSX, gen_vv_i, gen_helper_vfrstpi_h)
TRANS(vfadd_s, LSX, gen_vvv, gen_helper_vfadd_s)
TRANS(vfadd_d, LSX, gen_vvv, gen_helper_vfadd_d)
TRANS(vfsub_s, LSX, gen_vvv, gen_helper_vfsub_s)
TRANS(vfsub_d, LSX, gen_vvv, gen_helper_vfsub_d)
TRANS(vfmul_s, LSX, gen_vvv, gen_helper_vfmul_s)
TRANS(vfmul_d, LSX, gen_vvv, gen_helper_vfmul_d)
TRANS(vfdiv_s, LSX, gen_vvv, gen_helper_vfdiv_s)
TRANS(vfdiv_d, LSX, gen_vvv, gen_helper_vfdiv_d)
TRANS(vfadd_s, LSX, gen_vvv_ptr, gen_helper_vfadd_s)
TRANS(vfadd_d, LSX, gen_vvv_ptr, gen_helper_vfadd_d)
TRANS(vfsub_s, LSX, gen_vvv_ptr, gen_helper_vfsub_s)
TRANS(vfsub_d, LSX, gen_vvv_ptr, gen_helper_vfsub_d)
TRANS(vfmul_s, LSX, gen_vvv_ptr, gen_helper_vfmul_s)
TRANS(vfmul_d, LSX, gen_vvv_ptr, gen_helper_vfmul_d)
TRANS(vfdiv_s, LSX, gen_vvv_ptr, gen_helper_vfdiv_s)
TRANS(vfdiv_d, LSX, gen_vvv_ptr, gen_helper_vfdiv_d)
TRANS(vfmadd_s, LSX, gen_vvvv_ptr, gen_helper_vfmadd_s)
TRANS(vfmadd_d, LSX, gen_vvvv_ptr, gen_helper_vfmadd_d)
@ -3666,15 +3684,15 @@ TRANS(vfnmadd_d, LSX, gen_vvvv_ptr, gen_helper_vfnmadd_d)
TRANS(vfnmsub_s, LSX, gen_vvvv_ptr, gen_helper_vfnmsub_s)
TRANS(vfnmsub_d, LSX, gen_vvvv_ptr, gen_helper_vfnmsub_d)
TRANS(vfmax_s, LSX, gen_vvv, gen_helper_vfmax_s)
TRANS(vfmax_d, LSX, gen_vvv, gen_helper_vfmax_d)
TRANS(vfmin_s, LSX, gen_vvv, gen_helper_vfmin_s)
TRANS(vfmin_d, LSX, gen_vvv, gen_helper_vfmin_d)
TRANS(vfmax_s, LSX, gen_vvv_ptr, gen_helper_vfmax_s)
TRANS(vfmax_d, LSX, gen_vvv_ptr, gen_helper_vfmax_d)
TRANS(vfmin_s, LSX, gen_vvv_ptr, gen_helper_vfmin_s)
TRANS(vfmin_d, LSX, gen_vvv_ptr, gen_helper_vfmin_d)
TRANS(vfmaxa_s, LSX, gen_vvv, gen_helper_vfmaxa_s)
TRANS(vfmaxa_d, LSX, gen_vvv, gen_helper_vfmaxa_d)
TRANS(vfmina_s, LSX, gen_vvv, gen_helper_vfmina_s)
TRANS(vfmina_d, LSX, gen_vvv, gen_helper_vfmina_d)
TRANS(vfmaxa_s, LSX, gen_vvv_ptr, gen_helper_vfmaxa_s)
TRANS(vfmaxa_d, LSX, gen_vvv_ptr, gen_helper_vfmaxa_d)
TRANS(vfmina_s, LSX, gen_vvv_ptr, gen_helper_vfmina_s)
TRANS(vfmina_d, LSX, gen_vvv_ptr, gen_helper_vfmina_d)
TRANS(vflogb_s, LSX, gen_vv, gen_helper_vflogb_s)
TRANS(vflogb_d, LSX, gen_vv, gen_helper_vflogb_d)
@ -3693,8 +3711,8 @@ TRANS(vfcvtl_s_h, LSX, gen_vv, gen_helper_vfcvtl_s_h)
TRANS(vfcvth_s_h, LSX, gen_vv, gen_helper_vfcvth_s_h)
TRANS(vfcvtl_d_s, LSX, gen_vv, gen_helper_vfcvtl_d_s)
TRANS(vfcvth_d_s, LSX, gen_vv, gen_helper_vfcvth_d_s)
TRANS(vfcvt_h_s, LSX, gen_vvv, gen_helper_vfcvt_h_s)
TRANS(vfcvt_s_d, LSX, gen_vvv, gen_helper_vfcvt_s_d)
TRANS(vfcvt_h_s, LSX, gen_vvv_ptr, gen_helper_vfcvt_h_s)
TRANS(vfcvt_s_d, LSX, gen_vvv_ptr, gen_helper_vfcvt_s_d)
TRANS(vfrintrne_s, LSX, gen_vv, gen_helper_vfrintrne_s)
TRANS(vfrintrne_d, LSX, gen_vv, gen_helper_vfrintrne_d)
@ -3721,11 +3739,11 @@ TRANS(vftintrz_wu_s, LSX, gen_vv, gen_helper_vftintrz_wu_s)
TRANS(vftintrz_lu_d, LSX, gen_vv, gen_helper_vftintrz_lu_d)
TRANS(vftint_wu_s, LSX, gen_vv, gen_helper_vftint_wu_s)
TRANS(vftint_lu_d, LSX, gen_vv, gen_helper_vftint_lu_d)
TRANS(vftintrne_w_d, LSX, gen_vvv, gen_helper_vftintrne_w_d)
TRANS(vftintrz_w_d, LSX, gen_vvv, gen_helper_vftintrz_w_d)
TRANS(vftintrp_w_d, LSX, gen_vvv, gen_helper_vftintrp_w_d)
TRANS(vftintrm_w_d, LSX, gen_vvv, gen_helper_vftintrm_w_d)
TRANS(vftint_w_d, LSX, gen_vvv, gen_helper_vftint_w_d)
TRANS(vftintrne_w_d, LSX, gen_vvv_ptr, gen_helper_vftintrne_w_d)
TRANS(vftintrz_w_d, LSX, gen_vvv_ptr, gen_helper_vftintrz_w_d)
TRANS(vftintrp_w_d, LSX, gen_vvv_ptr, gen_helper_vftintrp_w_d)
TRANS(vftintrm_w_d, LSX, gen_vvv_ptr, gen_helper_vftintrm_w_d)
TRANS(vftint_w_d, LSX, gen_vvv_ptr, gen_helper_vftint_w_d)
TRANS(vftintrnel_l_s, LSX, gen_vv, gen_helper_vftintrnel_l_s)
TRANS(vftintrneh_l_s, LSX, gen_vv, gen_helper_vftintrneh_l_s)
TRANS(vftintrzl_l_s, LSX, gen_vv, gen_helper_vftintrzl_l_s)
@ -3743,7 +3761,7 @@ TRANS(vffint_s_wu, LSX, gen_vv, gen_helper_vffint_s_wu)
TRANS(vffint_d_lu, LSX, gen_vv, gen_helper_vffint_d_lu)
TRANS(vffintl_d_w, LSX, gen_vv, gen_helper_vffintl_d_w)
TRANS(vffinth_d_w, LSX, gen_vv, gen_helper_vffinth_d_w)
TRANS(vffint_s_l, LSX, gen_vvv, gen_helper_vffint_s_l)
TRANS(vffint_s_l, LSX, gen_vvv_ptr, gen_helper_vffint_s_l)
static bool do_cmp(DisasContext *ctx, arg_vvv *a, MemOp mop, TCGCond cond)
{

50
target/loongarch/vec_helper.c
View File

@ -2096,13 +2096,13 @@ static inline void vec_clear_cause(CPULoongArchState *env)
}
#define DO_3OP_F(NAME, BIT, E, FN) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t vk) \
void HELPER(NAME)(void *vd, void *vj, void *vk, \
CPULoongArchState *env, uint32_t desc) \
{ \
int i; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
VReg *Vk = &(env->fpr[vk].vreg); \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
\
vec_clear_cause(env); \
for (i = 0; i < LSX_LEN/BIT; i++) { \
@ -2326,14 +2326,14 @@ void HELPER(vfcvth_d_s)(CPULoongArchState *env, uint32_t vd, uint32_t vj)
*Vd = temp;
}
void HELPER(vfcvt_h_s)(CPULoongArchState *env,
uint32_t vd, uint32_t vj, uint32_t vk)
void HELPER(vfcvt_h_s)(void *vd, void *vj, void *vk,
CPULoongArchState *env, uint32_t desc)
{
int i;
VReg temp;
VReg *Vd = &(env->fpr[vd].vreg);
VReg *Vj = &(env->fpr[vj].vreg);
VReg *Vk = &(env->fpr[vk].vreg);
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
vec_clear_cause(env);
for(i = 0; i < LSX_LEN/32; i++) {
@ -2344,14 +2344,14 @@ void HELPER(vfcvt_h_s)(CPULoongArchState *env,
*Vd = temp;
}
void HELPER(vfcvt_s_d)(CPULoongArchState *env,
uint32_t vd, uint32_t vj, uint32_t vk)
void HELPER(vfcvt_s_d)(void *vd, void *vj, void *vk,
CPULoongArchState *env, uint32_t desc)
{
int i;
VReg temp;
VReg *Vd = &(env->fpr[vd].vreg);
VReg *Vj = &(env->fpr[vj].vreg);
VReg *Vk = &(env->fpr[vk].vreg);
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
vec_clear_cause(env);
for(i = 0; i < LSX_LEN/64; i++) {
@ -2482,14 +2482,14 @@ FTINT(rz_w_d, float64, int32, uint64_t, uint32_t, float_round_to_zero)
FTINT(rne_w_d, float64, int32, uint64_t, uint32_t, float_round_nearest_even)
#define FTINT_W_D(NAME, FN) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t vk) \
void HELPER(NAME)(void *vd, void *vj, void *vk, \
CPULoongArchState *env, uint32_t desc) \
{ \
int i; \
VReg temp; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
VReg *Vk = &(env->fpr[vk].vreg); \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
\
vec_clear_cause(env); \
for (i = 0; i < 2; i++) { \
@ -2606,14 +2606,14 @@ void HELPER(vffinth_d_w)(CPULoongArchState *env, uint32_t vd, uint32_t vj)
*Vd = temp;
}
void HELPER(vffint_s_l)(CPULoongArchState *env,
uint32_t vd, uint32_t vj, uint32_t vk)
void HELPER(vffint_s_l)(void *vd, void *vj, void *vk,
CPULoongArchState *env, uint32_t desc)
{
int i;
VReg temp;
VReg *Vd = &(env->fpr[vd].vreg);
VReg *Vj = &(env->fpr[vj].vreg);
VReg *Vk = &(env->fpr[vk].vreg);
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
vec_clear_cause(env);
for (i = 0; i < 2; i++) {