PPC: Bamboo: fold ppc440.c and ppc440_bamboo.c into a single file
The separation of ppc440 and ppc440_bamboo makes some sense, since ppc440 is the SoC while ppc440_bamboo is the actual board. But the separation makes things harder for us for no good reason, so let's just fold them in together with each other. Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -250,7 +250,7 @@ obj-ppc-$(CONFIG_PSERIES) += xics.o spapr_vty.o spapr_llan.o spapr_vscsi.o
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obj-ppc-$(CONFIG_PSERIES) += spapr_pci.o device-hotplug.o pci-hotplug.o
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# PowerPC 4xx boards
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obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
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obj-ppc-y += ppc440.o ppc440_bamboo.o
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obj-ppc-y += ppc440_bamboo.o
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# PowerPC E500 boards
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obj-ppc-y += ppce500_mpc8544ds.o mpc8544_guts.o ppce500_spin.o
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# PowerPC 440 Xilinx ML507 reference board.
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107
hw/ppc440.c
107
hw/ppc440.c
@ -1,107 +0,0 @@
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/*
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* Qemu PowerPC 440 chip emulation
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*
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* Copyright 2007 IBM Corporation.
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* Authors:
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* Jerone Young <jyoung5@us.ibm.com>
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* Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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* Hollis Blanchard <hollisb@us.ibm.com>
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "hw.h"
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#include "pc.h"
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#include "isa.h"
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#include "ppc.h"
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#include "ppc4xx.h"
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#include "ppc440.h"
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#include "ppc405.h"
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#include "sysemu.h"
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#include "kvm.h"
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#define PPC440EP_PCI_CONFIG 0xeec00000
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#define PPC440EP_PCI_INTACK 0xeed00000
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#define PPC440EP_PCI_SPECIAL 0xeed00000
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#define PPC440EP_PCI_REGS 0xef400000
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#define PPC440EP_PCI_IO 0xe8000000
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#define PPC440EP_PCI_IOLEN 0x00010000
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#define PPC440EP_SDRAM_NR_BANKS 4
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static const unsigned int ppc440ep_sdram_bank_sizes[] = {
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256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
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};
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CPUState *ppc440ep_init(MemoryRegion *address_space_mem, ram_addr_t *ram_size,
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PCIBus **pcip, const unsigned int pci_irq_nrs[4],
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int do_init, const char *cpu_model)
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{
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MemoryRegion *ram_memories
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= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
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target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
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target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
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CPUState *env;
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qemu_irq *pic;
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qemu_irq *irqs;
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qemu_irq *pci_irqs;
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if (cpu_model == NULL) {
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cpu_model = "440EP";
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}
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to initialize CPU!\n");
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exit(1);
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}
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ppc_booke_timers_init(env, 400000000, 0);
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ppc_dcr_init(env, NULL, NULL);
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/* interrupt controller */
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irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
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irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
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irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
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pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
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/* SDRAM controller */
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memset(ram_bases, 0, sizeof(ram_bases));
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memset(ram_sizes, 0, sizeof(ram_sizes));
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*ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS,
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ram_memories,
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ram_bases, ram_sizes,
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ppc440ep_sdram_bank_sizes);
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/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
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ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
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ram_bases, ram_sizes, do_init);
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/* PCI */
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pci_irqs = g_malloc(sizeof(qemu_irq) * 4);
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pci_irqs[0] = pic[pci_irq_nrs[0]];
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pci_irqs[1] = pic[pci_irq_nrs[1]];
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pci_irqs[2] = pic[pci_irq_nrs[2]];
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pci_irqs[3] = pic[pci_irq_nrs[3]];
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*pcip = ppc4xx_pci_init(env, pci_irqs,
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PPC440EP_PCI_CONFIG,
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PPC440EP_PCI_INTACK,
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PPC440EP_PCI_SPECIAL,
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PPC440EP_PCI_REGS);
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if (!*pcip)
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printf("couldn't create PCI controller!\n");
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isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
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if (serial_hds[0] != NULL) {
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serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
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PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
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DEVICE_BIG_ENDIAN);
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}
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if (serial_hds[1] != NULL) {
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serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
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PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
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DEVICE_BIG_ENDIAN);
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}
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return env;
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}
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21
hw/ppc440.h
21
hw/ppc440.h
@ -1,21 +0,0 @@
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/*
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* Qemu PowerPC 440 board emualtion
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*
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* Copyright 2007 IBM Corporation.
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* Authors: Jerone Young <jyoung5@us.ibm.com>
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* Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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*
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* This work is licensed under the GNU GPL licence version 2 or later
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*
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*/
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#ifndef QEMU_PPC440_H
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#define QEMU_PPC440_H
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#include "hw.h"
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CPUState *ppc440ep_init(MemoryRegion *address_space, ram_addr_t *ram_size,
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PCIBus **pcip, const unsigned int pci_irq_nrs[4],
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int do_init, const char *cpu_model);
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#endif
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@ -17,13 +17,16 @@
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#include "hw.h"
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#include "pci.h"
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#include "boards.h"
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#include "ppc440.h"
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#include "kvm.h"
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#include "kvm_ppc.h"
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#include "device_tree.h"
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#include "loader.h"
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#include "elf.h"
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#include "exec-memory.h"
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#include "pc.h"
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#include "ppc.h"
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#include "ppc405.h"
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#include "sysemu.h"
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#define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
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@ -32,6 +35,19 @@
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#define FDT_ADDR 0x1800000
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#define RAMDISK_ADDR 0x1900000
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#define PPC440EP_PCI_CONFIG 0xeec00000
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#define PPC440EP_PCI_INTACK 0xeed00000
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#define PPC440EP_PCI_SPECIAL 0xeed00000
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#define PPC440EP_PCI_REGS 0xef400000
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#define PPC440EP_PCI_IO 0xe8000000
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#define PPC440EP_PCI_IOLEN 0x00010000
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#define PPC440EP_SDRAM_NR_BANKS 4
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static const unsigned int ppc440ep_sdram_bank_sizes[] = {
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256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
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};
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static target_phys_addr_t entry;
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static PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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@ -43,6 +59,78 @@ static PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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return NULL;
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}
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CPUState *ppc440ep_init(MemoryRegion *address_space_mem, ram_addr_t *ram_size,
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PCIBus **pcip, const unsigned int pci_irq_nrs[4],
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int do_init, const char *cpu_model)
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{
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MemoryRegion *ram_memories
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= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
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target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
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target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
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CPUState *env;
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qemu_irq *pic;
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qemu_irq *irqs;
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qemu_irq *pci_irqs;
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if (cpu_model == NULL) {
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cpu_model = "440EP";
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}
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to initialize CPU!\n");
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exit(1);
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}
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ppc_booke_timers_init(env, 400000000, 0);
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ppc_dcr_init(env, NULL, NULL);
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/* interrupt controller */
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irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
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irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
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irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
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pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
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/* SDRAM controller */
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memset(ram_bases, 0, sizeof(ram_bases));
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memset(ram_sizes, 0, sizeof(ram_sizes));
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*ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS,
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ram_memories,
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ram_bases, ram_sizes,
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ppc440ep_sdram_bank_sizes);
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/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
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ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
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ram_bases, ram_sizes, do_init);
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/* PCI */
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pci_irqs = g_malloc(sizeof(qemu_irq) * 4);
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pci_irqs[0] = pic[pci_irq_nrs[0]];
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pci_irqs[1] = pic[pci_irq_nrs[1]];
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pci_irqs[2] = pic[pci_irq_nrs[2]];
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pci_irqs[3] = pic[pci_irq_nrs[3]];
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*pcip = ppc4xx_pci_init(env, pci_irqs,
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PPC440EP_PCI_CONFIG,
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PPC440EP_PCI_INTACK,
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PPC440EP_PCI_SPECIAL,
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PPC440EP_PCI_REGS);
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if (!*pcip)
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printf("couldn't create PCI controller!\n");
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isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
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if (serial_hds[0] != NULL) {
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serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
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PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
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DEVICE_BIG_ENDIAN);
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}
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if (serial_hds[1] != NULL) {
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serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
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PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
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DEVICE_BIG_ENDIAN);
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}
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return env;
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}
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static int bamboo_load_device_tree(target_phys_addr_t addr,
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uint32_t ramsize,
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target_phys_addr_t initrd_base,
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@ -38,7 +38,6 @@
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#include "ppc.h"
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#include "ppc4xx.h"
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#include "ppc440.h"
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#include "ppc405.h"
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#include "blockdev.h"
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