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PPC: 4xx: Qdevify the 440 PCI host controller

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Due to popular demand, this qdevifies the PCI host controller of 4xx SoCs
the same way as e500.

We have to introduce a small stub function for pci init that will be
removed in a later patch, once we qdev'ified the board, to keep the build
working.

Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf 2012-01-10 19:36:26 +01:00
parent acd1bf9083
commit 623f7c2172
2 changed files with 68 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
hw/ppc440_bamboo.c
View File

@ -34,6 +34,15 @@
static target_phys_addr_t entry;
static PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
target_phys_addr_t config_space,
target_phys_addr_t int_ack,
target_phys_addr_t special_cycle,
target_phys_addr_t registers)
{
return NULL;
}
static int bamboo_load_device_tree(target_phys_addr_t addr,
uint32_t ramsize,
target_phys_addr_t initrd_base,

113
hw/ppc4xx_pci.c
View File

@ -49,13 +49,14 @@ struct PCITargetMap {
#define PPC4xx_PCI_NR_PTMS 2
struct PPC4xxPCIState {
PCIHostState pci_state;
struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
qemu_irq irq[4];
PCIHostState pci_state;
PCIDevice *pci_dev;
MemoryRegion iomem_addr;
MemoryRegion iomem_regs;
MemoryRegion container;
MemoryRegion iomem;
};
typedef struct PPC4xxPCIState PPC4xxPCIState;
@ -83,8 +84,10 @@ typedef struct PPC4xxPCIState PPC4xxPCIState;
#define PCIL0_PTM1LA 0x34
#define PCIL0_PTM2MS 0x38
#define PCIL0_PTM2LA 0x3c
#define PCI_REG_BASE 0x800000
#define PCI_REG_SIZE 0x40
#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
unsigned size)
@ -314,7 +317,6 @@ static const VMStateDescription vmstate_ppc4xx_pci = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPC4xxPCIState),
VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
vmstate_pci_master_map,
struct PCIMasterMap),
@ -326,60 +328,63 @@ static const VMStateDescription vmstate_ppc4xx_pci = {
};
/* XXX Interrupt acknowledge cycles not supported. */
PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
target_phys_addr_t config_space,
target_phys_addr_t int_ack,
target_phys_addr_t special_cycle,
target_phys_addr_t registers)
static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
{
PPC4xxPCIState *controller;
static int ppc4xx_pci_id;
uint8_t *pci_conf;
PPC4xxPCIState *s;
PCIHostState *h;
PCIBus *b;
int i;
controller = g_malloc0(sizeof(PPC4xxPCIState));
h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
s = DO_UPCAST(PPC4xxPCIState, pci_state, h);
controller->pci_state.bus = pci_register_bus(NULL, "pci",
ppc4xx_pci_set_irq,
ppc4xx_pci_map_irq,
pci_irqs,
get_system_memory(),
get_system_io(),
0, 4);
for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
sysbus_init_irq(dev, &s->irq[i]);
}
controller->pci_dev = pci_register_device(controller->pci_state.bus,
"host bridge", sizeof(PCIDevice),
0, NULL, NULL);
pci_conf = controller->pci_dev->config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, ppc4xx_pci_set_irq,
ppc4xx_pci_map_irq, s->irq, get_system_memory(),
get_system_io(), 0, 4);
s->pci_state.bus = b;
/* CFGADDR */
memory_region_init_io(&controller->iomem_addr, &pci4xx_cfgaddr_ops,
controller, "pci.cfgaddr", 4);
memory_region_add_subregion(get_system_memory(),
config_space + PCIC0_CFGADDR,
&controller->iomem_addr);
pci_create_simple(b, 0, "ppc4xx-host-bridge");
/* CFGDATA */
memory_region_init_io(&controller->pci_state.data_mem,
&pci_host_data_be_ops,
&controller->pci_state, "pci-conf-data", 4);
memory_region_add_subregion(get_system_memory(),
config_space + PCIC0_CFGDATA,
&controller->pci_state.data_mem);
/* XXX split into 2 memory regions, one for config space, one for regs */
memory_region_init(&s->container, "pci-container", PCI_ALL_SIZE);
memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops, h,
"pci-conf-idx", 4);
memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
"pci-conf-data", 4);
memory_region_init_io(&s->iomem, &pci_reg_ops, s,
"pci.reg", PCI_REG_SIZE);
memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
sysbus_init_mmio(dev, &s->container);
qemu_register_reset(ppc4xx_pci_reset, s);
/* Internal registers */
memory_region_init_io(&controller->iomem_regs, &pci_reg_ops, controller,
"pci.regs", PCI_REG_SIZE);
memory_region_add_subregion(get_system_memory(), registers,
&controller->iomem_regs);
qemu_register_reset(ppc4xx_pci_reset, controller);
/* XXX load/save code not tested. */
vmstate_register(&controller->pci_dev->qdev, ppc4xx_pci_id++,
&vmstate_ppc4xx_pci, controller);
return controller->pci_state.bus;
return 0;
}
static PCIDeviceInfo ppc4xx_host_bridge_info = {
.qdev.name = "ppc4xx-host-bridge",
.qdev.desc = "Host bridge",
.qdev.size = sizeof(PCIDevice),
.vendor_id = PCI_VENDOR_ID_IBM,
.device_id = PCI_DEVICE_ID_IBM_440GX,
.class_id = PCI_CLASS_BRIDGE_OTHER,
};
static SysBusDeviceInfo ppc4xx_pcihost_info = {
.init = ppc4xx_pcihost_initfn,
.qdev.name = "ppc4xx-pcihost",
.qdev.size = sizeof(PPC4xxPCIState),
.qdev.vmsd = &vmstate_ppc4xx_pci,
};
static void ppc4xx_pci_register(void)
{
sysbus_register_withprop(&ppc4xx_pcihost_info);
pci_qdev_register(&ppc4xx_host_bridge_info);
}
device_init(ppc4xx_pci_register);