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tcg/riscv: Use atom_and_align_for_opc

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-04-19 11:50:36 +02:00
parent 1bac469719
commit 37e523f04b
1 changed files with 8 additions and 5 deletions
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13
tcg/riscv/tcg-target.c.inc
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@ -910,8 +910,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
{ {
TCGLabelQemuLdst *ldst = NULL; TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi); MemOp opc = get_memop(oi);
unsigned a_bits = get_alignment_bits(opc); TCGAtomAlign aa;
unsigned a_mask = (1u << a_bits) - 1; unsigned a_mask;
aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
a_mask = (1u << aa.align) - 1;
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
unsigned s_bits = opc & MO_SIZE; unsigned s_bits = opc & MO_SIZE;
@ -944,7 +947,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
* cross pages using the address of the last byte of the access. * cross pages using the address of the last byte of the access.
*/ */
addr_adj = addr_reg; addr_adj = addr_reg;
if (a_bits < s_bits) { if (a_mask < s_mask) {
addr_adj = TCG_REG_TMP0; addr_adj = TCG_REG_TMP0;
tcg_out_opc_imm(s, TARGET_LONG_BITS == 32 ? OPC_ADDIW : OPC_ADDI, tcg_out_opc_imm(s, TARGET_LONG_BITS == 32 ? OPC_ADDIW : OPC_ADDI,
addr_adj, addr_reg, s_mask - a_mask); addr_adj, addr_reg, s_mask - a_mask);
@ -983,8 +986,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addrlo_reg = addr_reg;
/* We are expecting a_bits max 7, so we can always use andi. */ /* We are expecting alignment max 7, so we can always use andi. */
tcg_debug_assert(a_bits < 12); tcg_debug_assert(a_mask == sextreg(a_mask, 0, 12));
tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask);
ldst->label_ptr[0] = s->code_ptr; ldst->label_ptr[0] = s->code_ptr;