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tcg/ppc: Use atom_and_align_for_opc

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-04-19 10:45:00 +02:00
parent c0cafab5a5
commit 1bac469719
1 changed files with 18 additions and 1 deletions
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19
tcg/ppc/tcg-target.c.inc
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@ -2015,6 +2015,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
typedef struct {
TCGReg base;
TCGReg index;
TCGAtomAlign aa;
} HostAddress;
bool tcg_target_has_memory_bswap(MemOp memop)
@ -2034,7 +2035,23 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
{
TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi);
unsigned a_bits = get_alignment_bits(opc);
MemOp a_bits;
/*
* Book II, Section 1.4, Single-Copy Atomicity, specifies:
*
* Before 3.0, "An access that is not atomic is performed as a set of
* smaller disjoint atomic accesses. In general, the number and alignment
* of these accesses are implementation-dependent." Thus MO_ATOM_IFALIGN.
*
* As of 3.0, "the non-atomic access is performed as described in
* the corresponding list", which matches MO_ATOM_SUBALIGN.
*/
h->aa = atom_and_align_for_opc(s, opc,
have_isa_3_00 ? MO_ATOM_SUBALIGN
: MO_ATOM_IFALIGN,
false);
a_bits = h->aa.align;
#ifdef CONFIG_SOFTMMU
int mem_index = get_mmuidx(oi);