hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour
The SSE-300's iokit-sysctl device is similar to the SSE-200, but some registers have moved address or have different behaviours. In this commit we add case statements for the registers where the SSE-300 and SSE-200 have the same behaviour. Some registers are the same on all SSE versions and so need no code change at all. Putting both of these categories together covers: 0x0 SECDBGSTAT 0x4 SECDBGSET 0x8 SECDBGCLR 0xc SCSECCTRL 0x10 CLK_CFG0 -- this is like SSE-200 FCLK_DIV but with a different set of clocks being controlled; our implementation is a dummy reads-as-written anyway 0x14 CLK_CFG1 -- similar to SSE-200 SYSCLK_DIV; our implementation is a dummy 0x18 CLK_FORCE -- similar to SSE-200 but different bit allocations; we have a dummy implementation 0x100 RESET_SYNDROME -- bit allocation differs from SSE-200 but our implementation is a dummy 0x104 RESET_MASK -- bit allocation differs from SSE-200 but our implementation is a dummy 0x108 SWRESET 0x10c GRETREG 0x200 PDCM_PD_SYS_SENSE -- some bit allocations differ, but our implementation is a dummy We also need to migrate the state of these registers which are shared between the SSE-200 and SSE-300, so update the vmstate 'needed' function to do this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-14-peter.maydell@linaro.org
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@ -105,6 +105,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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case ARMSSE_IOTKIT:
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goto bad_offset;
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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r = s->scsecctrl;
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break;
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default:
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@ -116,6 +117,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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case ARMSSE_IOTKIT:
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goto bad_offset;
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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r = s->fclk_div;
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break;
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default:
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@ -127,6 +129,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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case ARMSSE_IOTKIT:
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goto bad_offset;
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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r = s->sysclk_div;
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break;
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default:
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@ -138,6 +141,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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case ARMSSE_IOTKIT:
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goto bad_offset;
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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r = s->clock_force;
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break;
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default:
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@ -202,6 +206,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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case ARMSSE_IOTKIT:
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goto bad_offset;
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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r = s->pdcm_pd_sys_sense;
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break;
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default:
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@ -348,6 +353,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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case ARMSSE_IOTKIT:
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goto bad_offset;
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n");
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s->scsecctrl = value;
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break;
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@ -360,6 +366,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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case ARMSSE_IOTKIT:
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goto bad_offset;
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n");
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s->fclk_div = value;
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break;
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@ -372,6 +379,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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case ARMSSE_IOTKIT:
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goto bad_offset;
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
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s->sysclk_div = value;
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break;
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@ -384,6 +392,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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case ARMSSE_IOTKIT:
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goto bad_offset;
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
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s->clock_force = value;
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break;
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@ -420,6 +429,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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case ARMSSE_IOTKIT:
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goto bad_offset;
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
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s->pdcm_pd_sys_sense = value;
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@ -569,7 +579,7 @@ static bool sse200_needed(void *opaque)
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{
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IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
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return s->sse_version == ARMSSE_SSE200;
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return s->sse_version != ARMSSE_IOTKIT;
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}
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static const VMStateDescription iotkit_sysctl_sse200_vmstate = {
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