hw/timer/sse-timer: Model the SSE Subsystem System Timer
The SSE-300 includes some timers which are a different kind to those in the SSE-200. Model them. These timers are documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-13-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
0d10df3038
commit
0b8ceee822
@ -753,6 +753,8 @@ F: hw/misc/armsse-mhu.c
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F: include/hw/misc/armsse-mhu.h
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F: hw/timer/sse-counter.c
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F: include/hw/timer/sse-counter.h
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F: hw/timer/sse-timer.c
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F: include/hw/timer/sse-timer.h
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F: docs/system/arm/mps2.rst
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Musca
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@ -521,6 +521,7 @@ config ARMSSE
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select TZ_PPC
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select UNIMP
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select SSE_COUNTER
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select SSE_TIMER
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config ARMSSE_CPUID
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bool
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@ -45,5 +45,8 @@ config RENESAS_CMT
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config SSE_COUNTER
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bool
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config SSE_TIMER
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bool
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config AVR_TIMER16
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bool
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@ -33,6 +33,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_systmr.c'))
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softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_timer.c'))
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softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_timer.c'))
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softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c'))
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softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c'))
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softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c'))
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softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c'))
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470
hw/timer/sse-timer.c
Normal file
470
hw/timer/sse-timer.c
Normal file
@ -0,0 +1,470 @@
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/*
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* Arm SSE Subsystem System Timer
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*
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* Copyright (c) 2020 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "System timer" which is documented in
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* the Arm SSE-123 Example Subsystem Technical Reference Manual:
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* https://developer.arm.com/documentation/101370/latest/
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*
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* The timer is based around a simple 64-bit incrementing counter
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* (readable from CNTPCT_HI/LO). The timer fires when
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* Counter - CompareValue >= 0.
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* The CompareValue is guest-writable, via CNTP_CVAL_HI/LO.
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* CNTP_TVAL is an alternative view of the CompareValue defined by
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* TimerValue = CompareValue[31:0] - Counter[31:0]
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* which can be both read and written.
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* This part is similar to the generic timer in an Arm A-class CPU.
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*
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* The timer also has a separate auto-increment timer. When this
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* timer is enabled, then the AutoIncrValue is set to:
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* AutoIncrValue = Reload + Counter
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* and this timer fires when
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* Counter - AutoIncrValue >= 0
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* at which point, an interrupt is generated and the new AutoIncrValue
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* is calculated.
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* When the auto-increment timer is enabled, interrupt generation
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* via the compare/timervalue registers is disabled.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/timer.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/timer/sse-timer.h"
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#include "hw/timer/sse-counter.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/registerfields.h"
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#include "hw/clock.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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REG32(CNTPCT_LO, 0x0)
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REG32(CNTPCT_HI, 0x4)
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REG32(CNTFRQ, 0x10)
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REG32(CNTP_CVAL_LO, 0x20)
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REG32(CNTP_CVAL_HI, 0x24)
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REG32(CNTP_TVAL, 0x28)
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REG32(CNTP_CTL, 0x2c)
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FIELD(CNTP_CTL, ENABLE, 0, 1)
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FIELD(CNTP_CTL, IMASK, 1, 1)
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FIELD(CNTP_CTL, ISTATUS, 2, 1)
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REG32(CNTP_AIVAL_LO, 0x40)
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REG32(CNTP_AIVAL_HI, 0x44)
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REG32(CNTP_AIVAL_RELOAD, 0x48)
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REG32(CNTP_AIVAL_CTL, 0x4c)
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FIELD(CNTP_AIVAL_CTL, EN, 0, 1)
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FIELD(CNTP_AIVAL_CTL, CLR, 1, 1)
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REG32(CNTP_CFG, 0x50)
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FIELD(CNTP_CFG, AIVAL, 0, 4)
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#define R_CNTP_CFG_AIVAL_IMPLEMENTED 1
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REG32(PID4, 0xFD0)
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REG32(PID5, 0xFD4)
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REG32(PID6, 0xFD8)
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REG32(PID7, 0xFDC)
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REG32(PID0, 0xFE0)
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REG32(PID1, 0xFE4)
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REG32(PID2, 0xFE8)
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REG32(PID3, 0xFEC)
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REG32(CID0, 0xFF0)
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REG32(CID1, 0xFF4)
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REG32(CID2, 0xFF8)
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REG32(CID3, 0xFFC)
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/* PID/CID values */
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static const int timer_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0xb7, 0xb0, 0x0b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static bool sse_is_autoinc(SSETimer *s)
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{
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return (s->cntp_aival_ctl & R_CNTP_AIVAL_CTL_EN_MASK) != 0;
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}
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static bool sse_enabled(SSETimer *s)
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{
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return (s->cntp_ctl & R_CNTP_CTL_ENABLE_MASK) != 0;
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}
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static uint64_t sse_cntpct(SSETimer *s)
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{
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/* Return the CNTPCT value for the current time */
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return sse_counter_for_timestamp(s->counter,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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}
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static bool sse_timer_status(SSETimer *s)
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{
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/*
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* Return true if timer condition is met. This is used for both
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* the CNTP_CTL.ISTATUS bit and for whether (unless masked) we
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* assert our IRQ.
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* The documentation is unclear about the behaviour of ISTATUS when
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* in autoincrement mode; we assume that it follows CNTP_AIVAL_CTL.CLR
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* (ie whether the autoincrement timer is asserting the interrupt).
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*/
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if (!sse_enabled(s)) {
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return false;
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}
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if (sse_is_autoinc(s)) {
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return s->cntp_aival_ctl & R_CNTP_AIVAL_CTL_CLR_MASK;
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} else {
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return sse_cntpct(s) >= s->cntp_cval;
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}
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}
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static void sse_update_irq(SSETimer *s)
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{
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bool irqstate = (!(s->cntp_ctl & R_CNTP_CTL_IMASK_MASK) &&
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sse_timer_status(s));
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qemu_set_irq(s->irq, irqstate);
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}
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static void sse_set_timer(SSETimer *s, uint64_t nexttick)
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{
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/* Set the timer to expire at nexttick */
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uint64_t expiry = sse_counter_tick_to_time(s->counter, nexttick);
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if (expiry <= INT64_MAX) {
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timer_mod_ns(&s->timer, expiry);
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} else {
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/*
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* nexttick is so far in the future that it would overflow the
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* signed 64-bit range of a QEMUTimer. Since timer_mod_ns()
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* expiry times are absolute, not relative, we are never going
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* to be able to set the timer to this value, so we must just
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* assume that guest execution can never run so long that it
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* reaches the theoretical point when the timer fires.
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* This is also the code path for "counter is not running",
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* which is signalled by expiry == UINT64_MAX.
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*/
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timer_del(&s->timer);
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}
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}
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static void sse_recalc_timer(SSETimer *s)
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{
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/* Recalculate the normal timer */
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uint64_t count, nexttick;
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if (sse_is_autoinc(s)) {
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return;
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}
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if (!sse_enabled(s)) {
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timer_del(&s->timer);
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return;
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}
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count = sse_cntpct(s);
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if (count >= s->cntp_cval) {
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/*
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* Timer condition already met. In theory we have a transition when
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* the count rolls back over to 0, but that is so far in the future
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* that it is not representable as a timer_mod() expiry, so in
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* fact sse_set_timer() will always just delete the timer.
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*/
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nexttick = UINT64_MAX;
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} else {
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/* Next transition is when count hits cval */
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nexttick = s->cntp_cval;
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}
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sse_set_timer(s, nexttick);
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sse_update_irq(s);
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}
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static void sse_autoinc(SSETimer *s)
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{
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/* Auto-increment the AIVAL, and set the timer accordingly */
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s->cntp_aival = sse_cntpct(s) + s->cntp_aival_reload;
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sse_set_timer(s, s->cntp_aival);
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}
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static void sse_timer_cb(void *opaque)
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{
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SSETimer *s = SSE_TIMER(opaque);
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if (sse_is_autoinc(s)) {
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uint64_t count = sse_cntpct(s);
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if (count >= s->cntp_aival) {
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/* Timer condition met, set CLR and do another autoinc */
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s->cntp_aival_ctl |= R_CNTP_AIVAL_CTL_CLR_MASK;
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s->cntp_aival = count + s->cntp_aival_reload;
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}
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sse_set_timer(s, s->cntp_aival);
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sse_update_irq(s);
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} else {
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sse_recalc_timer(s);
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}
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}
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static uint64_t sse_timer_read(void *opaque, hwaddr offset, unsigned size)
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{
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SSETimer *s = SSE_TIMER(opaque);
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uint64_t r;
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switch (offset) {
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case A_CNTPCT_LO:
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r = extract64(sse_cntpct(s), 0, 32);
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break;
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case A_CNTPCT_HI:
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r = extract64(sse_cntpct(s), 32, 32);
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break;
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case A_CNTFRQ:
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r = s->cntfrq;
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break;
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case A_CNTP_CVAL_LO:
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r = extract64(s->cntp_cval, 0, 32);
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break;
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case A_CNTP_CVAL_HI:
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r = extract64(s->cntp_cval, 32, 32);
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break;
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case A_CNTP_TVAL:
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r = extract64(s->cntp_cval - sse_cntpct(s), 0, 32);
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break;
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case A_CNTP_CTL:
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r = s->cntp_ctl;
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if (sse_timer_status(s)) {
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r |= R_CNTP_CTL_ISTATUS_MASK;
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}
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break;
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case A_CNTP_AIVAL_LO:
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r = extract64(s->cntp_aival, 0, 32);
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break;
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case A_CNTP_AIVAL_HI:
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r = extract64(s->cntp_aival, 32, 32);
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break;
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case A_CNTP_AIVAL_RELOAD:
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r = s->cntp_aival_reload;
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break;
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case A_CNTP_AIVAL_CTL:
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/*
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* All the bits of AIVAL_CTL are documented as WO, but this is probably
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* a documentation error. We implement them as readable.
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*/
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r = s->cntp_aival_ctl;
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break;
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case A_CNTP_CFG:
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r = R_CNTP_CFG_AIVAL_IMPLEMENTED << R_CNTP_CFG_AIVAL_SHIFT;
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break;
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case A_PID4 ... A_CID3:
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r = timer_id[(offset - A_PID4) / 4];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE System Timer read: bad offset 0x%x",
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(unsigned) offset);
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r = 0;
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break;
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}
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trace_sse_timer_read(offset, r, size);
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return r;
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}
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static void sse_timer_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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SSETimer *s = SSE_TIMER(opaque);
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trace_sse_timer_write(offset, value, size);
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switch (offset) {
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case A_CNTFRQ:
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s->cntfrq = value;
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break;
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case A_CNTP_CVAL_LO:
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s->cntp_cval = deposit64(s->cntp_cval, 0, 32, value);
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sse_recalc_timer(s);
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break;
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case A_CNTP_CVAL_HI:
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s->cntp_cval = deposit64(s->cntp_cval, 32, 32, value);
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sse_recalc_timer(s);
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break;
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case A_CNTP_TVAL:
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s->cntp_cval = sse_cntpct(s) + sextract64(value, 0, 32);
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sse_recalc_timer(s);
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break;
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case A_CNTP_CTL:
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{
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uint32_t old_ctl = s->cntp_ctl;
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value &= R_CNTP_CTL_ENABLE_MASK | R_CNTP_CTL_IMASK_MASK;
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s->cntp_ctl = value;
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if ((old_ctl ^ s->cntp_ctl) & R_CNTP_CTL_ENABLE_MASK) {
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if (sse_enabled(s)) {
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if (sse_is_autoinc(s)) {
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sse_autoinc(s);
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} else {
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sse_recalc_timer(s);
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}
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}
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}
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sse_update_irq(s);
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break;
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}
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case A_CNTP_AIVAL_RELOAD:
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s->cntp_aival_reload = value;
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break;
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case A_CNTP_AIVAL_CTL:
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{
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uint32_t old_ctl = s->cntp_aival_ctl;
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/* EN bit is writeable; CLR bit is write-0-to-clear, write-1-ignored */
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s->cntp_aival_ctl &= ~R_CNTP_AIVAL_CTL_EN_MASK;
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s->cntp_aival_ctl |= value & R_CNTP_AIVAL_CTL_EN_MASK;
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if (!(value & R_CNTP_AIVAL_CTL_CLR_MASK)) {
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s->cntp_aival_ctl &= ~R_CNTP_AIVAL_CTL_CLR_MASK;
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}
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if ((old_ctl ^ s->cntp_aival_ctl) & R_CNTP_AIVAL_CTL_EN_MASK) {
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/* Auto-increment toggled on/off */
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if (sse_enabled(s)) {
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if (sse_is_autoinc(s)) {
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sse_autoinc(s);
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} else {
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sse_recalc_timer(s);
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}
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}
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}
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sse_update_irq(s);
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break;
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}
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case A_CNTPCT_LO:
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case A_CNTPCT_HI:
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case A_CNTP_CFG:
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case A_CNTP_AIVAL_LO:
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case A_CNTP_AIVAL_HI:
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case A_PID4 ... A_CID3:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE System Timer write: write to RO offset 0x%x\n",
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(unsigned)offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE System Timer write: bad offset 0x%x\n",
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(unsigned)offset);
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break;
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}
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}
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static const MemoryRegionOps sse_timer_ops = {
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.read = sse_timer_read,
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.write = sse_timer_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void sse_timer_reset(DeviceState *dev)
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{
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SSETimer *s = SSE_TIMER(dev);
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trace_sse_timer_reset();
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timer_del(&s->timer);
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s->cntfrq = 0;
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s->cntp_ctl = 0;
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s->cntp_cval = 0;
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s->cntp_aival = 0;
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s->cntp_aival_ctl = 0;
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s->cntp_aival_reload = 0;
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}
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static void sse_timer_counter_callback(Notifier *notifier, void *data)
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{
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SSETimer *s = container_of(notifier, SSETimer, counter_notifier);
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/* System counter told us we need to recalculate */
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if (sse_enabled(s)) {
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if (sse_is_autoinc(s)) {
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sse_set_timer(s, s->cntp_aival);
|
||||
} else {
|
||||
sse_recalc_timer(s);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void sse_timer_init(Object *obj)
|
||||
{
|
||||
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||||
SSETimer *s = SSE_TIMER(obj);
|
||||
|
||||
memory_region_init_io(&s->iomem, obj, &sse_timer_ops,
|
||||
s, "sse-timer", 0x1000);
|
||||
sysbus_init_mmio(sbd, &s->iomem);
|
||||
sysbus_init_irq(sbd, &s->irq);
|
||||
}
|
||||
|
||||
static void sse_timer_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
SSETimer *s = SSE_TIMER(dev);
|
||||
|
||||
if (!s->counter) {
|
||||
error_setg(errp, "counter property was not set");
|
||||
}
|
||||
|
||||
s->counter_notifier.notify = sse_timer_counter_callback;
|
||||
sse_counter_register_consumer(s->counter, &s->counter_notifier);
|
||||
|
||||
timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL, sse_timer_cb, s);
|
||||
}
|
||||
|
||||
static const VMStateDescription sse_timer_vmstate = {
|
||||
.name = "sse-timer",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_TIMER(timer, SSETimer),
|
||||
VMSTATE_UINT32(cntfrq, SSETimer),
|
||||
VMSTATE_UINT32(cntp_ctl, SSETimer),
|
||||
VMSTATE_UINT64(cntp_cval, SSETimer),
|
||||
VMSTATE_UINT64(cntp_aival, SSETimer),
|
||||
VMSTATE_UINT32(cntp_aival_ctl, SSETimer),
|
||||
VMSTATE_UINT32(cntp_aival_reload, SSETimer),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static Property sse_timer_properties[] = {
|
||||
DEFINE_PROP_LINK("counter", SSETimer, counter, TYPE_SSE_COUNTER, SSECounter *),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void sse_timer_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->realize = sse_timer_realize;
|
||||
dc->vmsd = &sse_timer_vmstate;
|
||||
dc->reset = sse_timer_reset;
|
||||
device_class_set_props(dc, sse_timer_properties);
|
||||
}
|
||||
|
||||
static const TypeInfo sse_timer_info = {
|
||||
.name = TYPE_SSE_TIMER,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(SSETimer),
|
||||
.instance_init = sse_timer_init,
|
||||
.class_init = sse_timer_class_init,
|
||||
};
|
||||
|
||||
static void sse_timer_register_types(void)
|
||||
{
|
||||
type_register_static(&sse_timer_info);
|
||||
}
|
||||
|
||||
type_init(sse_timer_register_types);
|
||||
@ -100,3 +100,8 @@ sse_counter_control_write(uint64_t offset, uint64_t data, unsigned size) "SSE sy
|
||||
sse_counter_status_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||
sse_counter_status_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status frame write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||
sse_counter_reset(void) "SSE system counter: reset"
|
||||
|
||||
# sse_timer.c
|
||||
sse_timer_read(uint64_t offset, uint64_t data, unsigned size) "SSE system timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||
sse_timer_write(uint64_t offset, uint64_t data, unsigned size) "SSE system timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||
sse_timer_reset(void) "SSE system timer: reset"
|
||||
|
||||
53
include/hw/timer/sse-timer.h
Normal file
53
include/hw/timer/sse-timer.h
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Arm SSE Subsystem System Timer
|
||||
*
|
||||
* Copyright (c) 2020 Linaro Limited
|
||||
* Written by Peter Maydell
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This is a model of the "System timer" which is documented in
|
||||
* the Arm SSE-123 Example Subsystem Technical Reference Manual:
|
||||
* https://developer.arm.com/documentation/101370/latest/
|
||||
*
|
||||
* QEMU interface:
|
||||
* + QOM property "counter": link property to be set to the
|
||||
* TYPE_SSE_COUNTER timestamp counter device this timer runs off
|
||||
* + sysbus MMIO region 0: the register bank
|
||||
* + sysbus IRQ 0: timer interrupt
|
||||
*/
|
||||
|
||||
#ifndef SSE_TIMER_H
|
||||
#define SSE_TIMER_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "qom/object.h"
|
||||
#include "hw/timer/sse-counter.h"
|
||||
|
||||
#define TYPE_SSE_TIMER "sse-timer"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(SSETimer, SSE_TIMER)
|
||||
|
||||
struct SSETimer {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
MemoryRegion iomem;
|
||||
qemu_irq irq;
|
||||
SSECounter *counter;
|
||||
QEMUTimer timer;
|
||||
Notifier counter_notifier;
|
||||
|
||||
uint32_t cntfrq;
|
||||
uint32_t cntp_ctl;
|
||||
uint64_t cntp_cval;
|
||||
uint64_t cntp_aival;
|
||||
uint32_t cntp_aival_ctl;
|
||||
uint32_t cntp_aival_reload;
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user