mirror of https://gitlab.com/qemu-project/qemu
hw/timer/sse-counter: Model the SSE Subsystem System Counter
The SSE-300 includes a counter module; implement a model of it. This counter is documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-12-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
446587a914
commit
0d10df3038
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@ -751,6 +751,8 @@ F: hw/misc/armsse-cpuid.c
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F: include/hw/misc/armsse-cpuid.h
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F: hw/misc/armsse-mhu.c
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F: include/hw/misc/armsse-mhu.h
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F: hw/timer/sse-counter.c
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F: include/hw/timer/sse-counter.h
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F: docs/system/arm/mps2.rst
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Musca
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@ -520,6 +520,7 @@ config ARMSSE
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select TZ_MSC
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select TZ_PPC
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select UNIMP
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select SSE_COUNTER
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config ARMSSE_CPUID
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bool
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@ -42,5 +42,8 @@ config RENESAS_TMR
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config RENESAS_CMT
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bool
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config SSE_COUNTER
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bool
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config AVR_TIMER16
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bool
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@ -32,6 +32,7 @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_timer.c'))
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softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_systmr.c'))
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softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_timer.c'))
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softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_timer.c'))
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softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c'))
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softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c'))
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softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c'))
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@ -0,0 +1,474 @@
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/*
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* Arm SSE Subsystem System Counter
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*
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* Copyright (c) 2020 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "System counter" which is documented in
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* the Arm SSE-123 Example Subsystem Technical Reference Manual:
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* https://developer.arm.com/documentation/101370/latest/
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*
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* The system counter is a non-stop 64-bit up-counter. It provides
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* this count value to other devices like the SSE system timer,
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* which are driven by this system timestamp rather than directly
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* from a clock. Internally to the counter the count is actually
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* 88-bit precision (64.24 fixed point), with a programmable scale factor.
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*
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* The hardware has the optional feature that it supports dynamic
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* clock switching, where two clock inputs are connected, and which
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* one is used is selected via a CLKSEL input signal. Since the
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* users of this device in QEMU don't use this feature, we only model
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* the HWCLKSW=0 configuration.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/timer.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/timer/sse-counter.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/registerfields.h"
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#include "hw/clock.h"
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#include "hw/qdev-clock.h"
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#include "migration/vmstate.h"
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/* Registers in the control frame */
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REG32(CNTCR, 0x0)
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FIELD(CNTCR, EN, 0, 1)
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FIELD(CNTCR, HDBG, 1, 1)
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FIELD(CNTCR, SCEN, 2, 1)
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FIELD(CNTCR, INTRMASK, 3, 1)
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FIELD(CNTCR, PSLVERRDIS, 4, 1)
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FIELD(CNTCR, INTRCLR, 5, 1)
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/*
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* Although CNTCR defines interrupt-related bits, the counter doesn't
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* appear to actually have an interrupt output. So INTRCLR is
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* effectively a RAZ/WI bit, as are the reserved bits [31:6].
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*/
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#define CNTCR_VALID_MASK (R_CNTCR_EN_MASK | R_CNTCR_HDBG_MASK | \
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R_CNTCR_SCEN_MASK | R_CNTCR_INTRMASK_MASK | \
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R_CNTCR_PSLVERRDIS_MASK)
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REG32(CNTSR, 0x4)
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REG32(CNTCV_LO, 0x8)
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REG32(CNTCV_HI, 0xc)
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REG32(CNTSCR, 0x10) /* Aliased with CNTSCR0 */
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REG32(CNTID, 0x1c)
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FIELD(CNTID, CNTSC, 0, 4)
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FIELD(CNTID, CNTCS, 16, 1)
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FIELD(CNTID, CNTSELCLK, 17, 2)
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FIELD(CNTID, CNTSCR_OVR, 19, 1)
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REG32(CNTSCR0, 0xd0)
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REG32(CNTSCR1, 0xd4)
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/* Registers in the status frame */
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REG32(STATUS_CNTCV_LO, 0x0)
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REG32(STATUS_CNTCV_HI, 0x4)
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/* Standard ID registers, present in both frames */
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REG32(PID4, 0xFD0)
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REG32(PID5, 0xFD4)
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REG32(PID6, 0xFD8)
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REG32(PID7, 0xFDC)
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REG32(PID0, 0xFE0)
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REG32(PID1, 0xFE4)
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REG32(PID2, 0xFE8)
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REG32(PID3, 0xFEC)
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REG32(CID0, 0xFF0)
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REG32(CID1, 0xFF4)
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REG32(CID2, 0xFF8)
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REG32(CID3, 0xFFC)
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/* PID/CID values */
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static const int control_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0xba, 0xb0, 0x0b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static const int status_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0xbb, 0xb0, 0x0b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static void sse_counter_notify_users(SSECounter *s)
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{
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/*
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* Notify users of the count timestamp that they may
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* need to recalculate.
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*/
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notifier_list_notify(&s->notifier_list, NULL);
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}
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static bool sse_counter_enabled(SSECounter *s)
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{
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return (s->cntcr & R_CNTCR_EN_MASK) != 0;
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}
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uint64_t sse_counter_tick_to_time(SSECounter *s, uint64_t tick)
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{
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if (!sse_counter_enabled(s)) {
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return UINT64_MAX;
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}
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tick -= s->ticks_then;
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if (s->cntcr & R_CNTCR_SCEN_MASK) {
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/* Adjust the tick count to account for the scale factor */
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tick = muldiv64(tick, 0x01000000, s->cntscr0);
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}
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return s->ns_then + clock_ticks_to_ns(s->clk, tick);
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}
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void sse_counter_register_consumer(SSECounter *s, Notifier *notifier)
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{
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/*
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* For the moment we assume that both we and the devices
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* which consume us last for the life of the simulation,
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* and so there is no mechanism for removing a notifier.
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*/
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notifier_list_add(&s->notifier_list, notifier);
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}
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uint64_t sse_counter_for_timestamp(SSECounter *s, uint64_t now)
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{
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/* Return the CNTCV value for a particular timestamp (clock ns value). */
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uint64_t ticks;
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if (!sse_counter_enabled(s)) {
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/* Counter is disabled and does not increment */
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return s->ticks_then;
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}
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ticks = clock_ns_to_ticks(s->clk, now - s->ns_then);
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if (s->cntcr & R_CNTCR_SCEN_MASK) {
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/*
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* Scaling is enabled. The CNTSCR value is the amount added to
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* the underlying 88-bit counter for every tick of the
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* underlying clock; CNTCV is the top 64 bits of that full
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* 88-bit value. Multiplying the tick count by CNTSCR tells us
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* how much the full 88-bit counter has moved on; we then
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* divide that by 0x01000000 to find out how much the 64-bit
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* visible portion has advanced. muldiv64() gives us the
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* necessary at-least-88-bit precision for the intermediate
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* result.
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*/
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ticks = muldiv64(ticks, s->cntscr0, 0x01000000);
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}
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return s->ticks_then + ticks;
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}
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static uint64_t sse_cntcv(SSECounter *s)
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{
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/* Return the CNTCV value for the current time */
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return sse_counter_for_timestamp(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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}
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static void sse_write_cntcv(SSECounter *s, uint32_t value, unsigned startbit)
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{
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/*
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* Write one 32-bit half of the counter value; startbit is the
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* bit position of this half in the 64-bit word, either 0 or 32.
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*/
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint64_t cntcv = sse_counter_for_timestamp(s, now);
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cntcv = deposit64(cntcv, startbit, 32, value);
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s->ticks_then = cntcv;
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s->ns_then = now;
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sse_counter_notify_users(s);
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}
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static uint64_t sse_counter_control_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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SSECounter *s = SSE_COUNTER(opaque);
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uint64_t r;
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switch (offset) {
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case A_CNTCR:
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r = s->cntcr;
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break;
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case A_CNTSR:
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/*
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* The only bit here is DBGH, indicating that the counter has been
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* halted via the Halt-on-Debug signal. We don't implement halting
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* debug, so the whole register always reads as zero.
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*/
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r = 0;
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break;
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case A_CNTCV_LO:
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r = extract64(sse_cntcv(s), 0, 32);
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break;
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case A_CNTCV_HI:
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r = extract64(sse_cntcv(s), 32, 32);
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break;
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case A_CNTID:
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/*
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* For our implementation:
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* - CNTSCR can only be written when CNTCR.EN == 0
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* - HWCLKSW=0, so selected clock is always CLK0
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* - counter scaling is implemented
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*/
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r = (1 << R_CNTID_CNTSELCLK_SHIFT) | (1 << R_CNTID_CNTSC_SHIFT);
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break;
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case A_CNTSCR:
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case A_CNTSCR0:
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r = s->cntscr0;
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break;
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case A_CNTSCR1:
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/* If HWCLKSW == 0, CNTSCR1 is RAZ/WI */
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r = 0;
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break;
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case A_PID4 ... A_CID3:
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r = control_id[(offset - A_PID4) / 4];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE System Counter control frame read: bad offset 0x%x",
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(unsigned)offset);
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r = 0;
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break;
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}
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trace_sse_counter_control_read(offset, r, size);
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return r;
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}
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static void sse_counter_control_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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SSECounter *s = SSE_COUNTER(opaque);
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trace_sse_counter_control_write(offset, value, size);
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switch (offset) {
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case A_CNTCR:
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/*
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* Although CNTCR defines interrupt-related bits, the counter doesn't
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* appear to actually have an interrupt output. So INTRCLR is
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* effectively a RAZ/WI bit, as are the reserved bits [31:6].
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* The documentation does not explicitly say so, but we assume
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* that changing the scale factor while the counter is enabled
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* by toggling CNTCR.SCEN has the same behaviour (making the counter
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* value UNKNOWN) as changing it by writing to CNTSCR, and so we
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* don't need to try to recalculate for that case.
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*/
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value &= CNTCR_VALID_MASK;
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if ((value ^ s->cntcr) & R_CNTCR_EN_MASK) {
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/*
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* Whether the counter is being enabled or disabled, the
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* required action is the same: sync the (ns_then, ticks_then)
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* tuple.
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*/
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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s->ticks_then = sse_counter_for_timestamp(s, now);
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s->ns_then = now;
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sse_counter_notify_users(s);
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}
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s->cntcr = value;
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break;
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case A_CNTCV_LO:
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sse_write_cntcv(s, value, 0);
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break;
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case A_CNTCV_HI:
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sse_write_cntcv(s, value, 32);
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break;
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case A_CNTSCR:
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case A_CNTSCR0:
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/*
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* If the scale registers are changed when the counter is enabled,
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* the count value becomes UNKNOWN. So we don't try to recalculate
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* anything here but only do it on a write to CNTCR.EN.
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*/
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s->cntscr0 = value;
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break;
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case A_CNTSCR1:
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/* If HWCLKSW == 0, CNTSCR1 is RAZ/WI */
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break;
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case A_CNTSR:
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case A_CNTID:
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case A_PID4 ... A_CID3:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE System Counter control frame: write to RO offset 0x%x\n",
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(unsigned)offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE System Counter control frame: write to bad offset 0x%x\n",
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(unsigned)offset);
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break;
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}
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}
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static uint64_t sse_counter_status_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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SSECounter *s = SSE_COUNTER(opaque);
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uint64_t r;
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switch (offset) {
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case A_STATUS_CNTCV_LO:
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r = extract64(sse_cntcv(s), 0, 32);
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break;
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case A_STATUS_CNTCV_HI:
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r = extract64(sse_cntcv(s), 32, 32);
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break;
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case A_PID4 ... A_CID3:
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r = status_id[(offset - A_PID4) / 4];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE System Counter status frame read: bad offset 0x%x",
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(unsigned)offset);
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r = 0;
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break;
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}
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trace_sse_counter_status_read(offset, r, size);
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return r;
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}
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static void sse_counter_status_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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trace_sse_counter_status_write(offset, value, size);
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switch (offset) {
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case A_STATUS_CNTCV_LO:
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case A_STATUS_CNTCV_HI:
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case A_PID4 ... A_CID3:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE System Counter status frame: write to RO offset 0x%x\n",
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(unsigned)offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE System Counter status frame: write to bad offset 0x%x\n",
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(unsigned)offset);
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break;
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}
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}
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static const MemoryRegionOps sse_counter_control_ops = {
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.read = sse_counter_control_read,
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.write = sse_counter_control_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static const MemoryRegionOps sse_counter_status_ops = {
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.read = sse_counter_status_read,
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.write = sse_counter_status_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void sse_counter_reset(DeviceState *dev)
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{
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SSECounter *s = SSE_COUNTER(dev);
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trace_sse_counter_reset();
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s->cntcr = 0;
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s->cntscr0 = 0x01000000;
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s->ns_then = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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s->ticks_then = 0;
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}
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static void sse_clk_callback(void *opaque, ClockEvent event)
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{
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SSECounter *s = SSE_COUNTER(opaque);
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uint64_t now;
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switch (event) {
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case ClockPreUpdate:
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/*
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* Before the clock period updates, set (ticks_then, ns_then)
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* to the current time and tick count (as calculated with
|
||||
* the old clock period).
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||||
*/
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if (sse_counter_enabled(s)) {
|
||||
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
||||
s->ticks_then = sse_counter_for_timestamp(s, now);
|
||||
s->ns_then = now;
|
||||
}
|
||||
break;
|
||||
case ClockUpdate:
|
||||
sse_counter_notify_users(s);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void sse_counter_init(Object *obj)
|
||||
{
|
||||
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||||
SSECounter *s = SSE_COUNTER(obj);
|
||||
|
||||
notifier_list_init(&s->notifier_list);
|
||||
|
||||
s->clk = qdev_init_clock_in(DEVICE(obj), "CLK", sse_clk_callback, s,
|
||||
ClockPreUpdate | ClockUpdate);
|
||||
memory_region_init_io(&s->control_mr, obj, &sse_counter_control_ops,
|
||||
s, "sse-counter-control", 0x1000);
|
||||
memory_region_init_io(&s->status_mr, obj, &sse_counter_status_ops,
|
||||
s, "sse-counter-status", 0x1000);
|
||||
sysbus_init_mmio(sbd, &s->control_mr);
|
||||
sysbus_init_mmio(sbd, &s->status_mr);
|
||||
}
|
||||
|
||||
static void sse_counter_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
SSECounter *s = SSE_COUNTER(dev);
|
||||
|
||||
if (!clock_has_source(s->clk)) {
|
||||
error_setg(errp, "SSE system counter: CLK must be connected");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static const VMStateDescription sse_counter_vmstate = {
|
||||
.name = "sse-counter",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_CLOCK(clk, SSECounter),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static void sse_counter_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->realize = sse_counter_realize;
|
||||
dc->vmsd = &sse_counter_vmstate;
|
||||
dc->reset = sse_counter_reset;
|
||||
}
|
||||
|
||||
static const TypeInfo sse_counter_info = {
|
||||
.name = TYPE_SSE_COUNTER,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(SSECounter),
|
||||
.instance_init = sse_counter_init,
|
||||
.class_init = sse_counter_class_init,
|
||||
};
|
||||
|
||||
static void sse_counter_register_types(void)
|
||||
{
|
||||
type_register_static(&sse_counter_info);
|
||||
}
|
||||
|
||||
type_init(sse_counter_register_types);
|
||||
|
|
@ -93,3 +93,10 @@ avr_timer16_interrupt_count(uint8_t cnt) "count: %u"
|
|||
avr_timer16_interrupt_overflow(const char *reason) "overflow: %s"
|
||||
avr_timer16_next_alarm(uint64_t delay_ns) "next alarm: %" PRIu64 " ns from now"
|
||||
avr_timer16_clksrc_update(uint64_t freq_hz, uint64_t period_ns, uint64_t delay_s) "timer frequency: %" PRIu64 " Hz, period: %" PRIu64 " ns (%" PRId64 " us)"
|
||||
|
||||
# sse_counter.c
|
||||
sse_counter_control_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter control frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||
sse_counter_control_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter control framen write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||
sse_counter_status_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||
sse_counter_status_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status frame write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||
sse_counter_reset(void) "SSE system counter: reset"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* Arm SSE Subsystem System Counter
|
||||
*
|
||||
* Copyright (c) 2020 Linaro Limited
|
||||
* Written by Peter Maydell
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This is a model of the "System counter" which is documented in
|
||||
* the Arm SSE-123 Example Subsystem Technical Reference Manual:
|
||||
* https://developer.arm.com/documentation/101370/latest/
|
||||
*
|
||||
* QEMU interface:
|
||||
* + Clock input "CLK": clock
|
||||
* + sysbus MMIO region 0: the control register frame
|
||||
* + sysbus MMIO region 1: the status register frame
|
||||
*
|
||||
* Consumers of the system counter's timestamp, such as the SSE
|
||||
* System Timer device, can also use the APIs sse_counter_for_timestamp(),
|
||||
* sse_counter_tick_to_time() and sse_counter_register_consumer() to
|
||||
* interact with an instance of the System Counter. Generally the
|
||||
* consumer device should have a QOM link property which the board
|
||||
* code can set to the appropriate instance of the system counter.
|
||||
*/
|
||||
|
||||
#ifndef SSE_COUNTER_H
|
||||
#define SSE_COUNTER_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "qom/object.h"
|
||||
#include "qemu/notify.h"
|
||||
|
||||
#define TYPE_SSE_COUNTER "sse-counter"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(SSECounter, SSE_COUNTER)
|
||||
|
||||
struct SSECounter {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
MemoryRegion control_mr;
|
||||
MemoryRegion status_mr;
|
||||
Clock *clk;
|
||||
NotifierList notifier_list;
|
||||
|
||||
uint32_t cntcr;
|
||||
uint32_t cntscr0;
|
||||
|
||||
/*
|
||||
* These are used for handling clock frequency changes: they are a
|
||||
* tuple of (QEMU_CLOCK_VIRTUAL timestamp, CNTCV at that time),
|
||||
* taken when the clock frequency changes. sse_cntcv() needs them
|
||||
* to calculate the current CNTCV.
|
||||
*/
|
||||
uint64_t ns_then;
|
||||
uint64_t ticks_then;
|
||||
};
|
||||
|
||||
/*
|
||||
* These functions are the interface by which a consumer of
|
||||
* the system timestamp (such as the SSE system timer device)
|
||||
* can communicate with the SSECounter.
|
||||
*/
|
||||
|
||||
/**
|
||||
* sse_counter_for_timestamp:
|
||||
* @counter: SSECounter
|
||||
* @ns: timestamp of QEMU_CLOCK_VIRTUAL in nanoseconds
|
||||
*
|
||||
* Returns the value of the timestamp counter at the specified
|
||||
* point in time (assuming that no changes to scale factor, enable, etc
|
||||
* happen in the meantime).
|
||||
*/
|
||||
uint64_t sse_counter_for_timestamp(SSECounter *counter, uint64_t ns);
|
||||
|
||||
/**
|
||||
* sse_counter_tick_to_time:
|
||||
* @counter: SSECounter
|
||||
* @tick: tick value
|
||||
*
|
||||
* Returns the time (a QEMU_CLOCK_VIRTUAL timestamp in nanoseconds)
|
||||
* when the timestamp counter will reach the specified tick count.
|
||||
* If the counter is not currently running, returns UINT64_MAX.
|
||||
*/
|
||||
uint64_t sse_counter_tick_to_time(SSECounter *counter, uint64_t tick);
|
||||
|
||||
/**
|
||||
* sse_counter_register_consumer:
|
||||
* @counter: SSECounter
|
||||
* @notifier: Notifier which is notified on counter changes
|
||||
*
|
||||
* Registers @notifier with the SSECounter. When the counter's
|
||||
* configuration changes in a way that might invalidate information
|
||||
* previously returned via sse_counter_for_timestamp() or
|
||||
* sse_counter_tick_to_time(), the notifier will be called.
|
||||
* Devices which consume the timestamp counter can use this as
|
||||
* a cue to recalculate timer events.
|
||||
*/
|
||||
void sse_counter_register_consumer(SSECounter *counter, Notifier *notifier);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue