mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

semihosting: Split out common-semi-target.h

Browse Source 
Move the ARM and RISCV specific helpers into
their own header file.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Luc Michel <lmichel@kalray.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-06-07 10:31:22 -07:00
parent a1df4bab43
commit 1b3b7693b7
3 changed files with 113 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

94
semihosting/arm-compat-semi.c
View File

@ -46,9 +46,6 @@
#else #else
#include "qemu/cutils.h" #include "qemu/cutils.h"
#include "hw/loader.h" #include "hw/loader.h"
#ifdef TARGET_ARM
#include "hw/arm/boot.h"
#endif
#include "hw/boards.h" #include "hw/boards.h"
#endif #endif
@ -182,96 +179,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs)
#endif #endif
#ifdef TARGET_ARM #include "common-semi-target.h"
static inline target_ulong
common_semi_arg(CPUState *cs, int argno)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
if (is_a64(env)) {
return env->xregs[argno];
} else {
return env->regs[argno];
}
}
static inline void
common_semi_set_ret(CPUState *cs, target_ulong ret)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
if (is_a64(env)) {
env->xregs[0] = ret;
} else {
env->regs[0] = ret;
}
}
static inline bool
common_semi_sys_exit_extended(CPUState *cs, int nr)
{
return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr));
}
static inline bool is_64bit_semihosting(CPUArchState *env)
{
return is_a64(env);
}
static inline target_ulong common_semi_stack_bottom(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
return is_a64(env) ? env->xregs[31] : env->regs[13];
}
static inline bool common_semi_has_synccache(CPUArchState *env)
{
/* Ok for A64, invalid for A32/T32. */
return is_a64(env);
}
#endif /* TARGET_ARM */
#ifdef TARGET_RISCV
static inline target_ulong
common_semi_arg(CPUState *cs, int argno)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
return env->gpr[xA0 + argno];
}
static inline void
common_semi_set_ret(CPUState *cs, target_ulong ret)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->gpr[xA0] = ret;
}
static inline bool
common_semi_sys_exit_extended(CPUState *cs, int nr)
{
return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8);
}
static inline bool is_64bit_semihosting(CPUArchState *env)
{
return riscv_cpu_mxl(env) != MXL_RV32;
}
static inline target_ulong common_semi_stack_bottom(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
return env->gpr[xSP];
}
static inline bool common_semi_has_synccache(CPUArchState *env)
{
return true;
}
#endif
/* /*
* The semihosting API has no concept of its errno being thread-safe, * The semihosting API has no concept of its errno being thread-safe,

62
target/arm/common-semi-target.h Normal file
View File

@ -0,0 +1,62 @@
/*
* Target-specific parts of semihosting/arm-compat-semi.c.
*
* Copyright (c) 2005, 2007 CodeSourcery.
* Copyright (c) 2019, 2022 Linaro
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H
#define TARGET_ARM_COMMON_SEMI_TARGET_H
#ifndef CONFIG_USER_ONLY
#include "hw/arm/boot.h"
#endif
static inline target_ulong common_semi_arg(CPUState *cs, int argno)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
if (is_a64(env)) {
return env->xregs[argno];
} else {
return env->regs[argno];
}
}
static inline void common_semi_set_ret(CPUState *cs, target_ulong ret)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
if (is_a64(env)) {
env->xregs[0] = ret;
} else {
env->regs[0] = ret;
}
}
static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr)
{
return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr));
}
static inline bool is_64bit_semihosting(CPUArchState *env)
{
return is_a64(env);
}
static inline target_ulong common_semi_stack_bottom(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
return is_a64(env) ? env->xregs[31] : env->regs[13];
}
static inline bool common_semi_has_synccache(CPUArchState *env)
{
/* Ok for A64, invalid for A32/T32 */
return is_a64(env);
}
#endif

50
target/riscv/common-semi-target.h Normal file
View File

@ -0,0 +1,50 @@
/*
* Target-specific parts of semihosting/arm-compat-semi.c.
*
* Copyright (c) 2005, 2007 CodeSourcery.
* Copyright (c) 2019, 2022 Linaro
* Copyright © 2020 by Keith Packard <keithp@keithp.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H
#define TARGET_RISCV_COMMON_SEMI_TARGET_H
static inline target_ulong common_semi_arg(CPUState *cs, int argno)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
return env->gpr[xA0 + argno];
}
static inline void common_semi_set_ret(CPUState *cs, target_ulong ret)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->gpr[xA0] = ret;
}
static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr)
{
return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8);
}
static inline bool is_64bit_semihosting(CPUArchState *env)
{
return riscv_cpu_mxl(env) != MXL_RV32;
}
static inline target_ulong common_semi_stack_bottom(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
return env->gpr[xSP];
}
static inline bool common_semi_has_synccache(CPUArchState *env)
{
return true;
}
#endif