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semihosting: Split out common_semi_has_synccache

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We already have some larger ifdef blocks for ARM and RISCV;
split out a boolean test for SYS_SYNCCACHE.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-29 14:16:01 -07:00
parent 3c820ddc1b
commit a1df4bab43
1 changed files with 13 additions and 7 deletions
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20
semihosting/arm-compat-semi.c
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@ -224,6 +224,12 @@ static inline target_ulong common_semi_stack_bottom(CPUState *cs)
CPUARMState *env = &cpu->env;
return is_a64(env) ? env->xregs[31] : env->regs[13];
}
static inline bool common_semi_has_synccache(CPUArchState *env)
{
/* Ok for A64, invalid for A32/T32. */
return is_a64(env);
}
#endif /* TARGET_ARM */
#ifdef TARGET_RISCV
@ -260,6 +266,11 @@ static inline target_ulong common_semi_stack_bottom(CPUState *cs)
CPURISCVState *env = &cpu->env;
return env->gpr[xSP];
}
static inline bool common_semi_has_synccache(CPUArchState *env)
{
return true;
}
#endif
/*
@ -1102,16 +1113,11 @@ void do_common_semihosting(CPUState *cs)
* virtual address range. This is a nop for us since we don't
* implement caches. This is only present on A64.
*/
#ifdef TARGET_ARM
if (is_a64(cs->env_ptr)) {
if (common_semi_has_synccache(env)) {
common_semi_set_ret(cs, 0);
break;
}
#endif
#ifdef TARGET_RISCV
common_semi_set_ret(cs, 0);
#endif
/* fall through -- invalid for A32/T32 */
/* fall through */
default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
cpu_dump_state(cs, stderr, 0);