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ppc/pnv: Implement Power9 CPU core thread state indirect register

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Power9 CPUs have a core thread state register accessible via SPRC/SPRD
indirect registers. This register includes a bit for big-core mode,
which skiboot requires.

Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-07-11 18:31:35 +10:00
parent 27f61d1b0b
commit 16ffcb3401
1 changed files with 17 additions and 0 deletions
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17
target/ppc/misc_helper.c
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@ -325,6 +325,23 @@ target_ulong helper_load_sprd(CPUPPCState *env)
case 0: /* SCRATCH0-3 */
case 1: /* SCRATCH4-7 */
return pc->scratch[(sprc >> 3) & 0x7];
case 0x1e0: /* core thread state */
if (env->excp_model == POWERPC_EXCP_POWER9) {
/*
* Only implement for POWER9 because skiboot uses it to check
* big-core mode. Other bits are unimplemented so we would
* prefer to get unimplemented message on POWER10 if it were
* used anywhere.
*/
if (pc->big_core) {
return PPC_BIT(63);
} else {
return 0;
}
}
/* fallthru */
default:
qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x"
TARGET_FMT_lx"\n", sprc);