From 16ffcb3401ddb991ec746de05595ba62eae45a1b Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Thu, 11 Jul 2024 18:31:35 +1000 Subject: [PATCH] ppc/pnv: Implement Power9 CPU core thread state indirect register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Power9 CPUs have a core thread state register accessible via SPRC/SPRD indirect registers. This register includes a bit for big-core mode, which skiboot requires. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- target/ppc/misc_helper.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 9789d69664..1b83971375 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -325,6 +325,23 @@ target_ulong helper_load_sprd(CPUPPCState *env) case 0: /* SCRATCH0-3 */ case 1: /* SCRATCH4-7 */ return pc->scratch[(sprc >> 3) & 0x7]; + + case 0x1e0: /* core thread state */ + if (env->excp_model == POWERPC_EXCP_POWER9) { + /* + * Only implement for POWER9 because skiboot uses it to check + * big-core mode. Other bits are unimplemented so we would + * prefer to get unimplemented message on POWER10 if it were + * used anywhere. + */ + if (pc->big_core) { + return PPC_BIT(63); + } else { + return 0; + } + } + /* fallthru */ + default: qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" TARGET_FMT_lx"\n", sprc);