mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ppc/ppc405: QOM'ify GPIO

Browse Source 
The GPIO controller is currently modeled as a simple SysBus device
with a unique memory region.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <e95d7849f3768e1f9a2846c4b282392750678b3e.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Cédric Le Goater 2022-08-17 17:08:23 +02:00 committed by Daniel Henrique Barboza
parent 2847eb4089
commit 125277c6a8
3 changed files with 45 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
hw/ppc/ppc405.h
View File

@ -63,6 +63,26 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
/* GPIO */
#define TYPE_PPC405_GPIO "ppc405-gpio"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
struct Ppc405GpioState {
SysBusDevice parent_obj;
MemoryRegion io;
uint32_t or;
uint32_t tcr;
uint32_t osrh;
uint32_t osrl;
uint32_t tsrh;
uint32_t tsrl;
uint32_t odr;
uint32_t ir;
uint32_t rr1;
uint32_t isr1h;
uint32_t isr1l;
};
/* On Chip Memory */
#define TYPE_PPC405_OCM "ppc405-ocm"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
@ -152,6 +172,7 @@ struct Ppc405SoCState {
Ppc405CpcState cpc;
Ppc405GptState gpt;
Ppc405OcmState ocm;
Ppc405GpioState gpio;
};
/* PowerPC 405 core */

50
hw/ppc/ppc405_uc.c
View File

@ -714,22 +714,6 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
/*****************************************************************************/
/* GPIO */
typedef struct ppc405_gpio_t ppc405_gpio_t;
struct ppc405_gpio_t {
MemoryRegion io;
uint32_t or;
uint32_t tcr;
uint32_t osrh;
uint32_t osrl;
uint32_t tsrh;
uint32_t tsrl;
uint32_t odr;
uint32_t ir;
uint32_t rr1;
uint32_t isr1h;
uint32_t isr1l;
};
static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
{
trace_ppc405_gpio_read(addr, size);
@ -748,20 +732,22 @@ static const MemoryRegionOps ppc405_gpio_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc405_gpio_reset (void *opaque)
static void ppc405_gpio_realize(DeviceState *dev, Error **errp)
{
Ppc405GpioState *s = PPC405_GPIO(dev);
memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio",
0x38);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io);
}
static void ppc405_gpio_init(hwaddr base)
static void ppc405_gpio_class_init(ObjectClass *oc, void *data)
{
ppc405_gpio_t *gpio;
DeviceClass *dc = DEVICE_CLASS(oc);
trace_ppc405_gpio_init(base);
gpio = g_new0(ppc405_gpio_t, 1);
memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
memory_region_add_subregion(get_system_memory(), base, &gpio->io);
qemu_register_reset(&ppc405_gpio_reset, gpio);
dc->realize = ppc405_gpio_realize;
/* Reason: only works as function of a ppc4xx SoC */
dc->user_creatable = false;
}
/*****************************************************************************/
@ -1414,6 +1400,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
}
static void ppc405_reset(void *opaque)
@ -1492,8 +1480,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
qdev_get_gpio_in(s->uic, 2));
/* GPIO */
ppc405_gpio_init(0xef600700);
sbd = SYS_BUS_DEVICE(&s->gpio);
if (!sysbus_realize(sbd, errp)) {
return;
}
sysbus_mmio_map(sbd, 0, 0xef600700);
/* Serial ports */
if (serial_hd(0) != NULL) {
@ -1555,6 +1548,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
.name = TYPE_PPC405_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405GpioState),
.class_init = ppc405_gpio_class_init,
}, {
.name = TYPE_PPC405_OCM,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405OcmState),

1
hw/ppc/trace-events
View File

@ -165,7 +165,6 @@ opba_init(uint64_t addr) "offet 0x%" PRIx64
ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
ppc405_gpio_init(uint64_t addr) "offet 0x%" PRIx64
ocm_update_mappings(uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl, uint32_t ocm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc, uint32_t ocm_dsacntl) "OCM update ISA 0x%08" PRIx32 " 0x%08" PRIx32 " (0x%08" PRIx32" 0x%08" PRIx32 ") DSA 0x%08" PRIx32 " 0x%08" PRIx32" (0x%08" PRIx32 " 0x%08" PRIx32 ")"
ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32