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ppc/ppc405: QOM'ify OCM

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The OCM controller is currently modeled as a simple DCR device with
a couple of memory regions.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <ecb93d2d5993bb7a970365744c7d342d4abcb017.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Cédric Le Goater 2022-08-17 17:08:22 +02:00 committed by Daniel Henrique Barboza
parent 269fbb5b8a
commit 2847eb4089
2 changed files with 55 additions and 38 deletions
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16
hw/ppc/ppc405.h
View File

@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
/* On Chip Memory */
#define TYPE_PPC405_OCM "ppc405-ocm"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
struct Ppc405OcmState {
Ppc4xxDcrDeviceState parent_obj;
MemoryRegion ram;
MemoryRegion isarc_ram;
MemoryRegion dsarc_ram;
uint32_t isarc;
uint32_t isacntl;
uint32_t dsarc;
uint32_t dsacntl;
};
/* General purpose timers */
#define TYPE_PPC405_GPT "ppc405-gpt"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
@ -136,6 +151,7 @@ struct Ppc405SoCState {
DeviceState *uic;
Ppc405CpcState cpc;
Ppc405GptState gpt;
Ppc405OcmState ocm;
};
/* PowerPC 405 core */

77
hw/ppc/ppc405_uc.c
View File

@ -773,20 +773,9 @@ enum {
OCM0_DSACNTL = 0x01B,
};
typedef struct ppc405_ocm_t ppc405_ocm_t;
struct ppc405_ocm_t {
MemoryRegion ram;
MemoryRegion isarc_ram;
MemoryRegion dsarc_ram;
uint32_t isarc;
uint32_t isacntl;
uint32_t dsarc;
uint32_t dsacntl;
};
static void ocm_update_mappings (ppc405_ocm_t *ocm,
uint32_t isarc, uint32_t isacntl,
uint32_t dsarc, uint32_t dsacntl)
static void ocm_update_mappings(Ppc405OcmState *ocm,
uint32_t isarc, uint32_t isacntl,
uint32_t dsarc, uint32_t dsacntl)
{
trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
ocm->isacntl, ocm->dsarc, ocm->dsacntl);
@ -828,12 +817,11 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
}
}
static uint32_t dcr_read_ocm (void *opaque, int dcrn)
static uint32_t dcr_read_ocm(void *opaque, int dcrn)
{
ppc405_ocm_t *ocm;
Ppc405OcmState *ocm = opaque;
uint32_t ret;
ocm = opaque;
switch (dcrn) {
case OCM0_ISARC:
ret = ocm->isarc;
@ -855,12 +843,11 @@ static uint32_t dcr_read_ocm (void *opaque, int dcrn)
return ret;
}
static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
static void dcr_write_ocm(void *opaque, int dcrn, uint32_t val)
{
ppc405_ocm_t *ocm;
Ppc405OcmState *ocm = opaque;
uint32_t isarc, dsarc, isacntl, dsacntl;
ocm = opaque;
isarc = ocm->isarc;
dsarc = ocm->dsarc;
isacntl = ocm->isacntl;
@ -886,12 +873,11 @@ static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
ocm->dsacntl = dsacntl;
}
static void ocm_reset (void *opaque)
static void ppc405_ocm_reset(DeviceState *dev)
{
ppc405_ocm_t *ocm;
Ppc405OcmState *ocm = PPC405_OCM(dev);
uint32_t isarc, dsarc, isacntl, dsacntl;
ocm = opaque;
isarc = 0x00000000;
isacntl = 0x00000000;
dsarc = 0x00000000;
@ -903,25 +889,31 @@ static void ocm_reset (void *opaque)
ocm->dsacntl = dsacntl;
}
static void ppc405_ocm_init(CPUPPCState *env)
static void ppc405_ocm_realize(DeviceState *dev, Error **errp)
{
ppc405_ocm_t *ocm;
Ppc405OcmState *ocm = PPC405_OCM(dev);
Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
ocm = g_new0(ppc405_ocm_t, 1);
/* XXX: Size is 4096 or 0x04000000 */
memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB,
memory_region_init_ram(&ocm->isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 * KiB,
&error_fatal);
memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc",
memory_region_init_alias(&ocm->dsarc_ram, OBJECT(ocm), "ppc405.dsarc",
&ocm->isarc_ram, 0, 4 * KiB);
qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_ISACNTL,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_DSARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_DSACNTL,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc4xx_dcr_register(dcr, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc4xx_dcr_register(dcr, OCM0_ISACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc4xx_dcr_register(dcr, OCM0_DSARC, ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc4xx_dcr_register(dcr, OCM0_DSACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm);
}
static void ppc405_ocm_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = ppc405_ocm_realize;
dc->reset = ppc405_ocm_reset;
/* Reason: only works as function of a ppc4xx SoC */
dc->user_creatable = false;
}
/*****************************************************************************/
@ -1420,6 +1412,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
}
static void ppc405_reset(void *opaque)
@ -1516,7 +1510,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* OCM */
ppc405_ocm_init(env);
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ocm), &s->cpu, errp)) {
return;
}
/* GPT */
sbd = SYS_BUS_DEVICE(&s->gpt);
@ -1559,6 +1555,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
.name = TYPE_PPC405_OCM,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405OcmState),
.class_init = ppc405_ocm_class_init,
}, {
.name = TYPE_PPC405_GPT,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405GptState),