target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
875ce3929a
commit
09b157e628
@ -498,6 +498,12 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
|
|||||||
FONEd 10 ..... 110110 00000 0 0111 1110 00000 rd=%dfp_rd
|
FONEd 10 ..... 110110 00000 0 0111 1110 00000 rd=%dfp_rd
|
||||||
FONEs 10 rd:5 110110 00000 0 0111 1111 00000
|
FONEs 10 rd:5 110110 00000 0 0111 1111 00000
|
||||||
|
|
||||||
|
MOVsTOuw 10 ..... 110110 00000 1 0001 0001 ..... @r_r2
|
||||||
|
MOVsTOsw 10 ..... 110110 00000 1 0001 0011 ..... @r_r2
|
||||||
|
MOVwTOs 10 ..... 110110 00000 1 0001 1001 ..... @r_r2
|
||||||
|
MOVdTOx 10 ..... 110110 00000 1 0001 0000 ..... @r_d2
|
||||||
|
MOVxTOd 10 ..... 110110 00000 1 0001 1000 ..... @d_r2
|
||||||
|
|
||||||
FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5
|
FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5
|
||||||
FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \
|
FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \
|
||||||
rs1=%dfp_rs1 rs2=%dfp_rs2
|
rs1=%dfp_rs1 rs2=%dfp_rs2
|
||||||
|
@ -5401,6 +5401,42 @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
|
|||||||
return advance_pc(dc);
|
return advance_pc(dc);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static bool do_movf2r(DisasContext *dc, arg_r_r *a,
|
||||||
|
int (*offset)(unsigned int),
|
||||||
|
void (*load)(TCGv, TCGv_ptr, tcg_target_long))
|
||||||
|
{
|
||||||
|
TCGv dst;
|
||||||
|
|
||||||
|
if (gen_trap_ifnofpu(dc)) {
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
dst = gen_dest_gpr(dc, a->rd);
|
||||||
|
load(dst, tcg_env, offset(a->rs));
|
||||||
|
gen_store_gpr(dc, a->rd, dst);
|
||||||
|
return advance_pc(dc);
|
||||||
|
}
|
||||||
|
|
||||||
|
TRANS(MOVsTOsw, VIS3B, do_movf2r, a, gen_offset_fpr_F, tcg_gen_ld32s_tl)
|
||||||
|
TRANS(MOVsTOuw, VIS3B, do_movf2r, a, gen_offset_fpr_F, tcg_gen_ld32u_tl)
|
||||||
|
TRANS(MOVdTOx, VIS3B, do_movf2r, a, gen_offset_fpr_D, tcg_gen_ld_tl)
|
||||||
|
|
||||||
|
static bool do_movr2f(DisasContext *dc, arg_r_r *a,
|
||||||
|
int (*offset)(unsigned int),
|
||||||
|
void (*store)(TCGv, TCGv_ptr, tcg_target_long))
|
||||||
|
{
|
||||||
|
TCGv src;
|
||||||
|
|
||||||
|
if (gen_trap_ifnofpu(dc)) {
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
src = gen_load_gpr(dc, a->rs);
|
||||||
|
store(src, tcg_env, offset(a->rd));
|
||||||
|
return advance_pc(dc);
|
||||||
|
}
|
||||||
|
|
||||||
|
TRANS(MOVwTOs, VIS3B, do_movr2f, a, gen_offset_fpr_F, tcg_gen_st32_tl)
|
||||||
|
TRANS(MOVxTOd, VIS3B, do_movr2f, a, gen_offset_fpr_D, tcg_gen_st_tl)
|
||||||
|
|
||||||
static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
|
static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
|
||||||
{
|
{
|
||||||
DisasContext *dc = container_of(dcbase, DisasContext, base);
|
DisasContext *dc = container_of(dcbase, DisasContext, base);
|
||||||
|
Loading…
x
Reference in New Issue
Block a user