mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/sparc: Implement LZCNT

Browse Source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-04 17:48:25 -07:00
parent 298c52f784
commit 875ce3929a
2 changed files with 19 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/sparc/insns.decode
View File

@ -389,6 +389,7 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
ADDXC 10 ..... 110110 ..... 0 0001 0001 ..... @r_r_r
ADDXCcc 10 ..... 110110 ..... 0 0001 0011 ..... @r_r_r
LZCNT 10 ..... 110110 00000 0 0001 0111 ..... @r_r2
ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r
ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r

18
target/sparc/translate.c
View File

@ -658,6 +658,11 @@ static void gen_op_popc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_ctpop_tl(dst, src2);
}
static void gen_op_lzcnt(TCGv dst, TCGv src)
{
tcg_gen_clzi_tl(dst, src, TARGET_LONG_BITS);
}
#ifndef TARGET_SPARC64
static void gen_helper_array8(TCGv dst, TCGv src1, TCGv src2)
{
@ -3873,6 +3878,19 @@ TRANS(EDGE16LN, VIS2, gen_edge, a, 16, 0, 1)
TRANS(EDGE32N, VIS2, gen_edge, a, 32, 0, 0)
TRANS(EDGE32LN, VIS2, gen_edge, a, 32, 0, 1)
static bool do_rr(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv, TCGv))
{
TCGv dst = gen_dest_gpr(dc, a->rd);
TCGv src = gen_load_gpr(dc, a->rs);
func(dst, src);
gen_store_gpr(dc, a->rd, dst);
return advance_pc(dc);
}
TRANS(LZCNT, VIS3, do_rr, a, gen_op_lzcnt)
static bool do_rrr(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv, TCGv, TCGv))
{