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riscv: sifive_e: Manually define the machine

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Alistair Francis 2020-05-13 10:37:08 -07:00
parent f33559a427
commit 0869490b1c
2 changed files with 34 additions and 11 deletions
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41
hw/riscv/sifive_e.c
View File

@ -79,7 +79,7 @@ static void riscv_sifive_e_init(MachineState *machine)
{ {
const struct MemmapEntry *memmap = sifive_e_memmap; const struct MemmapEntry *memmap = sifive_e_memmap;
SiFiveEState *s = g_new0(SiFiveEState, 1); SiFiveEState *s = RISCV_E_MACHINE(machine);
MemoryRegion *sys_mem = get_system_memory(); MemoryRegion *sys_mem = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1); MemoryRegion *main_mem = g_new(MemoryRegion, 1);
int i; int i;
@ -115,6 +115,35 @@ static void riscv_sifive_e_init(MachineState *machine)
} }
} }
static void sifive_e_machine_instance_init(Object *obj)
{
}
static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Board compatible with SiFive E SDK";
mc->init = riscv_sifive_e_init;
mc->max_cpus = 1;
mc->default_cpu_type = SIFIVE_E_CPU;
}
static const TypeInfo sifive_e_machine_typeinfo = {
.name = MACHINE_TYPE_NAME("sifive_e"),
.parent = TYPE_MACHINE,
.class_init = sifive_e_machine_class_init,
.instance_init = sifive_e_machine_instance_init,
.instance_size = sizeof(SiFiveEState),
};
static void sifive_e_machine_init_register_types(void)
{
type_register_static(&sifive_e_machine_typeinfo);
}
type_init(sifive_e_machine_init_register_types)
static void riscv_sifive_e_soc_init(Object *obj) static void riscv_sifive_e_soc_init(Object *obj)
{ {
MachineState *ms = MACHINE(qdev_get_machine()); MachineState *ms = MACHINE(qdev_get_machine());
@ -214,16 +243,6 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
&s->xip_mem); &s->xip_mem);
} }
static void riscv_sifive_e_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with SiFive E SDK";
mc->init = riscv_sifive_e_init;
mc->max_cpus = 1;
mc->default_cpu_type = SIFIVE_E_CPU;
}
DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data) static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);

4
include/hw/riscv/sifive_e.h
View File

@ -47,6 +47,10 @@ typedef struct SiFiveEState {
SiFiveESoCState soc; SiFiveESoCState soc;
} SiFiveEState; } SiFiveEState;
#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
#define RISCV_E_MACHINE(obj) \
OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
enum { enum {
SIFIVE_E_DEBUG, SIFIVE_E_DEBUG,
SIFIVE_E_MROM, SIFIVE_E_MROM,