0869490b1c
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
269 lines
9.7 KiB
C
269 lines
9.7 KiB
C
/*
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* QEMU RISC-V Board Compatible with SiFive Freedom E SDK
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* Provides a board compatible with the SiFive Freedom E SDK:
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*
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* 0) UART
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* 1) CLINT (Core Level Interruptor)
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* 2) PLIC (Platform Level Interrupt Controller)
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* 3) PRCI (Power, Reset, Clock, Interrupt)
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* 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
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* 5) Flash memory emulated as RAM
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*
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* The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
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* The OTP ROM and Flash boot code will be emulated in a future version.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/misc/unimp.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/sifive_uart.h"
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#include "hw/riscv/sifive_e.h"
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#include "hw/riscv/sifive_e_prci.h"
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#include "hw/riscv/boot.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} sifive_e_memmap[] = {
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[SIFIVE_E_DEBUG] = { 0x0, 0x100 },
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[SIFIVE_E_MROM] = { 0x1000, 0x2000 },
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[SIFIVE_E_OTP] = { 0x20000, 0x2000 },
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[SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
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[SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
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[SIFIVE_E_AON] = { 0x10000000, 0x8000 },
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[SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
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[SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
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[SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
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[SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
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[SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 },
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[SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
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[SIFIVE_E_UART1] = { 0x10023000, 0x1000 },
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[SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 },
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[SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
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[SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 },
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[SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
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[SIFIVE_E_XIP] = { 0x20000000, 0x20000000 },
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[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
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};
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static void riscv_sifive_e_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = sifive_e_memmap;
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SiFiveEState *s = RISCV_E_MACHINE(machine);
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MemoryRegion *sys_mem = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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int i;
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/* Initialize SoC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc,
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sizeof(s->soc), TYPE_RISCV_E_SOC,
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&error_abort, NULL);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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/* Data Tightly Integrated Memory */
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memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
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memmap[SIFIVE_E_DTIM].size, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[SIFIVE_E_DTIM].base, main_mem);
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/* Mask ROM reset vector */
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uint32_t reset_vec[2] = {
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0x204002b7, /* 0x1000: lui t0,0x20400 */
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0x00028067, /* 0x1004: jr t0 */
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};
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/* copy in the reset vector in little_endian byte order */
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for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[SIFIVE_E_MROM].base, &address_space_memory);
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if (machine->kernel_filename) {
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riscv_load_kernel(machine->kernel_filename, NULL);
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}
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}
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static void sifive_e_machine_instance_init(Object *obj)
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{
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}
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static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "RISC-V Board compatible with SiFive E SDK";
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mc->init = riscv_sifive_e_init;
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mc->max_cpus = 1;
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mc->default_cpu_type = SIFIVE_E_CPU;
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}
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static const TypeInfo sifive_e_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("sifive_e"),
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.parent = TYPE_MACHINE,
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.class_init = sifive_e_machine_class_init,
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.instance_init = sifive_e_machine_instance_init,
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.instance_size = sizeof(SiFiveEState),
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};
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static void sifive_e_machine_init_register_types(void)
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{
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type_register_static(&sifive_e_machine_typeinfo);
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}
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type_init(sifive_e_machine_init_register_types)
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static void riscv_sifive_e_soc_init(Object *obj)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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SiFiveESoCState *s = RISCV_E_SOC(obj);
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object_initialize_child(obj, "cpus", &s->cpus,
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sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
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&error_abort, NULL);
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object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
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&error_abort);
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sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0",
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&s->gpio, sizeof(s->gpio),
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TYPE_SIFIVE_GPIO);
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}
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static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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const struct MemmapEntry *memmap = sifive_e_memmap;
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Error *err = NULL;
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SiFiveESoCState *s = RISCV_E_SOC(dev);
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MemoryRegion *sys_mem = get_system_memory();
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object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
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&error_abort);
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object_property_set_bool(OBJECT(&s->cpus), true, "realized",
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&error_abort);
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/* Mask ROM */
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memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
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memmap[SIFIVE_E_MROM].size, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[SIFIVE_E_MROM].base, &s->mask_rom);
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/* MMIO */
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s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
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(char *)SIFIVE_E_PLIC_HART_CONFIG,
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SIFIVE_E_PLIC_NUM_SOURCES,
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SIFIVE_E_PLIC_NUM_PRIORITIES,
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SIFIVE_E_PLIC_PRIORITY_BASE,
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SIFIVE_E_PLIC_PENDING_BASE,
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SIFIVE_E_PLIC_ENABLE_BASE,
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SIFIVE_E_PLIC_ENABLE_STRIDE,
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SIFIVE_E_PLIC_CONTEXT_BASE,
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SIFIVE_E_PLIC_CONTEXT_STRIDE,
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memmap[SIFIVE_E_PLIC].size);
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sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
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memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
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SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
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create_unimplemented_device("riscv.sifive.e.aon",
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memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
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sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
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/* GPIO */
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object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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/* Map GPIO registers */
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
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/* Pass all GPIOs to the SOC layer so they are available to the board */
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qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
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/* Connect GPIO interrupts to the PLIC */
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for (int i = 0; i < 32; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
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qdev_get_gpio_in(DEVICE(s->plic),
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SIFIVE_E_GPIO0_IRQ0 + i));
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}
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sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
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serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
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create_unimplemented_device("riscv.sifive.e.qspi0",
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memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
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create_unimplemented_device("riscv.sifive.e.pwm0",
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memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
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sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
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serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
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create_unimplemented_device("riscv.sifive.e.qspi1",
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memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
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create_unimplemented_device("riscv.sifive.e.pwm1",
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memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
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create_unimplemented_device("riscv.sifive.e.qspi2",
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memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
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create_unimplemented_device("riscv.sifive.e.pwm2",
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memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
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/* Flash memory */
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memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
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memmap[SIFIVE_E_XIP].size, &error_fatal);
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memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
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&s->xip_mem);
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}
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static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = riscv_sifive_e_soc_realize;
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/* Reason: Uses serial_hds in realize function, thus can't be used twice */
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dc->user_creatable = false;
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}
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static const TypeInfo riscv_sifive_e_soc_type_info = {
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.name = TYPE_RISCV_E_SOC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(SiFiveESoCState),
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.instance_init = riscv_sifive_e_soc_init,
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.class_init = riscv_sifive_e_soc_class_init,
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};
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static void riscv_sifive_e_soc_register_types(void)
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{
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type_register_static(&riscv_sifive_e_soc_type_info);
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}
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type_init(riscv_sifive_e_soc_register_types)
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