2006-05-13 20:11:23 +04:00
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/*
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2019-12-09 12:49:57 +03:00
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* QEMU i440FX PCI Bridge Emulation
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2006-05-13 20:11:23 +04:00
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*
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* Copyright (c) 2006 Fabrice Bellard
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2007-09-17 01:08:06 +04:00
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*
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2006-05-13 20:11:23 +04:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-01-26 21:17:03 +03:00
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#include "qemu/osdep.h"
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2020-06-01 17:29:27 +03:00
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#include "qemu/units.h"
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hw/pci-host/piix: Include "qemu/range.h"
hw/pci-host/piix.c calls various functions from the Range API.
Include "qemu/range.h" which declares them.
This fixes (when modifying unrelated headers):
hw/pci-host/i440fx.c:54:11: error: field has incomplete type 'Range' (aka 'struct Range')
Range pci_hole;
^
include/qemu/typedefs.h:116:16: note: forward declaration of 'struct Range'
typedef struct Range Range;
^
hw/pci-host/i440fx.c:126:9: error: implicit declaration of function 'ranges_overlap' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
^
hw/pci-host/i440fx.c:126:9: error: this function declaration is not a prototype [-Werror,-Wstrict-prototypes]
hw/pci-host/i440fx.c:127:9: error: implicit declaration of function 'range_covers_byte' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
range_covers_byte(address, len, I440FX_SMRAM)) {
^
hw/pci-host/i440fx.c:127:9: error: this function declaration is not a prototype [-Werror,-Wstrict-prototypes]
hw/pci-host/i440fx.c:189:13: error: implicit declaration of function 'range_is_empty' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
^
Acked-by: John Snow <jsnow@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200228114649.12818-15-philmd@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-02-28 14:46:45 +03:00
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#include "qemu/range.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/i386/pc.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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2019-02-02 22:57:47 +03:00
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#include "hw/pci-host/i440fx.h"
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2019-08-12 08:23:51 +03:00
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#include "hw/qdev-properties.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/sysbus.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
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#include "qapi/error.h"
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2019-08-12 08:23:45 +03:00
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#include "migration/vmstate.h"
|
2013-07-29 18:47:57 +04:00
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#include "qapi/visitor.h"
|
2015-11-13 09:55:48 +03:00
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#include "qemu/error-report.h"
|
2020-09-03 23:43:22 +03:00
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#include "qom/object.h"
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2007-11-17 20:14:51 +03:00
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2009-12-15 14:26:07 +03:00
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/*
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* I440FX chipset data sheet.
|
2018-10-24 01:44:25 +03:00
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* https://wiki.qemu.org/File:29054901.pdf
|
2009-12-15 14:26:07 +03:00
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*/
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2020-09-16 21:25:19 +03:00
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OBJECT_DECLARE_SIMPLE_TYPE(I440FXState, I440FX_PCI_HOST_BRIDGE)
|
2013-07-29 18:47:52 +04:00
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2020-09-03 23:43:22 +03:00
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struct I440FXState {
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2012-08-20 21:08:09 +04:00
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PCIHostState parent_obj;
|
2016-06-15 20:56:31 +03:00
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Range pci_hole;
|
2013-07-29 18:47:57 +04:00
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uint64_t pci_hole64_size;
|
2017-11-11 18:25:00 +03:00
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bool pci_hole64_fix;
|
2013-11-06 03:46:27 +04:00
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uint32_t short_root_bus;
|
2020-09-03 23:43:22 +03:00
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};
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2006-05-13 20:11:23 +04:00
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2009-12-15 14:26:05 +03:00
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#define I440FX_PAM 0x59
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#define I440FX_PAM_SIZE 7
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#define I440FX_SMRAM 0x72
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2017-11-11 18:25:00 +03:00
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/* Keep it 2G to comply with older win32 guests */
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#define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
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|
2015-08-07 22:15:31 +03:00
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/* Older coreboot versions (4.0 and older) read a config register that doesn't
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* exist in real hardware, to get the RAM size from QEMU.
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*/
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#define I440FX_COREBOOT_RAM_SIZE 0x57
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2009-08-28 17:28:15 +04:00
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static void i440fx_update_memory_mappings(PCII440FXState *d)
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2006-09-24 22:49:13 +04:00
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{
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2012-11-15 00:54:02 +04:00
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int i;
|
2013-07-01 14:18:21 +04:00
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PCIDevice *pd = PCI_DEVICE(d);
|
2006-09-24 23:31:43 +04:00
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2011-08-01 12:04:39 +04:00
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memory_region_transaction_begin();
|
2018-10-11 15:14:03 +03:00
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for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
|
2012-11-15 00:54:02 +04:00
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pam_update(&d->pam_regions[i], i,
|
2018-07-05 18:58:10 +03:00
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pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
|
2006-09-24 22:49:13 +04:00
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}
|
2015-03-31 15:14:28 +03:00
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memory_region_set_enabled(&d->smram_region,
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!(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
|
2015-03-31 15:10:22 +03:00
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memory_region_set_enabled(&d->smram,
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pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
|
2011-08-01 12:04:39 +04:00
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memory_region_transaction_commit();
|
2006-09-24 22:49:13 +04:00
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}
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2009-08-28 17:28:15 +04:00
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static void i440fx_write_config(PCIDevice *dev,
|
2006-09-24 22:49:13 +04:00
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uint32_t address, uint32_t val, int len)
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{
|
2013-02-23 04:40:37 +04:00
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PCII440FXState *d = I440FX_PCI_DEVICE(dev);
|
2009-08-28 17:28:15 +04:00
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2006-09-24 22:49:13 +04:00
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/* XXX: implement SMRAM.D_LOCK */
|
2009-08-28 17:28:15 +04:00
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pci_default_write_config(dev, address, val, len);
|
2009-12-15 14:26:06 +03:00
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if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
|
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range_covers_byte(address, len, I440FX_SMRAM)) {
|
2006-09-24 22:49:13 +04:00
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i440fx_update_memory_mappings(d);
|
2009-12-15 14:26:06 +03:00
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}
|
2006-09-24 22:49:13 +04:00
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}
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2009-09-30 00:48:21 +04:00
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static int i440fx_post_load(void *opaque, int version_id)
|
2009-08-28 17:28:26 +04:00
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{
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PCII440FXState *d = opaque;
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i440fx_update_memory_mappings(d);
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return 0;
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}
|
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|
static const VMStateDescription vmstate_i440fx = {
|
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.name = "I440FX",
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.version_id = 3,
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|
.minimum_version_id = 3,
|
2009-09-10 05:04:30 +04:00
|
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|
.post_load = i440fx_post_load,
|
2014-04-16 17:32:32 +04:00
|
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|
.fields = (VMStateField[]) {
|
2013-07-01 14:18:21 +04:00
|
|
|
VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
|
2015-03-31 15:12:25 +03:00
|
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|
/* Used to be smm_enabled, which was basically always zero because
|
|
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|
* SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
|
|
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|
*/
|
|
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|
VMSTATE_UNUSED(1),
|
2009-08-28 17:28:26 +04:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2013-07-29 18:47:57 +04:00
|
|
|
static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 16:48:55 +03:00
|
|
|
const char *name, void *opaque,
|
2013-07-29 18:47:57 +04:00
|
|
|
Error **errp)
|
|
|
|
{
|
|
|
|
I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
|
2016-07-01 14:47:47 +03:00
|
|
|
uint64_t val64;
|
|
|
|
uint32_t value;
|
2013-07-29 18:47:57 +04:00
|
|
|
|
2016-07-01 14:47:47 +03:00
|
|
|
val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
|
|
|
|
value = val64;
|
|
|
|
assert(value == val64);
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 16:48:54 +03:00
|
|
|
visit_type_uint32(v, name, &value, errp);
|
2013-07-29 18:47:57 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 16:48:55 +03:00
|
|
|
const char *name, void *opaque,
|
2013-07-29 18:47:57 +04:00
|
|
|
Error **errp)
|
|
|
|
{
|
|
|
|
I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
|
2016-07-01 14:47:47 +03:00
|
|
|
uint64_t val64;
|
|
|
|
uint32_t value;
|
2013-07-29 18:47:57 +04:00
|
|
|
|
2016-07-01 14:47:47 +03:00
|
|
|
val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
|
|
|
|
value = val64;
|
|
|
|
assert(value == val64);
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 16:48:54 +03:00
|
|
|
visit_type_uint32(v, name, &value, errp);
|
2013-07-29 18:47:57 +04:00
|
|
|
}
|
|
|
|
|
2017-11-11 18:25:00 +03:00
|
|
|
/*
|
|
|
|
* The 64bit PCI hole start is set by the Guest firmware
|
|
|
|
* as the address of the first 64bit PCI MEM resource.
|
|
|
|
* If no PCI device has resources on the 64bit area,
|
|
|
|
* the 64bit PCI hole will start after "over 4G RAM" and the
|
|
|
|
* reserved space for memory hotplug if any.
|
|
|
|
*/
|
2018-09-28 00:24:37 +03:00
|
|
|
static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
|
2013-07-29 18:47:57 +04:00
|
|
|
{
|
2013-09-02 13:58:57 +04:00
|
|
|
PCIHostState *h = PCI_HOST_BRIDGE(obj);
|
2017-11-11 18:25:00 +03:00
|
|
|
I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
|
2013-09-02 13:58:57 +04:00
|
|
|
Range w64;
|
2016-07-01 14:47:47 +03:00
|
|
|
uint64_t value;
|
2013-09-02 13:58:57 +04:00
|
|
|
|
|
|
|
pci_bus_get_w64_range(h->bus, &w64);
|
2016-07-01 14:47:47 +03:00
|
|
|
value = range_is_empty(&w64) ? 0 : range_lob(&w64);
|
2017-11-11 18:25:00 +03:00
|
|
|
if (!value && s->pci_hole64_fix) {
|
|
|
|
value = pc_pci_hole64_start();
|
|
|
|
}
|
2018-09-28 00:24:37 +03:00
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
|
|
|
|
const char *name,
|
|
|
|
void *opaque, Error **errp)
|
|
|
|
{
|
|
|
|
uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
|
|
|
|
|
|
|
|
visit_type_uint64(v, name, &hole64_start, errp);
|
2013-07-29 18:47:57 +04:00
|
|
|
}
|
|
|
|
|
2017-11-11 18:25:00 +03:00
|
|
|
/*
|
|
|
|
* The 64bit PCI hole end is set by the Guest firmware
|
|
|
|
* as the address of the last 64bit PCI MEM resource.
|
|
|
|
* Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
|
|
|
|
* that can be configured by the user.
|
|
|
|
*/
|
2013-07-29 18:47:57 +04:00
|
|
|
static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 16:48:55 +03:00
|
|
|
const char *name, void *opaque,
|
2013-07-29 18:47:57 +04:00
|
|
|
Error **errp)
|
|
|
|
{
|
2013-09-02 13:58:57 +04:00
|
|
|
PCIHostState *h = PCI_HOST_BRIDGE(obj);
|
2017-11-11 18:25:00 +03:00
|
|
|
I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
|
hw/pci-host/x86: extend the 64-bit PCI hole relative to the fw-assigned base
In commit 9fa99d2519cb ("hw/pci-host: Fix x86 Host Bridges 64bit PCI
hole", 2017-11-16), we meant to expose such a 64-bit PCI MMIO aperture in
the ACPI DSDT that would be at least as large as the new "pci-hole64-size"
property (2GB on i440fx, 32GB on q35). The goal was to offer "enough"
64-bit MMIO aperture to the guest OS for hotplug purposes.
In that commit, we added or modified five functions:
- pc_pci_hole64_start(): shared between i440fx and q35. Provides a default
64-bit base, which starts beyond the cold-plugged 64-bit RAM, and skips
the DIMM hotplug area too (if any).
- i440fx_pcihost_get_pci_hole64_start(), q35_host_get_pci_hole64_start():
board-specific 64-bit base property getters called abstractly by the
ACPI generator. Both of these fall back to pc_pci_hole64_start() if the
firmware didn't program any 64-bit hole (i.e. if the firmware didn't
assign a 64-bit GPA to any MMIO BAR on any device). Otherwise, they
honor the firmware's BAR assignments (i.e., they treat the lowest 64-bit
GPA programmed by the firmware as the base address for the aperture).
- i440fx_pcihost_get_pci_hole64_end(), q35_host_get_pci_hole64_end():
these intended to extend the aperture to our size recommendation,
calculated relative to the base of the aperture.
Despite the original intent, i440fx_pcihost_get_pci_hole64_end() and
q35_host_get_pci_hole64_end() currently only extend the aperture relative
to the default base (pc_pci_hole64_start()), ignoring any programming done
by the firmware. This means that our size recommendation may not be met.
Fix it by honoring the firmware's address assignments.
The strange extension sizes were spotted by Alex, in the log of a guest
kernel running on top of OVMF (which prefers to assign 64-bit GPAs to
64-bit BARs).
This change only affects DSDT generation, therefore no new compat property
is being introduced.
Using an i440fx OVMF guest with 5GB RAM, an example _CRS change is:
> @@ -881,9 +881,9 @@
> QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> 0x0000000000000000, // Granularity
> 0x0000000800000000, // Range Minimum
> - 0x000000080001C0FF, // Range Maximum
> + 0x000000087FFFFFFF, // Range Maximum
> 0x0000000000000000, // Translation Offset
> - 0x000000000001C100, // Length
> + 0x0000000080000000, // Length
> ,, , AddressRangeMemory, TypeStatic)
> })
> Device (GPE0)
(On i440fx, the low RAM split is at 3GB, in this case. Therefore, with 5GB
guest RAM and no DIMM hotplug range, pc_pci_hole64_start() returns 4 +
(5-3) = 6 GB. Adding the 2GB extension to that yields 8GB, which is below
the firmware-programmed base of 32GB, before the patch. Therefore, before
the patch, the extension is ineffective. After the patch, we add the 2GB
extension to the firmware-programmed base, namely 32GB.)
Using a q35 OVMF guest with 5GB RAM, an example _CRS change is:
> @@ -3162,9 +3162,9 @@
> QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> 0x0000000000000000, // Granularity
> 0x0000000800000000, // Range Minimum
> - 0x00000009BFFFFFFF, // Range Maximum
> + 0x0000000FFFFFFFFF, // Range Maximum
> 0x0000000000000000, // Translation Offset
> - 0x00000001C0000000, // Length
> + 0x0000000800000000, // Length
> ,, , AddressRangeMemory, TypeStatic)
> })
> Device (GPE0)
(On Q35, the low RAM split is at 2GB. Therefore, with 5GB guest RAM and no
DIMM hotplug range, pc_pci_hole64_start() returns 4 + (5-2) = 7 GB. Adding
the 32GB extension to that yields 39GB (0x0000_0009_BFFF_FFFF + 1), before
the patch. After the patch, we add the 32GB extension to the
firmware-programmed base, namely 32GB.)
The ACPI test data for the bios-tables-test case that we added earlier in
this series are corrected too, as follows:
> @@ -3339,9 +3339,9 @@
> QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> 0x0000000000000000, // Granularity
> 0x0000000200000000, // Range Minimum
> - 0x00000009BFFFFFFF, // Range Maximum
> + 0x00000009FFFFFFFF, // Range Maximum
> 0x0000000000000000, // Translation Offset
> - 0x00000007C0000000, // Length
> + 0x0000000800000000, // Length
> ,, , AddressRangeMemory, TypeStatic)
> })
> Device (GPE0)
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Fixes: 9fa99d2519cbf71f871e46871df12cb446dc1c3e
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-09-28 00:24:38 +03:00
|
|
|
uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
|
2013-09-02 13:58:57 +04:00
|
|
|
Range w64;
|
2017-11-11 18:25:00 +03:00
|
|
|
uint64_t value, hole64_end;
|
2013-09-02 13:58:57 +04:00
|
|
|
|
|
|
|
pci_bus_get_w64_range(h->bus, &w64);
|
2016-07-01 14:47:47 +03:00
|
|
|
value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
|
2017-11-11 18:25:00 +03:00
|
|
|
hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
|
|
|
|
if (s->pci_hole64_fix && value < hole64_end) {
|
|
|
|
value = hole64_end;
|
|
|
|
}
|
2016-07-01 14:47:47 +03:00
|
|
|
visit_type_uint64(v, name, &value, errp);
|
2013-07-29 18:47:57 +04:00
|
|
|
}
|
|
|
|
|
2013-07-01 14:18:20 +04:00
|
|
|
static void i440fx_pcihost_initfn(Object *obj)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
2013-07-01 14:18:20 +04:00
|
|
|
PCIHostState *s = PCI_HOST_BRIDGE(obj);
|
2006-05-13 20:11:23 +04:00
|
|
|
|
2013-07-01 14:18:20 +04:00
|
|
|
memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
|
2011-07-24 18:47:18 +04:00
|
|
|
"pci-conf-idx", 4);
|
2013-07-01 14:18:20 +04:00
|
|
|
memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
|
2011-07-24 18:47:18 +04:00
|
|
|
"pci-conf-data", 4);
|
2013-07-01 14:18:20 +04:00
|
|
|
}
|
2006-05-13 20:11:23 +04:00
|
|
|
|
2013-07-01 14:18:20 +04:00
|
|
|
static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
PCIHostState *s = PCI_HOST_BRIDGE(dev);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
|
|
|
|
sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
|
|
|
|
sysbus_init_ioports(sbd, 0xcf8, 4);
|
|
|
|
|
|
|
|
sysbus_add_io(sbd, 0xcfc, &s->data_mem);
|
|
|
|
sysbus_init_ioports(sbd, 0xcfc, 4);
|
2018-10-17 19:52:56 +03:00
|
|
|
|
|
|
|
/* register i440fx 0xcf8 port as coalesced pio */
|
|
|
|
memory_region_set_flush_coalesced(&s->data_mem);
|
|
|
|
memory_region_add_coalescing(&s->conf_mem, 0, 4);
|
2009-07-22 17:17:01 +04:00
|
|
|
}
|
2006-05-13 20:11:23 +04:00
|
|
|
|
2015-01-19 17:52:30 +03:00
|
|
|
static void i440fx_realize(PCIDevice *dev, Error **errp)
|
2009-07-22 17:17:01 +04:00
|
|
|
{
|
2013-07-01 14:18:21 +04:00
|
|
|
dev->config[I440FX_SMRAM] = 0x02;
|
2015-11-13 09:55:48 +03:00
|
|
|
|
|
|
|
if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
|
2017-07-12 16:57:41 +03:00
|
|
|
warn_report("i440fx doesn't support emulated iommu");
|
2015-11-13 09:55:48 +03:00
|
|
|
}
|
2009-07-22 17:17:01 +04:00
|
|
|
}
|
|
|
|
|
2022-07-19 20:00:05 +03:00
|
|
|
PCIBus *i440fx_init(const char *pci_type,
|
|
|
|
DeviceState *dev,
|
2013-07-29 18:47:53 +04:00
|
|
|
MemoryRegion *address_space_mem,
|
|
|
|
MemoryRegion *address_space_io,
|
|
|
|
ram_addr_t ram_size,
|
2013-12-21 06:02:50 +04:00
|
|
|
ram_addr_t below_4g_mem_size,
|
2013-07-29 18:47:57 +04:00
|
|
|
ram_addr_t above_4g_mem_size,
|
2013-07-29 18:47:53 +04:00
|
|
|
MemoryRegion *pci_address_space,
|
|
|
|
MemoryRegion *ram_memory)
|
2009-07-22 17:17:01 +04:00
|
|
|
{
|
|
|
|
PCIBus *b;
|
|
|
|
PCIDevice *d;
|
2012-08-20 21:08:08 +04:00
|
|
|
PCIHostState *s;
|
2011-08-15 18:17:38 +04:00
|
|
|
PCII440FXState *f;
|
2012-10-17 19:10:04 +04:00
|
|
|
unsigned i;
|
2013-07-29 18:47:57 +04:00
|
|
|
I440FXState *i440fx;
|
2009-07-22 17:17:01 +04:00
|
|
|
|
2012-08-20 21:08:08 +04:00
|
|
|
s = PCI_HOST_BRIDGE(dev);
|
2017-11-29 11:46:22 +03:00
|
|
|
b = pci_root_bus_new(dev, NULL, pci_address_space,
|
|
|
|
address_space_io, 0, TYPE_PCI_BUS);
|
2009-07-22 17:17:01 +04:00
|
|
|
s->bus = b;
|
qom: Drop parameter @errp of object_property_add() & friends
The only way object_property_add() can fail is when a property with
the same name already exists. Since our property names are all
hardcoded, failure is a programming error, and the appropriate way to
handle it is passing &error_abort.
Same for its variants, except for object_property_add_child(), which
additionally fails when the child already has a parent. Parentage is
also under program control, so this is a programming error, too.
We have a bit over 500 callers. Almost half of them pass
&error_abort, slightly fewer ignore errors, one test case handles
errors, and the remaining few callers pass them to their own callers.
The previous few commits demonstrated once again that ignoring
programming errors is a bad idea.
Of the few ones that pass on errors, several violate the Error API.
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call. ich9_pm_add_properties(), sparc32_ledma_realize(),
sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize()
are wrong that way.
When the one appropriate choice of argument is &error_abort, letting
users pick the argument is a bad idea.
Drop parameter @errp and assert the preconditions instead.
There's one exception to "duplicate property name is a programming
error": the way object_property_add() implements the magic (and
undocumented) "automatic arrayification". Don't drop @errp there.
Instead, rename object_property_add() to object_property_try_add(),
and add the obvious wrapper object_property_add().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-15-armbru@redhat.com>
[Two semantic rebase conflicts resolved]
2020-05-05 18:29:22 +03:00
|
|
|
object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev));
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:32:34 +03:00
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
2009-07-22 17:17:01 +04:00
|
|
|
|
2015-07-15 08:37:41 +03:00
|
|
|
d = pci_create_simple(b, 0, pci_type);
|
2022-06-12 22:28:00 +03:00
|
|
|
f = I440FX_PCI_DEVICE(d);
|
2011-08-15 18:17:38 +04:00
|
|
|
f->system_memory = address_space_mem;
|
|
|
|
f->pci_address_space = pci_address_space;
|
|
|
|
f->ram_memory = ram_memory;
|
2013-07-29 18:47:57 +04:00
|
|
|
|
|
|
|
i440fx = I440FX_PCI_HOST_BRIDGE(dev);
|
2016-07-01 14:47:47 +03:00
|
|
|
range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
|
|
|
|
IO_APIC_DEFAULT_ADDRESS - 1);
|
2013-07-29 18:47:57 +04:00
|
|
|
|
2013-10-29 16:57:34 +04:00
|
|
|
/* setup pci memory mapping */
|
2023-01-05 20:38:26 +03:00
|
|
|
pc_pci_as_mapping_init(f->system_memory, f->pci_address_space);
|
2013-10-29 16:57:34 +04:00
|
|
|
|
2015-03-31 15:10:22 +03:00
|
|
|
/* if *disabled* show SMRAM to all CPUs */
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
|
2011-08-15 18:17:38 +04:00
|
|
|
f->pci_address_space, 0xa0000, 0x20000);
|
2011-12-04 22:06:16 +04:00
|
|
|
memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
|
|
|
|
&f->smram_region, 1);
|
2015-03-31 15:10:22 +03:00
|
|
|
memory_region_set_enabled(&f->smram_region, true);
|
|
|
|
|
|
|
|
/* smram, as seen by SMM CPUs */
|
2020-06-01 17:29:27 +03:00
|
|
|
memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB);
|
2015-03-31 15:10:22 +03:00
|
|
|
memory_region_set_enabled(&f->smram, true);
|
|
|
|
memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
|
2015-03-31 15:12:25 +03:00
|
|
|
f->ram_memory, 0xa0000, 0x20000);
|
2015-03-31 15:10:22 +03:00
|
|
|
memory_region_set_enabled(&f->low_smram, true);
|
|
|
|
memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
|
|
|
|
object_property_add_const_link(qdev_get_machine(), "smram",
|
qom: Drop parameter @errp of object_property_add() & friends
The only way object_property_add() can fail is when a property with
the same name already exists. Since our property names are all
hardcoded, failure is a programming error, and the appropriate way to
handle it is passing &error_abort.
Same for its variants, except for object_property_add_child(), which
additionally fails when the child already has a parent. Parentage is
also under program control, so this is a programming error, too.
We have a bit over 500 callers. Almost half of them pass
&error_abort, slightly fewer ignore errors, one test case handles
errors, and the remaining few callers pass them to their own callers.
The previous few commits demonstrated once again that ignoring
programming errors is a bad idea.
Of the few ones that pass on errors, several violate the Error API.
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call. ich9_pm_add_properties(), sparc32_ledma_realize(),
sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize()
are wrong that way.
When the one appropriate choice of argument is &error_abort, letting
users pick the argument is a bad idea.
Drop parameter @errp and assert the preconditions instead.
There's one exception to "duplicate property name is a programming
error": the way object_property_add() implements the magic (and
undocumented) "automatic arrayification". Don't drop @errp there.
Instead, rename object_property_add() to object_property_try_add(),
and add the obvious wrapper object_property_add().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-15-armbru@redhat.com>
[Two semantic rebase conflicts resolved]
2020-05-05 18:29:22 +03:00
|
|
|
OBJECT(&f->smram));
|
2015-03-31 15:10:22 +03:00
|
|
|
|
2013-06-25 14:33:01 +04:00
|
|
|
init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
|
2012-11-15 00:54:02 +04:00
|
|
|
&f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
|
2018-10-11 15:14:03 +03:00
|
|
|
for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
|
2013-06-25 14:33:01 +04:00
|
|
|
init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
|
2012-11-15 00:54:02 +04:00
|
|
|
&f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
|
|
|
|
PAM_EXPAN_SIZE);
|
2012-10-17 19:10:04 +04:00
|
|
|
}
|
2009-07-22 17:17:01 +04:00
|
|
|
|
2010-04-20 22:48:06 +04:00
|
|
|
ram_size = ram_size / 8 / 1024 / 1024;
|
2013-07-01 14:18:21 +04:00
|
|
|
if (ram_size > 255) {
|
2010-04-20 22:48:06 +04:00
|
|
|
ram_size = 255;
|
2013-07-01 14:18:21 +04:00
|
|
|
}
|
2015-08-07 22:15:31 +03:00
|
|
|
d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
|
2010-04-20 22:48:06 +04:00
|
|
|
|
2011-08-15 18:17:38 +04:00
|
|
|
i440fx_update_memory_mappings(f);
|
|
|
|
|
2006-05-13 20:11:23 +04:00
|
|
|
return b;
|
|
|
|
}
|
|
|
|
|
2011-12-04 22:22:06 +04:00
|
|
|
static void i440fx_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 22:22:06 +04:00
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
2015-01-19 17:52:30 +03:00
|
|
|
k->realize = i440fx_realize;
|
2011-12-04 22:22:06 +04:00
|
|
|
k->config_write = i440fx_write_config;
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_INTEL;
|
|
|
|
k->device_id = PCI_DEVICE_ID_INTEL_82441;
|
|
|
|
k->revision = 0x02;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_HOST;
|
2011-12-08 07:34:16 +04:00
|
|
|
dc->desc = "Host bridge";
|
|
|
|
dc->vmsd = &vmstate_i440fx;
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 20:26:58 +04:00
|
|
|
/*
|
|
|
|
* PCI-facing part of the host bridge, not usable without the
|
|
|
|
* host-facing part, which can't be device_add'ed, yet.
|
|
|
|
*/
|
2017-05-03 23:35:44 +03:00
|
|
|
dc->user_creatable = false;
|
2014-02-05 19:36:48 +04:00
|
|
|
dc->hotpluggable = false;
|
2011-12-04 22:22:06 +04:00
|
|
|
}
|
|
|
|
|
2012-08-20 21:07:56 +04:00
|
|
|
static const TypeInfo i440fx_info = {
|
2013-02-23 04:40:37 +04:00
|
|
|
.name = TYPE_I440FX_PCI_DEVICE,
|
2011-12-08 07:34:16 +04:00
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(PCII440FXState),
|
|
|
|
.class_init = i440fx_class_init,
|
2017-09-27 22:56:34 +03:00
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
|
|
{ },
|
|
|
|
},
|
2009-07-22 17:17:01 +04:00
|
|
|
};
|
|
|
|
|
2013-06-06 12:48:49 +04:00
|
|
|
static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
|
|
|
|
PCIBus *rootbus)
|
|
|
|
{
|
2013-11-06 03:46:27 +04:00
|
|
|
I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
|
|
|
|
|
2013-06-06 12:48:49 +04:00
|
|
|
/* For backwards compat with old device paths */
|
2013-11-06 03:46:27 +04:00
|
|
|
if (s->short_root_bus) {
|
|
|
|
return "0000";
|
|
|
|
}
|
|
|
|
return "0000:00";
|
2013-06-06 12:48:49 +04:00
|
|
|
}
|
|
|
|
|
2013-07-29 18:47:57 +04:00
|
|
|
static Property i440fx_props[] = {
|
|
|
|
DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
|
2017-11-11 18:25:00 +03:00
|
|
|
pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
|
2013-11-06 03:46:27 +04:00
|
|
|
DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
|
2017-11-11 18:25:00 +03:00
|
|
|
DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
|
2013-07-29 18:47:57 +04:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2012-01-24 23:12:29 +04:00
|
|
|
static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2013-06-06 12:48:49 +04:00
|
|
|
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
|
2012-01-24 23:12:29 +04:00
|
|
|
|
2013-06-06 12:48:49 +04:00
|
|
|
hc->root_bus_path = i440fx_pcihost_root_bus_path;
|
2013-07-01 14:18:20 +04:00
|
|
|
dc->realize = i440fx_pcihost_realize;
|
2011-12-08 07:34:16 +04:00
|
|
|
dc->fw_name = "pci";
|
2020-01-10 18:30:32 +03:00
|
|
|
device_class_set_props(dc, i440fx_props);
|
2016-06-27 18:38:33 +03:00
|
|
|
/* Reason: needs to be wired up by pc_init1 */
|
2017-05-03 23:35:44 +03:00
|
|
|
dc->user_creatable = false;
|
2020-09-22 01:10:43 +03:00
|
|
|
|
|
|
|
object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
|
|
|
|
i440fx_pcihost_get_pci_hole_start,
|
|
|
|
NULL, NULL, NULL);
|
|
|
|
|
|
|
|
object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
|
|
|
|
i440fx_pcihost_get_pci_hole_end,
|
|
|
|
NULL, NULL, NULL);
|
|
|
|
|
|
|
|
object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
|
|
|
|
i440fx_pcihost_get_pci_hole64_start,
|
|
|
|
NULL, NULL, NULL);
|
|
|
|
|
|
|
|
object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
|
|
|
|
i440fx_pcihost_get_pci_hole64_end,
|
|
|
|
NULL, NULL, NULL);
|
2012-01-24 23:12:29 +04:00
|
|
|
}
|
|
|
|
|
2012-08-20 21:07:56 +04:00
|
|
|
static const TypeInfo i440fx_pcihost_info = {
|
2013-07-29 18:47:52 +04:00
|
|
|
.name = TYPE_I440FX_PCI_HOST_BRIDGE,
|
2012-08-20 21:08:08 +04:00
|
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
2011-12-08 07:34:16 +04:00
|
|
|
.instance_size = sizeof(I440FXState),
|
2013-07-01 14:18:20 +04:00
|
|
|
.instance_init = i440fx_pcihost_initfn,
|
2011-12-08 07:34:16 +04:00
|
|
|
.class_init = i440fx_pcihost_class_init,
|
2009-07-22 17:17:01 +04:00
|
|
|
};
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
static void i440fx_register_types(void)
|
2009-07-22 17:17:01 +04:00
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&i440fx_info);
|
|
|
|
type_register_static(&i440fx_pcihost_info);
|
2009-07-22 17:17:01 +04:00
|
|
|
}
|
2012-02-09 18:20:55 +04:00
|
|
|
|
|
|
|
type_init(i440fx_register_types)
|