i440fx: avoid destroying memory regions within a transaction
Calling memory_region_destroy() within a transaction is illegal, since the memory API is allowed to continue to dispatch to a region until the transaction commits. 440fx does that however when managing PAM registers. This bug is benign, since the regions are all aliases (which the memory core tends to throw anyway), and since we don't do concurrent dispatch yet, but instead of relying on that, tighten ship ahead of the coming concurrency storm. Fix by having a predefined set of regions, of which one will be enabled at any time. Signed-off-by: Avi Kivity <avi@redhat.com>
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@ -69,8 +69,8 @@ typedef struct PIIX3State {
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} PIIX3State;
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typedef struct PAMMemoryRegion {
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MemoryRegion mem;
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bool initialized;
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MemoryRegion alias[4]; /* index = PAM value */
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unsigned current;
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} PAMMemoryRegion;
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struct PCII440FXState {
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@ -105,37 +105,35 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
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return (pci_intx + slot_addend) & 3;
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}
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static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
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PAMMemoryRegion *mem)
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static void init_pam(PCII440FXState *d, PAMMemoryRegion *mem,
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uint32_t start, uint32_t size)
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{
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if (mem->initialized) {
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memory_region_del_subregion(d->system_memory, &mem->mem);
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memory_region_destroy(&mem->mem);
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}
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int i;
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// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
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switch(r) {
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case 3:
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/* RAM */
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memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
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start, end - start);
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break;
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case 1:
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/* ROM (XXX: not quite correct) */
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memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
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start, end - start);
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memory_region_set_readonly(&mem->mem, true);
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break;
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case 2:
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case 0:
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/* XXX: should distinguish read/write cases */
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memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
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start, end - start);
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break;
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/* RAM */
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memory_region_init_alias(&mem->alias[3], "pam-ram", d->ram_memory, start, size);
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/* ROM (XXX: not quite correct) */
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memory_region_init_alias(&mem->alias[1], "pam-rom", d->ram_memory, start, size);
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memory_region_set_readonly(&mem->alias[1], true);
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/* XXX: should distinguish read/write cases */
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memory_region_init_alias(&mem->alias[0], "pam-pci", d->pci_address_space,
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start, size);
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memory_region_init_alias(&mem->alias[2], "pam-pci", d->pci_address_space,
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start, size);
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for (i = 0; i < 4; ++i) {
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memory_region_set_enabled(&mem->alias[i], false);
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memory_region_add_subregion_overlap(d->system_memory, start, &mem->alias[i], 1);
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}
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memory_region_add_subregion_overlap(d->system_memory,
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start, &mem->mem, 1);
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mem->initialized = true;
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mem->current = 0;
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}
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static void update_pam(PAMMemoryRegion *pam, unsigned r)
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{
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memory_region_set_enabled(&pam->alias[pam->current], false);
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pam->current = r;
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memory_region_set_enabled(&pam->alias[pam->current], true);
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}
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static void i440fx_update_memory_mappings(PCII440FXState *d)
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@ -145,12 +143,10 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
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bool smram_enabled;
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memory_region_transaction_begin();
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update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
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&d->pam_regions[0]);
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update_pam(&d->pam_regions[0], (d->dev.config[I440FX_PAM] >> 4) & 3);
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for(i = 0; i < 12; i++) {
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r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
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update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
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&d->pam_regions[i+1]);
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update_pam(&d->pam_regions[i+1], r);
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}
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smram = d->dev.config[I440FX_SMRAM];
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smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
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@ -272,6 +268,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
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PCIHostState *s;
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PIIX3State *piix3;
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PCII440FXState *f;
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unsigned i;
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dev = qdev_create(NULL, "i440FX-pcihost");
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s = PCI_HOST_BRIDGE(dev);
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@ -303,6 +300,10 @@ static PCIBus *i440fx_common_init(const char *device_name,
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memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
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&f->smram_region, 1);
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memory_region_set_enabled(&f->smram_region, false);
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init_pam(f, &f->pam_regions[0], 0xf0000, 0x10000);
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for (i = 0; i < 12; ++i) {
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init_pam(f, &f->pam_regions[i+1], 0xc0000 + i * 0x4000, 0x4000);
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}
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/* Xen supports additional interrupt routes from the PCI devices to
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* the IOAPIC: the four pins of each PCI device on the bus are also
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