2010-04-27 13:50:11 +04:00
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/*
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* Copyright (C) 2010 Red Hat, Inc.
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*
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* written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
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* maintained by Gerd Hoffmann <kraxel@redhat.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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2016-01-26 21:17:13 +03:00
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#include "qemu/osdep.h"
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2012-09-12 17:13:28 +04:00
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#include <zlib.h>
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2010-04-27 13:50:11 +04:00
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#include "qemu-common.h"
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2012-12-17 21:20:00 +04:00
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#include "qemu/timer.h"
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#include "qemu/queue.h"
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2013-05-13 15:29:47 +04:00
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#include "qemu/atomic.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/sysemu.h"
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2012-03-18 16:46:14 +04:00
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#include "trace.h"
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2010-04-27 13:50:11 +04:00
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2013-03-18 20:36:02 +04:00
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#include "qxl.h"
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2010-04-27 13:50:11 +04:00
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2012-04-25 13:13:21 +04:00
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/*
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* NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
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* such can be changed by the guest, so to avoid a guest trigerrable
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2012-05-24 13:38:12 +04:00
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* abort we just qxl_set_guest_bug and set the return to NULL. Still
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2012-04-25 13:13:21 +04:00
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* it may happen as a result of emulator bug as well.
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*/
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2010-04-27 13:50:11 +04:00
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#undef SPICE_RING_PROD_ITEM
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2012-04-25 13:13:21 +04:00
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#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
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2010-04-27 13:50:11 +04:00
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uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
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2013-01-10 17:24:49 +04:00
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if (prod >= ARRAY_SIZE((r)->items)) { \
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2012-05-24 13:38:12 +04:00
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qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
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2013-01-10 17:24:49 +04:00
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"%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
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2012-04-25 13:13:21 +04:00
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ret = NULL; \
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} else { \
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2013-01-10 17:24:49 +04:00
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ret = &(r)->items[prod].el; \
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2010-04-27 13:50:11 +04:00
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} \
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}
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#undef SPICE_RING_CONS_ITEM
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2012-04-25 13:13:21 +04:00
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#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
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2010-04-27 13:50:11 +04:00
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uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
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2013-01-10 17:24:49 +04:00
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if (cons >= ARRAY_SIZE((r)->items)) { \
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2012-05-24 13:38:12 +04:00
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qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
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2013-01-10 17:24:49 +04:00
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"%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
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2012-04-25 13:13:21 +04:00
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ret = NULL; \
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} else { \
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2013-01-10 17:24:49 +04:00
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ret = &(r)->items[cons].el; \
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2010-04-27 13:50:11 +04:00
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} \
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}
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#undef ALIGN
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#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
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#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
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#define QXL_MODE(_x, _y, _b, _o) \
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{ .x_res = _x, \
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.y_res = _y, \
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.bits = _b, \
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.stride = (_x) * (_b) / 8, \
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.x_mili = PIXEL_SIZE * (_x), \
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.y_mili = PIXEL_SIZE * (_y), \
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.orientation = _o, \
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}
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#define QXL_MODE_16_32(x_res, y_res, orientation) \
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QXL_MODE(x_res, y_res, 16, orientation), \
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QXL_MODE(x_res, y_res, 32, orientation)
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#define QXL_MODE_EX(x_res, y_res) \
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QXL_MODE_16_32(x_res, y_res, 0), \
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2013-01-21 16:48:07 +04:00
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QXL_MODE_16_32(x_res, y_res, 1)
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2010-04-27 13:50:11 +04:00
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static QXLMode qxl_modes[] = {
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QXL_MODE_EX(640, 480),
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QXL_MODE_EX(800, 480),
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QXL_MODE_EX(800, 600),
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QXL_MODE_EX(832, 624),
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QXL_MODE_EX(960, 640),
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QXL_MODE_EX(1024, 600),
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QXL_MODE_EX(1024, 768),
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QXL_MODE_EX(1152, 864),
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QXL_MODE_EX(1152, 870),
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QXL_MODE_EX(1280, 720),
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QXL_MODE_EX(1280, 760),
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QXL_MODE_EX(1280, 768),
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QXL_MODE_EX(1280, 800),
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QXL_MODE_EX(1280, 960),
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QXL_MODE_EX(1280, 1024),
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QXL_MODE_EX(1360, 768),
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QXL_MODE_EX(1366, 768),
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QXL_MODE_EX(1400, 1050),
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QXL_MODE_EX(1440, 900),
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QXL_MODE_EX(1600, 900),
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QXL_MODE_EX(1600, 1200),
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QXL_MODE_EX(1680, 1050),
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QXL_MODE_EX(1920, 1080),
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/* these modes need more than 8 MB video memory */
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QXL_MODE_EX(1920, 1200),
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QXL_MODE_EX(1920, 1440),
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2013-04-04 12:15:34 +04:00
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QXL_MODE_EX(2000, 2000),
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2010-04-27 13:50:11 +04:00
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QXL_MODE_EX(2048, 1536),
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2013-04-04 12:15:34 +04:00
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QXL_MODE_EX(2048, 2048),
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2010-04-27 13:50:11 +04:00
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QXL_MODE_EX(2560, 1440),
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QXL_MODE_EX(2560, 1600),
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/* these modes need more than 16 MB video memory */
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QXL_MODE_EX(2560, 2048),
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QXL_MODE_EX(2800, 2100),
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QXL_MODE_EX(3200, 2400),
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2015-02-17 19:30:50 +03:00
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/* these modes need more than 32 MB video memory */
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2013-03-15 14:53:47 +04:00
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QXL_MODE_EX(3840, 2160), /* 4k mainstream */
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QXL_MODE_EX(4096, 2160), /* 4k */
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2015-02-17 19:30:50 +03:00
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/* these modes need more than 64 MB video memory */
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2013-03-15 14:53:47 +04:00
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QXL_MODE_EX(7680, 4320), /* 8k mainstream */
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2015-02-17 19:30:50 +03:00
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/* these modes need more than 128 MB video memory */
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2013-03-15 14:53:47 +04:00
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QXL_MODE_EX(8192, 4320), /* 8k */
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2010-04-27 13:50:11 +04:00
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};
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static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
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2011-07-20 13:20:58 +04:00
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static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
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2010-04-27 13:50:11 +04:00
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static void qxl_reset_memslots(PCIQXLDevice *d);
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static void qxl_reset_surfaces(PCIQXLDevice *d);
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static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
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2014-09-24 19:05:45 +04:00
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static void qxl_hw_update(void *opaque);
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2012-05-24 13:38:12 +04:00
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void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
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2011-07-20 13:20:55 +04:00
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{
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2012-09-12 17:13:26 +04:00
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trace_qxl_set_guest_bug(qxl->id);
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2011-07-20 13:20:55 +04:00
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qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
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2012-05-24 20:18:54 +04:00
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qxl->guest_bug = 1;
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2011-07-20 13:20:55 +04:00
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if (qxl->guestdebug) {
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2011-07-20 13:20:56 +04:00
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va_list ap;
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va_start(ap, msg);
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fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
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vfprintf(stderr, msg, ap);
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fprintf(stderr, "\n");
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va_end(ap);
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2011-07-20 13:20:55 +04:00
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}
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}
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2012-05-24 20:18:54 +04:00
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static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
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{
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qxl->guest_bug = 0;
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}
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2011-07-20 13:20:52 +04:00
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void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
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struct QXLRect *area, struct QXLRect *dirty_rects,
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uint32_t num_dirty_rects,
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2011-07-20 13:20:58 +04:00
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uint32_t clear_dirty_region,
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2012-02-25 01:19:30 +04:00
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qxl_async_io async, struct QXLCookie *cookie)
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2011-07-20 13:20:52 +04:00
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{
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2012-03-18 16:46:14 +04:00
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trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
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area->top, area->bottom);
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trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
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clear_dirty_region);
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2011-07-20 13:20:58 +04:00
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if (async == QXL_SYNC) {
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2013-10-04 15:10:46 +04:00
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spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
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2011-07-20 13:20:58 +04:00
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dirty_rects, num_dirty_rects, clear_dirty_region);
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} else {
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2012-02-25 01:19:30 +04:00
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assert(cookie != NULL);
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2011-07-20 13:20:58 +04:00
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spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
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2012-03-16 17:50:04 +04:00
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clear_dirty_region, (uintptr_t)cookie);
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2011-07-20 13:20:58 +04:00
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}
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2011-07-20 13:20:52 +04:00
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}
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2011-07-20 13:20:58 +04:00
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static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
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uint32_t id)
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2011-07-20 13:20:52 +04:00
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{
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2012-03-18 16:46:14 +04:00
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trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
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2011-07-20 13:20:53 +04:00
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qemu_mutex_lock(&qxl->track_lock);
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qxl->guest_surfaces.cmds[id] = 0;
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qxl->guest_surfaces.count--;
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qemu_mutex_unlock(&qxl->track_lock);
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2011-07-20 13:20:52 +04:00
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}
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2011-07-20 13:20:58 +04:00
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static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
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qxl_async_io async)
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{
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2012-02-25 01:19:30 +04:00
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QXLCookie *cookie;
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2012-03-18 16:46:14 +04:00
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trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
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2011-07-20 13:20:58 +04:00
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if (async) {
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2012-02-25 01:19:30 +04:00
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cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
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QXL_IO_DESTROY_SURFACE_ASYNC);
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cookie->u.surface_id = id;
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2012-03-16 17:50:04 +04:00
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spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
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2011-07-20 13:20:58 +04:00
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} else {
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2013-10-04 15:10:46 +04:00
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spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
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2012-09-11 11:09:58 +04:00
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qxl_spice_destroy_surface_wait_complete(qxl, id);
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2011-07-20 13:20:58 +04:00
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}
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}
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2011-07-20 13:20:59 +04:00
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static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
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{
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2012-03-18 16:46:14 +04:00
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trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
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qxl->num_free_res);
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2012-02-25 01:19:30 +04:00
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spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
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2012-03-16 17:50:04 +04:00
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(uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
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QXL_IO_FLUSH_SURFACES_ASYNC));
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2011-07-20 13:20:59 +04:00
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}
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2011-07-20 13:20:52 +04:00
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void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
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uint32_t count)
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{
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2012-03-18 16:46:14 +04:00
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trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
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2013-10-04 15:10:46 +04:00
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spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
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2011-07-20 13:20:52 +04:00
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}
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void qxl_spice_oom(PCIQXLDevice *qxl)
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{
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2012-03-18 16:46:14 +04:00
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trace_qxl_spice_oom(qxl->id);
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2013-10-04 15:10:46 +04:00
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spice_qxl_oom(&qxl->ssd.qxl);
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2011-07-20 13:20:52 +04:00
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}
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void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
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{
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2012-03-18 16:46:14 +04:00
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trace_qxl_spice_reset_memslots(qxl->id);
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2013-10-04 15:10:46 +04:00
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spice_qxl_reset_memslots(&qxl->ssd.qxl);
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2011-07-20 13:20:52 +04:00
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}
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2011-07-20 13:20:58 +04:00
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static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
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2011-07-20 13:20:52 +04:00
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{
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2012-03-18 16:46:14 +04:00
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trace_qxl_spice_destroy_surfaces_complete(qxl->id);
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2011-07-20 13:20:53 +04:00
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qemu_mutex_lock(&qxl->track_lock);
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2012-09-04 13:39:41 +04:00
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memset(qxl->guest_surfaces.cmds, 0,
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2013-03-13 19:58:35 +04:00
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sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
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2011-07-20 13:20:53 +04:00
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qxl->guest_surfaces.count = 0;
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qemu_mutex_unlock(&qxl->track_lock);
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2011-07-20 13:20:52 +04:00
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}
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2011-07-20 13:20:58 +04:00
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static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
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{
|
2012-03-18 16:46:14 +04:00
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trace_qxl_spice_destroy_surfaces(qxl->id, async);
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2011-07-20 13:20:58 +04:00
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if (async) {
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2012-02-25 01:19:30 +04:00
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spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
|
2012-03-16 17:50:04 +04:00
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(uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
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QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
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2011-07-20 13:20:58 +04:00
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} else {
|
2013-10-04 15:10:46 +04:00
|
|
|
spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
|
2011-07-20 13:20:58 +04:00
|
|
|
qxl_spice_destroy_surfaces_complete(qxl);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-22 12:16:25 +04:00
|
|
|
static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
|
|
|
|
{
|
|
|
|
trace_qxl_spice_monitors_config(qxl->id);
|
|
|
|
if (replay) {
|
|
|
|
/*
|
|
|
|
* don't use QXL_COOKIE_TYPE_IO:
|
|
|
|
* - we are not running yet (post_load), we will assert
|
|
|
|
* in send_events
|
|
|
|
* - this is not a guest io, but a reply, so async_io isn't set.
|
|
|
|
*/
|
|
|
|
spice_qxl_monitors_config_async(&qxl->ssd.qxl,
|
|
|
|
qxl->guest_monitors_config,
|
|
|
|
MEMSLOT_GROUP_GUEST,
|
|
|
|
(uintptr_t)qxl_cookie_new(
|
|
|
|
QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
|
|
|
|
0));
|
|
|
|
} else {
|
2015-07-06 09:56:38 +03:00
|
|
|
#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
|
|
|
|
if (qxl->max_outputs) {
|
2015-07-20 11:43:23 +03:00
|
|
|
spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
|
2015-07-06 09:56:38 +03:00
|
|
|
}
|
|
|
|
#endif
|
2012-08-22 12:16:25 +04:00
|
|
|
qxl->guest_monitors_config = qxl->ram->monitors_config;
|
|
|
|
spice_qxl_monitors_config_async(&qxl->ssd.qxl,
|
|
|
|
qxl->ram->monitors_config,
|
|
|
|
MEMSLOT_GROUP_GUEST,
|
|
|
|
(uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
|
|
|
|
QXL_IO_MONITORS_CONFIG_ASYNC));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-07-20 13:20:52 +04:00
|
|
|
void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
|
|
|
|
{
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_spice_reset_image_cache(qxl->id);
|
2013-10-04 15:10:46 +04:00
|
|
|
spice_qxl_reset_image_cache(&qxl->ssd.qxl);
|
2011-07-20 13:20:52 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
|
|
|
|
{
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_spice_reset_cursor(qxl->id);
|
2013-10-04 15:10:46 +04:00
|
|
|
spice_qxl_reset_cursor(&qxl->ssd.qxl);
|
2011-10-18 20:58:54 +04:00
|
|
|
qemu_mutex_lock(&qxl->track_lock);
|
|
|
|
qxl->guest_cursor = 0;
|
|
|
|
qemu_mutex_unlock(&qxl->track_lock);
|
2012-09-15 00:17:44 +04:00
|
|
|
if (qxl->ssd.cursor) {
|
|
|
|
cursor_put(qxl->ssd.cursor);
|
|
|
|
}
|
|
|
|
qxl->ssd.cursor = cursor_builtin_hidden();
|
2011-07-20 13:20:52 +04:00
|
|
|
}
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
static ram_addr_t qxl_rom_size(void)
|
|
|
|
{
|
2013-01-21 16:48:07 +04:00
|
|
|
uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
|
|
|
|
sizeof(qxl_modes);
|
|
|
|
uint32_t rom_size = 8192; /* two pages */
|
2012-06-10 19:05:06 +04:00
|
|
|
|
2013-09-11 15:08:49 +04:00
|
|
|
QEMU_BUILD_BUG_ON(required_rom_size > rom_size);
|
2010-04-27 13:50:11 +04:00
|
|
|
return rom_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void init_qxl_rom(PCIQXLDevice *d)
|
|
|
|
{
|
2011-08-08 17:08:57 +04:00
|
|
|
QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
|
2010-04-27 13:50:11 +04:00
|
|
|
QXLModes *modes = (QXLModes *)(rom + 1);
|
|
|
|
uint32_t ram_header_size;
|
|
|
|
uint32_t surface0_area_size;
|
|
|
|
uint32_t num_pages;
|
2012-06-10 19:05:06 +04:00
|
|
|
uint32_t fb;
|
|
|
|
int i, n;
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
memset(rom, 0, d->rom_size);
|
|
|
|
|
|
|
|
rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
|
|
|
|
rom->id = cpu_to_le32(d->id);
|
|
|
|
rom->log_level = cpu_to_le32(d->guestdebug);
|
|
|
|
rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
|
|
|
|
|
|
|
|
rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
|
|
|
|
rom->slot_id_bits = MEMSLOT_SLOT_BITS;
|
|
|
|
rom->slots_start = 1;
|
|
|
|
rom->slots_end = NUM_MEMSLOTS - 1;
|
2012-09-04 13:39:41 +04:00
|
|
|
rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2012-06-10 19:05:06 +04:00
|
|
|
for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
|
2010-04-27 13:50:11 +04:00
|
|
|
fb = qxl_modes[i].y_res * qxl_modes[i].stride;
|
2012-06-10 19:05:06 +04:00
|
|
|
if (fb > d->vgamem_size) {
|
|
|
|
continue;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
2012-06-10 19:05:06 +04:00
|
|
|
modes->modes[n].id = cpu_to_le32(i);
|
|
|
|
modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
|
|
|
|
modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
|
|
|
|
modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
|
|
|
|
modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
|
|
|
|
modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
|
|
|
|
modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
|
|
|
|
modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
modes->n_modes = cpu_to_le32(n);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
ram_header_size = ALIGN(sizeof(QXLRam), 4096);
|
2012-06-10 19:05:06 +04:00
|
|
|
surface0_area_size = ALIGN(d->vgamem_size, 4096);
|
2010-04-27 13:50:11 +04:00
|
|
|
num_pages = d->vga.vram_size;
|
|
|
|
num_pages -= ram_header_size;
|
|
|
|
num_pages -= surface0_area_size;
|
2013-09-11 15:14:25 +04:00
|
|
|
num_pages = num_pages / QXL_PAGE_SIZE;
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2015-02-17 19:30:51 +03:00
|
|
|
assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
rom->draw_area_offset = cpu_to_le32(0);
|
|
|
|
rom->surface0_area_size = cpu_to_le32(surface0_area_size);
|
|
|
|
rom->pages_offset = cpu_to_le32(surface0_area_size);
|
|
|
|
rom->num_pages = cpu_to_le32(num_pages);
|
|
|
|
rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
|
|
|
|
|
|
|
|
d->shadow_rom = *rom;
|
|
|
|
d->rom = rom;
|
|
|
|
d->modes = modes;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void init_qxl_ram(PCIQXLDevice *d)
|
|
|
|
{
|
|
|
|
uint8_t *buf;
|
|
|
|
uint64_t *item;
|
|
|
|
|
|
|
|
buf = d->vga.vram_ptr;
|
|
|
|
d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
|
|
|
|
d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
|
|
|
|
d->ram->int_pending = cpu_to_le32(0);
|
|
|
|
d->ram->int_mask = cpu_to_le32(0);
|
2011-10-23 19:03:52 +04:00
|
|
|
d->ram->update_surface = 0;
|
2013-06-17 20:38:26 +04:00
|
|
|
d->ram->monitors_config = 0;
|
2010-04-27 13:50:11 +04:00
|
|
|
SPICE_RING_INIT(&d->ram->cmd_ring);
|
|
|
|
SPICE_RING_INIT(&d->ram->cursor_ring);
|
|
|
|
SPICE_RING_INIT(&d->ram->release_ring);
|
2012-04-25 13:13:21 +04:00
|
|
|
SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
|
|
|
|
assert(item);
|
2010-04-27 13:50:11 +04:00
|
|
|
*item = 0;
|
|
|
|
qxl_ring_set_dirty(d);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* can be called from spice server thread context */
|
2011-08-08 17:08:57 +04:00
|
|
|
static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
2011-10-16 20:04:59 +04:00
|
|
|
memory_region_set_dirty(mr, addr, end - addr);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
|
|
|
|
{
|
2011-08-08 17:08:57 +04:00
|
|
|
qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* called from spice server thread context only */
|
|
|
|
static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
|
|
|
|
{
|
|
|
|
void *base = qxl->vga.vram_ptr;
|
|
|
|
intptr_t offset;
|
|
|
|
|
|
|
|
offset = ptr - base;
|
|
|
|
assert(offset < qxl->vga.vram_size);
|
2013-09-11 15:15:48 +04:00
|
|
|
qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* can be called from spice server thread context */
|
|
|
|
static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
|
|
|
|
{
|
2011-08-08 17:08:57 +04:00
|
|
|
ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
|
|
|
|
ram_addr_t end = qxl->vga.vram_size;
|
|
|
|
qxl_set_dirty(&qxl->vga.vram, addr, end);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* keep track of some command state, for savevm/loadvm.
|
|
|
|
* called from spice server thread context only
|
|
|
|
*/
|
2012-04-25 13:13:18 +04:00
|
|
|
static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
switch (le32_to_cpu(ext->cmd.type)) {
|
|
|
|
case QXL_CMD_SURFACE:
|
|
|
|
{
|
|
|
|
QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
|
2012-04-25 13:13:18 +04:00
|
|
|
|
|
|
|
if (!cmd) {
|
|
|
|
return 1;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
uint32_t id = le32_to_cpu(cmd->surface_id);
|
2012-04-25 13:13:19 +04:00
|
|
|
|
2012-09-04 13:39:41 +04:00
|
|
|
if (id >= qxl->ssd.num_surfaces) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
|
2012-09-04 13:39:41 +04:00
|
|
|
qxl->ssd.num_surfaces);
|
2012-04-25 13:13:19 +04:00
|
|
|
return 1;
|
|
|
|
}
|
2012-10-15 16:54:03 +04:00
|
|
|
if (cmd->type == QXL_SURFACE_CMD_CREATE &&
|
|
|
|
(cmd->u.surface_create.stride & 0x03) != 0) {
|
|
|
|
qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
|
|
|
|
cmd->u.surface_create.stride);
|
|
|
|
return 1;
|
|
|
|
}
|
2011-07-20 13:20:53 +04:00
|
|
|
qemu_mutex_lock(&qxl->track_lock);
|
2010-04-27 13:50:11 +04:00
|
|
|
if (cmd->type == QXL_SURFACE_CMD_CREATE) {
|
|
|
|
qxl->guest_surfaces.cmds[id] = ext->cmd.data;
|
|
|
|
qxl->guest_surfaces.count++;
|
|
|
|
if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
|
|
|
|
qxl->guest_surfaces.max = qxl->guest_surfaces.count;
|
|
|
|
}
|
|
|
|
if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
|
|
|
|
qxl->guest_surfaces.cmds[id] = 0;
|
|
|
|
qxl->guest_surfaces.count--;
|
|
|
|
}
|
2011-07-20 13:20:53 +04:00
|
|
|
qemu_mutex_unlock(&qxl->track_lock);
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case QXL_CMD_CURSOR:
|
|
|
|
{
|
|
|
|
QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
|
2012-04-25 13:13:18 +04:00
|
|
|
|
|
|
|
if (!cmd) {
|
|
|
|
return 1;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
if (cmd->type == QXL_CURSOR_SET) {
|
2011-10-18 20:58:54 +04:00
|
|
|
qemu_mutex_lock(&qxl->track_lock);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl->guest_cursor = ext->cmd.data;
|
2011-10-18 20:58:54 +04:00
|
|
|
qemu_mutex_unlock(&qxl->track_lock);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2012-04-25 13:13:18 +04:00
|
|
|
return 0;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* spice display interface callbacks */
|
|
|
|
|
|
|
|
static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_interface_attach_worker(qxl->id);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl->ssd.worker = qxl_worker;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void interface_set_compression_level(QXLInstance *sin, int level)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_interface_set_compression_level(qxl->id, level);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl->shadow_rom.compression_level = cpu_to_le32(level);
|
|
|
|
qxl->rom->compression_level = cpu_to_le32(level);
|
|
|
|
qxl_rom_set_dirty(qxl);
|
|
|
|
}
|
|
|
|
|
2016-06-30 01:41:35 +03:00
|
|
|
#if SPICE_NEEDS_SET_MM_TIME
|
2010-04-27 13:50:11 +04:00
|
|
|
static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
|
2015-05-12 12:54:34 +03:00
|
|
|
if (!qemu_spice_display_is_running(&qxl->ssd)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_interface_set_mm_time(qxl->id, mm_time);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
|
|
|
|
qxl->rom->mm_clock = cpu_to_le32(mm_time);
|
|
|
|
qxl_rom_set_dirty(qxl);
|
|
|
|
}
|
2016-06-30 01:41:35 +03:00
|
|
|
#endif
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_interface_get_init_info(qxl->id);
|
2010-04-27 13:50:11 +04:00
|
|
|
info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
|
|
|
|
info->memslot_id_bits = MEMSLOT_SLOT_BITS;
|
|
|
|
info->num_memslots = NUM_MEMSLOTS;
|
|
|
|
info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
|
|
|
|
info->internal_groupslot_id = 0;
|
2013-09-11 15:14:25 +04:00
|
|
|
info->qxl_ram_size =
|
|
|
|
le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
|
2012-09-04 13:39:41 +04:00
|
|
|
info->n_surfaces = qxl->ssd.num_surfaces;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2011-06-24 17:02:47 +04:00
|
|
|
static const char *qxl_mode_to_string(int mode)
|
|
|
|
{
|
|
|
|
switch (mode) {
|
|
|
|
case QXL_MODE_COMPAT:
|
|
|
|
return "compat";
|
|
|
|
case QXL_MODE_NATIVE:
|
|
|
|
return "native";
|
|
|
|
case QXL_MODE_UNDEFINED:
|
|
|
|
return "undefined";
|
|
|
|
case QXL_MODE_VGA:
|
|
|
|
return "vga";
|
|
|
|
}
|
|
|
|
return "INVALID";
|
|
|
|
}
|
|
|
|
|
2011-07-20 13:20:54 +04:00
|
|
|
static const char *io_port_to_string(uint32_t io_port)
|
|
|
|
{
|
|
|
|
if (io_port >= QXL_IO_RANGE_SIZE) {
|
|
|
|
return "out of range";
|
|
|
|
}
|
|
|
|
static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
|
|
|
|
[QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
|
|
|
|
[QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
|
|
|
|
[QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
|
|
|
|
[QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
|
|
|
|
[QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
|
|
|
|
[QXL_IO_RESET] = "QXL_IO_RESET",
|
|
|
|
[QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
|
|
|
|
[QXL_IO_LOG] = "QXL_IO_LOG",
|
|
|
|
[QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
|
|
|
|
[QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
|
|
|
|
[QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
|
|
|
|
[QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
|
|
|
|
[QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
|
|
|
|
[QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
|
|
|
|
[QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
|
|
|
|
[QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
|
|
|
|
[QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
|
|
|
|
[QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
|
|
|
|
[QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
|
|
|
|
[QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
|
|
|
|
[QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
|
|
|
|
[QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
|
|
|
|
= "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
|
|
|
|
[QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
|
|
|
|
[QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
|
2012-08-22 12:16:25 +04:00
|
|
|
[QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
|
2011-07-20 13:20:54 +04:00
|
|
|
};
|
|
|
|
return io_port_to_string[io_port];
|
|
|
|
}
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
/* called from spice server thread context only */
|
|
|
|
static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
SimpleSpiceUpdate *update;
|
|
|
|
QXLCommandRing *ring;
|
|
|
|
QXLCommand *cmd;
|
2011-04-27 17:21:51 +04:00
|
|
|
int notify, ret;
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
switch (qxl->mode) {
|
|
|
|
case QXL_MODE_VGA:
|
2011-04-27 17:21:51 +04:00
|
|
|
ret = false;
|
|
|
|
qemu_mutex_lock(&qxl->ssd.lock);
|
2012-09-05 10:25:08 +04:00
|
|
|
update = QTAILQ_FIRST(&qxl->ssd.updates);
|
|
|
|
if (update != NULL) {
|
|
|
|
QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
|
2011-04-27 17:21:51 +04:00
|
|
|
*ext = update->ext;
|
|
|
|
ret = true;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
2011-04-27 17:21:51 +04:00
|
|
|
qemu_mutex_unlock(&qxl->ssd.lock);
|
2011-05-18 18:34:36 +04:00
|
|
|
if (ret) {
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
|
2011-05-18 18:34:36 +04:00
|
|
|
qxl_log_command(qxl, "vga", ext);
|
|
|
|
}
|
2011-04-27 17:21:51 +04:00
|
|
|
return ret;
|
2010-04-27 13:50:11 +04:00
|
|
|
case QXL_MODE_COMPAT:
|
|
|
|
case QXL_MODE_NATIVE:
|
|
|
|
case QXL_MODE_UNDEFINED:
|
|
|
|
ring = &qxl->ram->cmd_ring;
|
2012-05-24 20:18:54 +04:00
|
|
|
if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
|
2010-04-27 13:50:11 +04:00
|
|
|
return false;
|
|
|
|
}
|
2012-04-25 13:13:21 +04:00
|
|
|
SPICE_RING_CONS_ITEM(qxl, ring, cmd);
|
|
|
|
if (!cmd) {
|
|
|
|
return false;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
ext->cmd = *cmd;
|
|
|
|
ext->group_id = MEMSLOT_GROUP_GUEST;
|
|
|
|
ext->flags = qxl->cmdflags;
|
|
|
|
SPICE_RING_POP(ring, notify);
|
|
|
|
qxl_ring_set_dirty(qxl);
|
|
|
|
if (notify) {
|
|
|
|
qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
|
|
|
|
}
|
|
|
|
qxl->guest_primary.commands++;
|
|
|
|
qxl_track_command(qxl, ext);
|
|
|
|
qxl_log_command(qxl, "cmd", ext);
|
2012-04-25 13:13:21 +04:00
|
|
|
trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
|
2010-04-27 13:50:11 +04:00
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called from spice server thread context only */
|
|
|
|
static int interface_req_cmd_notification(QXLInstance *sin)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
int wait = 1;
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_ring_command_req_notification(qxl->id);
|
2010-04-27 13:50:11 +04:00
|
|
|
switch (qxl->mode) {
|
|
|
|
case QXL_MODE_COMPAT:
|
|
|
|
case QXL_MODE_NATIVE:
|
|
|
|
case QXL_MODE_UNDEFINED:
|
|
|
|
SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
|
|
|
|
qxl_ring_set_dirty(qxl);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return wait;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called from spice server thread context only */
|
|
|
|
static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
|
|
|
|
{
|
|
|
|
QXLReleaseRing *ring = &d->ram->release_ring;
|
|
|
|
uint64_t *item;
|
|
|
|
int notify;
|
|
|
|
|
|
|
|
#define QXL_FREE_BUNCH_SIZE 32
|
|
|
|
|
|
|
|
if (ring->prod - ring->cons + 1 == ring->num_items) {
|
|
|
|
/* ring full -- can't push */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (!flush && d->oom_running) {
|
|
|
|
/* collect everything from oom handler before pushing */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
|
|
|
|
/* collect a bit more before pushing */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
SPICE_RING_PUSH(ring, notify);
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
|
|
|
|
d->guest_surfaces.count, d->num_free_res,
|
|
|
|
d->last_release, notify ? "yes" : "no");
|
|
|
|
trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
|
|
|
|
ring->num_items, ring->prod, ring->cons);
|
2010-04-27 13:50:11 +04:00
|
|
|
if (notify) {
|
|
|
|
qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
|
|
|
|
}
|
2012-04-25 13:13:21 +04:00
|
|
|
SPICE_RING_PROD_ITEM(d, ring, item);
|
|
|
|
if (!item) {
|
|
|
|
return;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
*item = 0;
|
|
|
|
d->num_free_res = 0;
|
|
|
|
d->last_release = NULL;
|
|
|
|
qxl_ring_set_dirty(d);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called from spice server thread context only */
|
|
|
|
static void interface_release_resource(QXLInstance *sin,
|
2015-04-08 21:04:14 +03:00
|
|
|
QXLReleaseInfoExt ext)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
QXLReleaseRing *ring;
|
|
|
|
uint64_t *item, id;
|
|
|
|
|
|
|
|
if (ext.group_id == MEMSLOT_GROUP_HOST) {
|
|
|
|
/* host group -> vga mode update request */
|
2014-06-20 10:12:44 +04:00
|
|
|
QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
|
2014-06-07 15:03:10 +04:00
|
|
|
SimpleSpiceUpdate *update;
|
|
|
|
g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
|
|
|
|
update = container_of(cmdext, SimpleSpiceUpdate, ext);
|
|
|
|
qemu_spice_destroy_update(&qxl->ssd, update);
|
2010-04-27 13:50:11 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ext->info points into guest-visible memory
|
|
|
|
* pci bar 0, $command.release_info
|
|
|
|
*/
|
|
|
|
ring = &qxl->ram->release_ring;
|
2012-04-25 13:13:21 +04:00
|
|
|
SPICE_RING_PROD_ITEM(qxl, ring, item);
|
|
|
|
if (!item) {
|
|
|
|
return;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
if (*item == 0) {
|
|
|
|
/* stick head into the ring */
|
|
|
|
id = ext.info->id;
|
|
|
|
ext.info->next = 0;
|
|
|
|
qxl_ram_set_dirty(qxl, &ext.info->next);
|
|
|
|
*item = id;
|
|
|
|
qxl_ring_set_dirty(qxl);
|
|
|
|
} else {
|
|
|
|
/* append item to the list */
|
|
|
|
qxl->last_release->next = ext.info->id;
|
|
|
|
qxl_ram_set_dirty(qxl, &qxl->last_release->next);
|
|
|
|
ext.info->next = 0;
|
|
|
|
qxl_ram_set_dirty(qxl, &ext.info->next);
|
|
|
|
}
|
|
|
|
qxl->last_release = ext.info;
|
|
|
|
qxl->num_free_res++;
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_push_free_res(qxl, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called from spice server thread context only */
|
|
|
|
static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
QXLCursorRing *ring;
|
|
|
|
QXLCommand *cmd;
|
|
|
|
int notify;
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
switch (qxl->mode) {
|
|
|
|
case QXL_MODE_COMPAT:
|
|
|
|
case QXL_MODE_NATIVE:
|
|
|
|
case QXL_MODE_UNDEFINED:
|
|
|
|
ring = &qxl->ram->cursor_ring;
|
|
|
|
if (SPICE_RING_IS_EMPTY(ring)) {
|
|
|
|
return false;
|
|
|
|
}
|
2012-04-25 13:13:21 +04:00
|
|
|
SPICE_RING_CONS_ITEM(qxl, ring, cmd);
|
|
|
|
if (!cmd) {
|
|
|
|
return false;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
ext->cmd = *cmd;
|
|
|
|
ext->group_id = MEMSLOT_GROUP_GUEST;
|
|
|
|
ext->flags = qxl->cmdflags;
|
|
|
|
SPICE_RING_POP(ring, notify);
|
|
|
|
qxl_ring_set_dirty(qxl);
|
|
|
|
if (notify) {
|
|
|
|
qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
|
|
|
|
}
|
|
|
|
qxl->guest_primary.commands++;
|
|
|
|
qxl_track_command(qxl, ext);
|
|
|
|
qxl_log_command(qxl, "csr", ext);
|
|
|
|
if (qxl->id == 0) {
|
|
|
|
qxl_render_cursor(qxl, ext);
|
|
|
|
}
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
|
2010-04-27 13:50:11 +04:00
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called from spice server thread context only */
|
|
|
|
static int interface_req_cursor_notification(QXLInstance *sin)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
int wait = 1;
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_ring_cursor_req_notification(qxl->id);
|
2010-04-27 13:50:11 +04:00
|
|
|
switch (qxl->mode) {
|
|
|
|
case QXL_MODE_COMPAT:
|
|
|
|
case QXL_MODE_NATIVE:
|
|
|
|
case QXL_MODE_UNDEFINED:
|
|
|
|
SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
|
|
|
|
qxl_ring_set_dirty(qxl);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return wait;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called from spice server thread context */
|
|
|
|
static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
|
|
|
|
{
|
2012-04-25 13:13:23 +04:00
|
|
|
/*
|
|
|
|
* Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
|
|
|
|
* use by xf86-video-qxl and is defined out in the qxl windows driver.
|
|
|
|
* Probably was at some earlier version that is prior to git start (2009),
|
|
|
|
* and is still guest trigerrable.
|
|
|
|
*/
|
|
|
|
fprintf(stderr, "%s: deprecated\n", __func__);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* called from spice server thread context only */
|
|
|
|
static int interface_flush_resources(QXLInstance *sin)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = qxl->num_free_res;
|
|
|
|
if (ret) {
|
|
|
|
qxl_push_free_res(qxl, 1);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-07-20 13:20:58 +04:00
|
|
|
static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
|
|
|
|
|
|
|
|
/* called from spice server thread context only */
|
2012-02-25 01:19:30 +04:00
|
|
|
static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
|
2011-07-20 13:20:58 +04:00
|
|
|
{
|
|
|
|
uint32_t current_async;
|
|
|
|
|
|
|
|
qemu_mutex_lock(&qxl->async_lock);
|
|
|
|
current_async = qxl->current_async;
|
|
|
|
qxl->current_async = QXL_UNDEFINED_IO;
|
|
|
|
qemu_mutex_unlock(&qxl->async_lock);
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
|
2012-02-25 01:19:30 +04:00
|
|
|
if (!cookie) {
|
|
|
|
fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (cookie && current_async != cookie->io) {
|
|
|
|
fprintf(stderr,
|
2012-04-25 13:13:20 +04:00
|
|
|
"qxl: %s: error: current_async = %d != %"
|
|
|
|
PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
|
2012-02-25 01:19:30 +04:00
|
|
|
}
|
2011-07-20 13:20:58 +04:00
|
|
|
switch (current_async) {
|
2012-02-25 01:19:31 +04:00
|
|
|
case QXL_IO_MEMSLOT_ADD_ASYNC:
|
|
|
|
case QXL_IO_DESTROY_PRIMARY_ASYNC:
|
|
|
|
case QXL_IO_UPDATE_AREA_ASYNC:
|
|
|
|
case QXL_IO_FLUSH_SURFACES_ASYNC:
|
2012-08-22 12:16:25 +04:00
|
|
|
case QXL_IO_MONITORS_CONFIG_ASYNC:
|
2012-02-25 01:19:31 +04:00
|
|
|
break;
|
2011-07-20 13:20:58 +04:00
|
|
|
case QXL_IO_CREATE_PRIMARY_ASYNC:
|
|
|
|
qxl_create_guest_primary_complete(qxl);
|
|
|
|
break;
|
|
|
|
case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
|
|
|
|
qxl_spice_destroy_surfaces_complete(qxl);
|
|
|
|
break;
|
|
|
|
case QXL_IO_DESTROY_SURFACE_ASYNC:
|
2012-02-25 01:19:30 +04:00
|
|
|
qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
|
2011-07-20 13:20:58 +04:00
|
|
|
break;
|
2012-02-25 01:19:31 +04:00
|
|
|
default:
|
|
|
|
fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
|
|
|
|
current_async);
|
2011-07-20 13:20:58 +04:00
|
|
|
}
|
|
|
|
qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
|
|
|
|
}
|
|
|
|
|
2012-02-25 01:19:31 +04:00
|
|
|
/* called from spice server thread context only */
|
|
|
|
static void interface_update_area_complete(QXLInstance *sin,
|
|
|
|
uint32_t surface_id,
|
|
|
|
QXLRect *dirty, uint32_t num_updated_rects)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
int i;
|
|
|
|
int qxl_i;
|
|
|
|
|
|
|
|
qemu_mutex_lock(&qxl->ssd.lock);
|
2016-06-08 17:11:41 +03:00
|
|
|
if (surface_id != 0 || !num_updated_rects ||
|
|
|
|
!qxl->render_update_cookie_num) {
|
2012-02-25 01:19:31 +04:00
|
|
|
qemu_mutex_unlock(&qxl->ssd.lock);
|
|
|
|
return;
|
|
|
|
}
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
|
|
|
|
dirty->right, dirty->top, dirty->bottom);
|
|
|
|
trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
|
2012-02-25 01:19:31 +04:00
|
|
|
if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
|
|
|
|
/*
|
|
|
|
* overflow - treat this as a full update. Not expected to be common.
|
|
|
|
*/
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_interface_update_area_complete_overflow(qxl->id,
|
|
|
|
QXL_NUM_DIRTY_RECTS);
|
2012-02-25 01:19:31 +04:00
|
|
|
qxl->guest_primary.resized = 1;
|
|
|
|
}
|
|
|
|
if (qxl->guest_primary.resized) {
|
|
|
|
/*
|
|
|
|
* Don't bother copying or scheduling the bh since we will flip
|
|
|
|
* the whole area anyway on completion of the update_area async call
|
|
|
|
*/
|
|
|
|
qemu_mutex_unlock(&qxl->ssd.lock);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
qxl_i = qxl->num_dirty_rects;
|
|
|
|
for (i = 0; i < num_updated_rects; i++) {
|
|
|
|
qxl->dirty[qxl_i++] = dirty[i];
|
|
|
|
}
|
|
|
|
qxl->num_dirty_rects += num_updated_rects;
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
|
|
|
|
qxl->num_dirty_rects);
|
2012-02-25 01:19:31 +04:00
|
|
|
qemu_bh_schedule(qxl->update_area_bh);
|
|
|
|
qemu_mutex_unlock(&qxl->ssd.lock);
|
|
|
|
}
|
|
|
|
|
2012-02-25 01:19:30 +04:00
|
|
|
/* called from spice server thread context only */
|
|
|
|
static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
2012-03-16 17:50:04 +04:00
|
|
|
QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
|
2012-02-25 01:19:30 +04:00
|
|
|
|
|
|
|
switch (cookie->type) {
|
|
|
|
case QXL_COOKIE_TYPE_IO:
|
|
|
|
interface_async_complete_io(qxl, cookie);
|
2012-02-25 01:19:31 +04:00
|
|
|
g_free(cookie);
|
|
|
|
break;
|
|
|
|
case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
|
|
|
|
qxl_render_update_area_done(qxl, cookie);
|
2012-02-25 01:19:30 +04:00
|
|
|
break;
|
2012-08-22 12:16:25 +04:00
|
|
|
case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
|
|
|
|
break;
|
2012-02-25 01:19:30 +04:00
|
|
|
default:
|
|
|
|
fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
|
|
|
|
__func__, cookie->type);
|
2012-02-25 01:19:31 +04:00
|
|
|
g_free(cookie);
|
2012-02-25 01:19:30 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-09-04 18:14:48 +04:00
|
|
|
/* called from spice server thread context only */
|
|
|
|
static void interface_set_client_capabilities(QXLInstance *sin,
|
|
|
|
uint8_t client_present,
|
|
|
|
uint8_t caps[58])
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
|
2013-01-21 16:48:06 +04:00
|
|
|
if (qxl->revision < 4) {
|
|
|
|
trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
|
|
|
|
qxl->revision);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-09-07 23:48:22 +04:00
|
|
|
if (runstate_check(RUN_STATE_INMIGRATE) ||
|
|
|
|
runstate_check(RUN_STATE_POSTMIGRATE)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-09-04 18:14:48 +04:00
|
|
|
qxl->shadow_rom.client_present = client_present;
|
2013-01-10 17:24:50 +04:00
|
|
|
memcpy(qxl->shadow_rom.client_capabilities, caps,
|
|
|
|
sizeof(qxl->shadow_rom.client_capabilities));
|
2012-09-04 18:14:48 +04:00
|
|
|
qxl->rom->client_present = client_present;
|
2013-01-10 17:24:50 +04:00
|
|
|
memcpy(qxl->rom->client_capabilities, caps,
|
|
|
|
sizeof(qxl->rom->client_capabilities));
|
2012-09-04 18:14:48 +04:00
|
|
|
qxl_rom_set_dirty(qxl);
|
|
|
|
|
|
|
|
qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
|
|
|
|
}
|
|
|
|
|
2012-09-12 17:13:28 +04:00
|
|
|
static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* zlib xors the seed with 0xffffffff, and xors the result
|
|
|
|
* again with 0xffffffff; Both are not done with linux's crc32,
|
|
|
|
* which we want to be compatible with, so undo that.
|
|
|
|
*/
|
|
|
|
return crc32(0xffffffff, p, len) ^ 0xffffffff;
|
|
|
|
}
|
|
|
|
|
2016-10-28 17:48:40 +03:00
|
|
|
static bool qxl_rom_monitors_config_changed(QXLRom *rom,
|
|
|
|
VDAgentMonitorsConfig *monitors_config,
|
|
|
|
unsigned int max_outputs)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
unsigned int monitors_count;
|
|
|
|
|
|
|
|
monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
|
|
|
|
|
|
|
|
if (rom->client_monitors_config.count != monitors_count) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
|
|
|
|
VDAgentMonConfig *monitor = &monitors_config->monitors[i];
|
|
|
|
QXLURect *rect = &rom->client_monitors_config.heads[i];
|
|
|
|
/* monitor->depth ignored */
|
|
|
|
if ((rect->left != monitor->x) ||
|
|
|
|
(rect->top != monitor->y) ||
|
|
|
|
(rect->right != monitor->x + monitor->width) ||
|
|
|
|
(rect->bottom != monitor->y + monitor->height)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-09-12 17:13:28 +04:00
|
|
|
/* called from main context only */
|
|
|
|
static int interface_client_monitors_config(QXLInstance *sin,
|
|
|
|
VDAgentMonitorsConfig *monitors_config)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
|
|
|
|
QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
|
|
|
|
int i;
|
2015-07-06 09:56:38 +03:00
|
|
|
unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
|
2016-10-28 17:48:40 +03:00
|
|
|
bool config_changed = false;
|
2012-09-12 17:13:28 +04:00
|
|
|
|
2013-01-21 16:48:06 +04:00
|
|
|
if (qxl->revision < 4) {
|
|
|
|
trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
|
|
|
|
qxl->revision);
|
|
|
|
return 0;
|
|
|
|
}
|
2012-09-12 17:13:28 +04:00
|
|
|
/*
|
|
|
|
* Older windows drivers set int_mask to 0 when their ISR is called,
|
|
|
|
* then later set it to ~0. So it doesn't relate to the actual interrupts
|
|
|
|
* handled. However, they are old, so clearly they don't support this
|
|
|
|
* interrupt
|
|
|
|
*/
|
|
|
|
if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
|
|
|
|
!(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
|
|
|
|
trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
|
|
|
|
qxl->ram->int_mask,
|
|
|
|
monitors_config);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if (!monitors_config) {
|
|
|
|
return 1;
|
|
|
|
}
|
2015-07-06 09:56:38 +03:00
|
|
|
|
|
|
|
#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
|
|
|
|
/* limit number of outputs based on setting limit */
|
|
|
|
if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
|
|
|
|
max_outputs = qxl->max_outputs;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-10-28 17:48:40 +03:00
|
|
|
config_changed = qxl_rom_monitors_config_changed(rom,
|
|
|
|
monitors_config,
|
|
|
|
max_outputs);
|
|
|
|
|
2012-09-12 17:13:28 +04:00
|
|
|
memset(&rom->client_monitors_config, 0,
|
|
|
|
sizeof(rom->client_monitors_config));
|
|
|
|
rom->client_monitors_config.count = monitors_config->num_of_monitors;
|
|
|
|
/* monitors_config->flags ignored */
|
2015-07-06 09:56:38 +03:00
|
|
|
if (rom->client_monitors_config.count >= max_outputs) {
|
2012-09-12 17:13:28 +04:00
|
|
|
trace_qxl_client_monitors_config_capped(qxl->id,
|
|
|
|
monitors_config->num_of_monitors,
|
2015-07-06 09:56:38 +03:00
|
|
|
max_outputs);
|
|
|
|
rom->client_monitors_config.count = max_outputs;
|
2012-09-12 17:13:28 +04:00
|
|
|
}
|
|
|
|
for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
|
|
|
|
VDAgentMonConfig *monitor = &monitors_config->monitors[i];
|
|
|
|
QXLURect *rect = &rom->client_monitors_config.heads[i];
|
|
|
|
/* monitor->depth ignored */
|
|
|
|
rect->left = monitor->x;
|
|
|
|
rect->top = monitor->y;
|
|
|
|
rect->right = monitor->x + monitor->width;
|
|
|
|
rect->bottom = monitor->y + monitor->height;
|
|
|
|
}
|
|
|
|
rom->client_monitors_config_crc = qxl_crc32(
|
|
|
|
(const uint8_t *)&rom->client_monitors_config,
|
|
|
|
sizeof(rom->client_monitors_config));
|
|
|
|
trace_qxl_client_monitors_config_crc(qxl->id,
|
|
|
|
sizeof(rom->client_monitors_config),
|
|
|
|
rom->client_monitors_config_crc);
|
|
|
|
|
|
|
|
trace_qxl_interrupt_client_monitors_config(qxl->id,
|
|
|
|
rom->client_monitors_config.count,
|
|
|
|
rom->client_monitors_config.heads);
|
2016-10-28 17:48:40 +03:00
|
|
|
if (config_changed) {
|
|
|
|
qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
|
|
|
|
}
|
2012-09-12 17:13:28 +04:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
static const QXLInterface qxl_interface = {
|
|
|
|
.base.type = SPICE_INTERFACE_QXL,
|
|
|
|
.base.description = "qxl gpu",
|
|
|
|
.base.major_version = SPICE_INTERFACE_QXL_MAJOR,
|
|
|
|
.base.minor_version = SPICE_INTERFACE_QXL_MINOR,
|
|
|
|
|
|
|
|
.attache_worker = interface_attach_worker,
|
|
|
|
.set_compression_level = interface_set_compression_level,
|
2016-06-30 01:41:35 +03:00
|
|
|
#if SPICE_NEEDS_SET_MM_TIME
|
2010-04-27 13:50:11 +04:00
|
|
|
.set_mm_time = interface_set_mm_time,
|
2016-06-30 01:41:35 +03:00
|
|
|
#endif
|
2010-04-27 13:50:11 +04:00
|
|
|
.get_init_info = interface_get_init_info,
|
|
|
|
|
|
|
|
/* the callbacks below are called from spice server thread context */
|
|
|
|
.get_command = interface_get_command,
|
|
|
|
.req_cmd_notification = interface_req_cmd_notification,
|
|
|
|
.release_resource = interface_release_resource,
|
|
|
|
.get_cursor_command = interface_get_cursor_command,
|
|
|
|
.req_cursor_notification = interface_req_cursor_notification,
|
|
|
|
.notify_update = interface_notify_update,
|
|
|
|
.flush_resources = interface_flush_resources,
|
2011-07-20 13:20:58 +04:00
|
|
|
.async_complete = interface_async_complete,
|
2012-02-25 01:19:31 +04:00
|
|
|
.update_area_complete = interface_update_area_complete,
|
2012-09-04 18:14:48 +04:00
|
|
|
.set_client_capabilities = interface_set_client_capabilities,
|
2012-09-12 17:13:28 +04:00
|
|
|
.client_monitors_config = interface_client_monitors_config,
|
2010-04-27 13:50:11 +04:00
|
|
|
};
|
|
|
|
|
2014-09-24 19:05:45 +04:00
|
|
|
static const GraphicHwOps qxl_ops = {
|
|
|
|
.gfx_update = qxl_hw_update,
|
|
|
|
};
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
static void qxl_enter_vga_mode(PCIQXLDevice *d)
|
|
|
|
{
|
|
|
|
if (d->mode == QXL_MODE_VGA) {
|
|
|
|
return;
|
|
|
|
}
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_enter_vga_mode(d->id);
|
2013-04-23 12:18:16 +04:00
|
|
|
#if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
|
|
|
|
spice_qxl_driver_unload(&d->ssd.qxl);
|
|
|
|
#endif
|
2014-09-24 19:05:45 +04:00
|
|
|
graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
|
2014-11-04 16:16:12 +03:00
|
|
|
update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
|
2010-04-27 13:50:11 +04:00
|
|
|
qemu_spice_create_host_primary(&d->ssd);
|
|
|
|
d->mode = QXL_MODE_VGA;
|
2012-05-24 20:18:53 +04:00
|
|
|
vga_dirty_log_start(&d->vga);
|
2013-03-12 16:44:38 +04:00
|
|
|
graphic_hw_update(d->vga.con);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_exit_vga_mode(PCIQXLDevice *d)
|
|
|
|
{
|
|
|
|
if (d->mode != QXL_MODE_VGA) {
|
|
|
|
return;
|
|
|
|
}
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_exit_vga_mode(d->id);
|
2014-09-24 19:05:45 +04:00
|
|
|
graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
|
2014-11-04 16:16:12 +03:00
|
|
|
update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
|
2012-05-24 20:18:53 +04:00
|
|
|
vga_dirty_log_stop(&d->vga);
|
2011-07-20 13:20:58 +04:00
|
|
|
qxl_destroy_primary(d, QXL_SYNC);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2011-09-05 09:45:59 +04:00
|
|
|
static void qxl_update_irq(PCIQXLDevice *d)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
uint32_t pending = le32_to_cpu(d->ram->int_pending);
|
|
|
|
uint32_t mask = le32_to_cpu(d->ram->int_mask);
|
|
|
|
int level = !!(pending & mask);
|
2013-10-07 11:36:39 +04:00
|
|
|
pci_set_irq(&d->pci, level);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_ring_set_dirty(d);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_check_state(PCIQXLDevice *d)
|
|
|
|
{
|
|
|
|
QXLRam *ram = d->ram;
|
2012-08-21 12:51:56 +04:00
|
|
|
int spice_display_running = qemu_spice_display_is_running(&d->ssd);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2012-08-21 12:51:56 +04:00
|
|
|
assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
|
|
|
|
assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_reset_state(PCIQXLDevice *d)
|
|
|
|
{
|
|
|
|
QXLRom *rom = d->rom;
|
|
|
|
|
2011-08-09 17:12:40 +04:00
|
|
|
qxl_check_state(d);
|
2010-04-27 13:50:11 +04:00
|
|
|
d->shadow_rom.update_id = cpu_to_le32(0);
|
|
|
|
*rom = d->shadow_rom;
|
|
|
|
qxl_rom_set_dirty(d);
|
|
|
|
init_qxl_ram(d);
|
|
|
|
d->num_free_res = 0;
|
|
|
|
d->last_release = NULL;
|
|
|
|
memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
|
2014-01-20 14:44:19 +04:00
|
|
|
qxl_update_irq(d);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_soft_reset(PCIQXLDevice *d)
|
|
|
|
{
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_soft_reset(d->id);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_check_state(d);
|
2012-05-24 20:18:54 +04:00
|
|
|
qxl_clear_guest_bug(d);
|
2015-10-20 10:57:30 +03:00
|
|
|
qemu_mutex_lock(&d->async_lock);
|
2012-06-11 10:24:01 +04:00
|
|
|
d->current_async = QXL_UNDEFINED_IO;
|
2015-10-20 10:57:30 +03:00
|
|
|
qemu_mutex_unlock(&d->async_lock);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
if (d->id == 0) {
|
|
|
|
qxl_enter_vga_mode(d);
|
|
|
|
} else {
|
|
|
|
d->mode = QXL_MODE_UNDEFINED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
|
|
|
|
{
|
2013-12-09 19:03:49 +04:00
|
|
|
bool startstop = qemu_spice_display_is_running(&d->ssd);
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_hard_reset(d->id, loadvm);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2013-12-09 19:03:49 +04:00
|
|
|
if (startstop) {
|
|
|
|
qemu_spice_display_stop();
|
|
|
|
}
|
|
|
|
|
2011-07-20 13:20:52 +04:00
|
|
|
qxl_spice_reset_cursor(d);
|
|
|
|
qxl_spice_reset_image_cache(d);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_reset_surfaces(d);
|
|
|
|
qxl_reset_memslots(d);
|
|
|
|
|
|
|
|
/* pre loadvm reset must not touch QXLRam. This lives in
|
|
|
|
* device memory, is migrated together with RAM and thus
|
|
|
|
* already loaded at this point */
|
|
|
|
if (!loadvm) {
|
|
|
|
qxl_reset_state(d);
|
|
|
|
}
|
|
|
|
qemu_spice_create_host_memslot(&d->ssd);
|
|
|
|
qxl_soft_reset(d);
|
2013-12-09 19:03:49 +04:00
|
|
|
|
|
|
|
if (startstop) {
|
|
|
|
qemu_spice_display_start();
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_reset_handler(DeviceState *dev)
|
|
|
|
{
|
2015-05-12 12:27:10 +03:00
|
|
|
PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
|
2012-03-18 16:46:14 +04:00
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_hard_reset(d, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
VGACommonState *vga = opaque;
|
|
|
|
PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
|
2010-04-27 13:50:11 +04:00
|
|
|
if (qxl->mode != QXL_MODE_VGA) {
|
2011-07-20 13:20:58 +04:00
|
|
|
qxl_destroy_primary(qxl, QXL_SYNC);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_soft_reset(qxl);
|
|
|
|
}
|
|
|
|
vga_ioport_write(opaque, addr, val);
|
|
|
|
}
|
|
|
|
|
2011-11-03 21:21:54 +04:00
|
|
|
static const MemoryRegionPortio qxl_vga_portio_list[] = {
|
|
|
|
{ 0x04, 2, 1, .read = vga_ioport_read,
|
|
|
|
.write = qxl_vga_ioport_write }, /* 3b4 */
|
|
|
|
{ 0x0a, 1, 1, .read = vga_ioport_read,
|
|
|
|
.write = qxl_vga_ioport_write }, /* 3ba */
|
|
|
|
{ 0x10, 16, 1, .read = vga_ioport_read,
|
|
|
|
.write = qxl_vga_ioport_write }, /* 3c0 */
|
|
|
|
{ 0x24, 2, 1, .read = vga_ioport_read,
|
|
|
|
.write = qxl_vga_ioport_write }, /* 3d4 */
|
|
|
|
{ 0x2a, 1, 1, .read = vga_ioport_read,
|
|
|
|
.write = qxl_vga_ioport_write }, /* 3da */
|
|
|
|
PORTIO_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2012-04-25 13:13:24 +04:00
|
|
|
static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
|
|
|
|
qxl_async_io async)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
static const int regions[] = {
|
|
|
|
QXL_RAM_RANGE_INDEX,
|
|
|
|
QXL_VRAM_RANGE_INDEX,
|
2011-10-14 20:05:48 +04:00
|
|
|
QXL_VRAM64_RANGE_INDEX,
|
2010-04-27 13:50:11 +04:00
|
|
|
};
|
|
|
|
uint64_t guest_start;
|
|
|
|
uint64_t guest_end;
|
|
|
|
int pci_region;
|
|
|
|
pcibus_t pci_start;
|
|
|
|
pcibus_t pci_end;
|
2016-06-22 15:07:23 +03:00
|
|
|
MemoryRegion *mr;
|
2010-04-27 13:50:11 +04:00
|
|
|
intptr_t virt_start;
|
|
|
|
QXLDevMemSlot memslot;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
|
|
|
|
guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2012-04-25 13:13:24 +04:00
|
|
|
if (slot_id >= NUM_MEMSLOTS) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
|
2012-04-25 13:13:24 +04:00
|
|
|
slot_id, NUM_MEMSLOTS);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
if (guest_start > guest_end) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
|
2012-04-25 13:13:24 +04:00
|
|
|
" > 0x%" PRIx64, __func__, guest_start, guest_end);
|
|
|
|
return 1;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(regions); i++) {
|
|
|
|
pci_region = regions[i];
|
|
|
|
pci_start = d->pci.io_regions[pci_region].addr;
|
|
|
|
pci_end = pci_start + d->pci.io_regions[pci_region].size;
|
|
|
|
/* mapped? */
|
|
|
|
if (pci_start == -1) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
/* start address in range ? */
|
|
|
|
if (guest_start < pci_start || guest_start > pci_end) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
/* end address in range ? */
|
|
|
|
if (guest_end > pci_end) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
/* passed */
|
|
|
|
break;
|
|
|
|
}
|
2012-04-25 13:13:24 +04:00
|
|
|
if (i == ARRAY_SIZE(regions)) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
|
2012-04-25 13:13:24 +04:00
|
|
|
return 1;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
switch (pci_region) {
|
|
|
|
case QXL_RAM_RANGE_INDEX:
|
2016-06-22 15:07:23 +03:00
|
|
|
mr = &d->vga.vram;
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
case QXL_VRAM_RANGE_INDEX:
|
2011-10-14 20:05:48 +04:00
|
|
|
case 4 /* vram 64bit */:
|
2016-06-22 15:07:23 +03:00
|
|
|
mr = &d->vram_bar;
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* should not happen */
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
|
2012-04-25 13:13:24 +04:00
|
|
|
return 1;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2016-06-22 15:07:23 +03:00
|
|
|
virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
|
2010-04-27 13:50:11 +04:00
|
|
|
memslot.slot_id = slot_id;
|
|
|
|
memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
|
|
|
|
memslot.virt_start = virt_start + (guest_start - pci_start);
|
|
|
|
memslot.virt_end = virt_start + (guest_end - pci_start);
|
|
|
|
memslot.addr_delta = memslot.virt_start - delta;
|
|
|
|
memslot.generation = d->rom->slot_generation = 0;
|
|
|
|
qxl_rom_set_dirty(d);
|
|
|
|
|
2011-07-20 13:20:58 +04:00
|
|
|
qemu_spice_add_memslot(&d->ssd, &memslot, async);
|
2016-06-22 15:07:23 +03:00
|
|
|
d->guest_slots[slot_id].mr = mr;
|
|
|
|
d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
|
2010-04-27 13:50:11 +04:00
|
|
|
d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
|
|
|
|
d->guest_slots[slot_id].delta = delta;
|
|
|
|
d->guest_slots[slot_id].active = 1;
|
2012-04-25 13:13:24 +04:00
|
|
|
return 0;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
|
|
|
|
{
|
2011-07-20 13:20:50 +04:00
|
|
|
qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
|
2010-04-27 13:50:11 +04:00
|
|
|
d->guest_slots[slot_id].active = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_reset_memslots(PCIQXLDevice *d)
|
|
|
|
{
|
2011-07-20 13:20:52 +04:00
|
|
|
qxl_spice_reset_memslots(d);
|
2010-04-27 13:50:11 +04:00
|
|
|
memset(&d->guest_slots, 0, sizeof(d->guest_slots));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_reset_surfaces(PCIQXLDevice *d)
|
|
|
|
{
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_reset_surfaces(d->id);
|
2010-04-27 13:50:11 +04:00
|
|
|
d->mode = QXL_MODE_UNDEFINED;
|
2011-07-20 13:20:58 +04:00
|
|
|
qxl_spice_destroy_surfaces(d, QXL_SYNC);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2012-02-15 13:22:15 +04:00
|
|
|
/* can be also called from spice server thread context */
|
2016-06-22 15:07:22 +03:00
|
|
|
static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
|
|
|
|
uint32_t *s, uint64_t *o)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
uint64_t phys = le64_to_cpu(pqxl);
|
|
|
|
uint32_t slot = (phys >> (64 - 8)) & 0xff;
|
|
|
|
uint64_t offset = phys & 0xffffffffffff;
|
|
|
|
|
2016-06-22 15:07:22 +03:00
|
|
|
if (slot >= NUM_MEMSLOTS) {
|
|
|
|
qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
|
|
|
|
NUM_MEMSLOTS);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (!qxl->guest_slots[slot].active) {
|
|
|
|
qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (offset < qxl->guest_slots[slot].delta) {
|
|
|
|
qxl_set_guest_bug(qxl,
|
2012-05-24 13:38:12 +04:00
|
|
|
"slot %d offset %"PRIu64" < delta %"PRIu64"\n",
|
2012-04-25 13:13:17 +04:00
|
|
|
slot, offset, qxl->guest_slots[slot].delta);
|
2016-06-22 15:07:22 +03:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
offset -= qxl->guest_slots[slot].delta;
|
|
|
|
if (offset > qxl->guest_slots[slot].size) {
|
|
|
|
qxl_set_guest_bug(qxl,
|
2012-05-24 13:38:12 +04:00
|
|
|
"slot %d offset %"PRIu64" > size %"PRIu64"\n",
|
2012-04-25 13:13:17 +04:00
|
|
|
slot, offset, qxl->guest_slots[slot].size);
|
2016-06-22 15:07:22 +03:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
*s = slot;
|
|
|
|
*o = offset;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* can be also called from spice server thread context */
|
|
|
|
void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
|
|
|
|
{
|
|
|
|
uint64_t offset;
|
|
|
|
uint32_t slot;
|
2016-06-22 15:07:23 +03:00
|
|
|
void *ptr;
|
2016-06-22 15:07:22 +03:00
|
|
|
|
|
|
|
switch (group_id) {
|
|
|
|
case MEMSLOT_GROUP_HOST:
|
|
|
|
offset = le64_to_cpu(pqxl) & 0xffffffffffff;
|
|
|
|
return (void *)(intptr_t)offset;
|
|
|
|
case MEMSLOT_GROUP_GUEST:
|
|
|
|
if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
|
2012-04-25 13:13:17 +04:00
|
|
|
return NULL;
|
|
|
|
}
|
2016-06-22 15:07:23 +03:00
|
|
|
ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
|
|
|
|
ptr += qxl->guest_slots[slot].offset;
|
|
|
|
ptr += offset;
|
|
|
|
return ptr;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
2012-04-25 13:13:17 +04:00
|
|
|
return NULL;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2011-07-20 13:20:58 +04:00
|
|
|
static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
|
|
|
|
{
|
|
|
|
/* for local rendering */
|
|
|
|
qxl_render_resize(qxl);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
|
|
|
|
qxl_async_io async)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
QXLDevSurfaceCreate surface;
|
|
|
|
QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
|
2014-01-20 20:57:12 +04:00
|
|
|
uint32_t requested_height = le32_to_cpu(sc->height);
|
2012-06-10 19:05:06 +04:00
|
|
|
int requested_stride = le32_to_cpu(sc->stride);
|
|
|
|
|
2014-01-20 20:57:12 +04:00
|
|
|
if (requested_stride == INT32_MIN ||
|
|
|
|
abs(requested_stride) * (uint64_t)requested_height
|
|
|
|
> qxl->vgamem_size) {
|
|
|
|
qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
|
|
|
|
" stride %d x height %" PRIu32 " > %" PRIu32,
|
|
|
|
__func__, requested_stride, requested_height,
|
|
|
|
qxl->vgamem_size);
|
2012-06-10 19:05:06 +04:00
|
|
|
return;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2012-04-25 13:43:31 +04:00
|
|
|
if (qxl->mode == QXL_MODE_NATIVE) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
|
2012-04-25 13:43:31 +04:00
|
|
|
__func__);
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_exit_vga_mode(qxl);
|
|
|
|
|
|
|
|
surface.format = le32_to_cpu(sc->format);
|
|
|
|
surface.height = le32_to_cpu(sc->height);
|
|
|
|
surface.mem = le64_to_cpu(sc->mem);
|
|
|
|
surface.position = le32_to_cpu(sc->position);
|
|
|
|
surface.stride = le32_to_cpu(sc->stride);
|
|
|
|
surface.width = le32_to_cpu(sc->width);
|
|
|
|
surface.type = le32_to_cpu(sc->type);
|
|
|
|
surface.flags = le32_to_cpu(sc->flags);
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
|
|
|
|
sc->format, sc->position);
|
|
|
|
trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
|
|
|
|
sc->flags);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2012-10-15 16:54:03 +04:00
|
|
|
if ((surface.stride & 0x3) != 0) {
|
|
|
|
qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
|
|
|
|
surface.stride);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
surface.mouse_mode = true;
|
|
|
|
surface.group_id = MEMSLOT_GROUP_GUEST;
|
|
|
|
if (loadvm) {
|
|
|
|
surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
|
|
|
|
}
|
|
|
|
|
|
|
|
qxl->mode = QXL_MODE_NATIVE;
|
|
|
|
qxl->cmdflags = 0;
|
2011-07-20 13:20:58 +04:00
|
|
|
qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2011-07-20 13:20:58 +04:00
|
|
|
if (async == QXL_SYNC) {
|
|
|
|
qxl_create_guest_primary_complete(qxl);
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2011-07-20 13:20:58 +04:00
|
|
|
/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
|
|
|
|
* done (in QXL_SYNC case), 0 otherwise. */
|
|
|
|
static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
if (d->mode == QXL_MODE_UNDEFINED) {
|
2011-07-20 13:20:58 +04:00
|
|
|
return 0;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_destroy_primary(d->id);
|
2010-04-27 13:50:11 +04:00
|
|
|
d->mode = QXL_MODE_UNDEFINED;
|
2011-07-20 13:20:58 +04:00
|
|
|
qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
|
2011-10-18 20:58:54 +04:00
|
|
|
qxl_spice_reset_cursor(d);
|
2011-07-20 13:20:58 +04:00
|
|
|
return 1;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2014-02-19 14:40:17 +04:00
|
|
|
static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
|
|
|
|
pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
|
|
|
|
QXLMode *mode = d->modes->modes + modenr;
|
|
|
|
uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
|
|
|
|
QXLMemSlot slot = {
|
|
|
|
.mem_start = start,
|
|
|
|
.mem_end = end
|
|
|
|
};
|
2014-02-19 14:40:17 +04:00
|
|
|
|
|
|
|
if (modenr >= d->modes->n_modes) {
|
|
|
|
qxl_set_guest_bug(d, "mode number out of range");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
QXLSurfaceCreate surface = {
|
|
|
|
.width = mode->x_res,
|
|
|
|
.height = mode->y_res,
|
|
|
|
.stride = -mode->x_res * 4,
|
|
|
|
.format = SPICE_SURFACE_FMT_32_xRGB,
|
|
|
|
.flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
|
|
|
|
.mouse_mode = true,
|
|
|
|
.mem = devmem + d->shadow_rom.draw_area_offset,
|
|
|
|
};
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
|
|
|
|
devmem);
|
2010-04-27 13:50:11 +04:00
|
|
|
if (!loadvm) {
|
|
|
|
qxl_hard_reset(d, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
d->guest_slots[0].slot = slot;
|
2012-04-25 13:13:24 +04:00
|
|
|
assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
d->guest_primary.surface = surface;
|
2011-07-20 13:20:58 +04:00
|
|
|
qxl_create_guest_primary(d, 0, QXL_SYNC);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
d->mode = QXL_MODE_COMPAT;
|
|
|
|
d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
|
|
|
|
if (mode->bits == 16) {
|
|
|
|
d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
|
|
|
|
}
|
|
|
|
d->shadow_rom.mode = cpu_to_le32(modenr);
|
|
|
|
d->rom->mode = cpu_to_le32(modenr);
|
|
|
|
qxl_rom_set_dirty(d);
|
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static void ioport_write(void *opaque, hwaddr addr,
|
2011-08-08 17:08:57 +04:00
|
|
|
uint64_t val, unsigned size)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
PCIQXLDevice *d = opaque;
|
2011-08-08 17:08:57 +04:00
|
|
|
uint32_t io_port = addr;
|
2011-07-20 13:20:58 +04:00
|
|
|
qxl_async_io async = QXL_SYNC;
|
|
|
|
uint32_t orig_io_port = io_port;
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2012-10-02 13:39:14 +04:00
|
|
|
if (d->guest_bug && io_port != QXL_IO_RESET) {
|
2012-05-24 20:18:54 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-08-22 12:16:25 +04:00
|
|
|
if (d->revision <= QXL_REVISION_STABLE_V10 &&
|
2012-09-25 15:56:40 +04:00
|
|
|
io_port > QXL_IO_FLUSH_RELEASE) {
|
2012-08-22 12:16:25 +04:00
|
|
|
qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
|
|
|
|
io_port, d->revision);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
switch (io_port) {
|
|
|
|
case QXL_IO_RESET:
|
|
|
|
case QXL_IO_SET_MODE:
|
|
|
|
case QXL_IO_MEMSLOT_ADD:
|
|
|
|
case QXL_IO_MEMSLOT_DEL:
|
|
|
|
case QXL_IO_CREATE_PRIMARY:
|
2011-06-24 14:23:44 +04:00
|
|
|
case QXL_IO_UPDATE_IRQ:
|
2011-06-29 15:57:11 +04:00
|
|
|
case QXL_IO_LOG:
|
2011-07-20 13:20:58 +04:00
|
|
|
case QXL_IO_MEMSLOT_ADD_ASYNC:
|
|
|
|
case QXL_IO_CREATE_PRIMARY_ASYNC:
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
default:
|
2011-07-20 13:20:57 +04:00
|
|
|
if (d->mode != QXL_MODE_VGA) {
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
2011-07-20 13:20:57 +04:00
|
|
|
}
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_io_unexpected_vga_mode(d->id,
|
2012-09-12 17:13:26 +04:00
|
|
|
addr, val, io_port_to_string(io_port));
|
2011-07-20 13:20:58 +04:00
|
|
|
/* be nice to buggy guest drivers */
|
|
|
|
if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
|
2012-08-22 12:16:25 +04:00
|
|
|
io_port < QXL_IO_RANGE_SIZE) {
|
2011-07-20 13:20:58 +04:00
|
|
|
qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-07-20 13:20:58 +04:00
|
|
|
/* we change the io_port to avoid ifdeffery in the main switch */
|
|
|
|
orig_io_port = io_port;
|
|
|
|
switch (io_port) {
|
|
|
|
case QXL_IO_UPDATE_AREA_ASYNC:
|
|
|
|
io_port = QXL_IO_UPDATE_AREA;
|
|
|
|
goto async_common;
|
|
|
|
case QXL_IO_MEMSLOT_ADD_ASYNC:
|
|
|
|
io_port = QXL_IO_MEMSLOT_ADD;
|
|
|
|
goto async_common;
|
|
|
|
case QXL_IO_CREATE_PRIMARY_ASYNC:
|
|
|
|
io_port = QXL_IO_CREATE_PRIMARY;
|
|
|
|
goto async_common;
|
|
|
|
case QXL_IO_DESTROY_PRIMARY_ASYNC:
|
|
|
|
io_port = QXL_IO_DESTROY_PRIMARY;
|
|
|
|
goto async_common;
|
|
|
|
case QXL_IO_DESTROY_SURFACE_ASYNC:
|
|
|
|
io_port = QXL_IO_DESTROY_SURFACE_WAIT;
|
|
|
|
goto async_common;
|
|
|
|
case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
|
|
|
|
io_port = QXL_IO_DESTROY_ALL_SURFACES;
|
2011-07-20 13:20:59 +04:00
|
|
|
goto async_common;
|
|
|
|
case QXL_IO_FLUSH_SURFACES_ASYNC:
|
2012-08-22 12:16:25 +04:00
|
|
|
case QXL_IO_MONITORS_CONFIG_ASYNC:
|
2011-07-20 13:20:58 +04:00
|
|
|
async_common:
|
|
|
|
async = QXL_ASYNC;
|
|
|
|
qemu_mutex_lock(&d->async_lock);
|
|
|
|
if (d->current_async != QXL_UNDEFINED_IO) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "%d async started before last (%d) complete",
|
2011-07-20 13:20:58 +04:00
|
|
|
io_port, d->current_async);
|
|
|
|
qemu_mutex_unlock(&d->async_lock);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
d->current_async = orig_io_port;
|
|
|
|
qemu_mutex_unlock(&d->async_lock);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2013-09-05 19:30:05 +04:00
|
|
|
trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
|
|
|
|
addr, io_port_to_string(addr),
|
|
|
|
val, size, async);
|
2011-07-20 13:20:58 +04:00
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
switch (io_port) {
|
|
|
|
case QXL_IO_UPDATE_AREA:
|
|
|
|
{
|
2012-02-25 01:19:31 +04:00
|
|
|
QXLCookie *cookie = NULL;
|
2010-04-27 13:50:11 +04:00
|
|
|
QXLRect update = d->ram->update_area;
|
2012-02-25 01:19:31 +04:00
|
|
|
|
2012-09-04 13:39:41 +04:00
|
|
|
if (d->ram->update_surface > d->ssd.num_surfaces) {
|
2012-08-21 14:51:31 +04:00
|
|
|
qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
|
|
|
|
d->ram->update_surface);
|
2012-09-19 17:41:26 +04:00
|
|
|
break;
|
2012-08-21 14:51:31 +04:00
|
|
|
}
|
2012-09-19 17:41:26 +04:00
|
|
|
if (update.left >= update.right || update.top >= update.bottom ||
|
|
|
|
update.left < 0 || update.top < 0) {
|
2012-08-21 14:51:31 +04:00
|
|
|
qxl_set_guest_bug(d,
|
|
|
|
"QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
|
|
|
|
update.left, update.top, update.right, update.bottom);
|
2014-10-10 21:05:11 +04:00
|
|
|
if (update.left == update.right || update.top == update.bottom) {
|
|
|
|
/* old drivers may provide empty area, keep going */
|
|
|
|
qxl_clear_guest_bug(d);
|
|
|
|
goto cancel_async;
|
|
|
|
}
|
2012-08-30 20:44:44 +04:00
|
|
|
break;
|
|
|
|
}
|
2012-02-25 01:19:31 +04:00
|
|
|
if (async == QXL_ASYNC) {
|
|
|
|
cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
|
|
|
|
QXL_IO_UPDATE_AREA_ASYNC);
|
|
|
|
cookie->u.area = update;
|
|
|
|
}
|
2011-07-20 13:20:52 +04:00
|
|
|
qxl_spice_update_area(d, d->ram->update_surface,
|
2012-02-25 01:19:31 +04:00
|
|
|
cookie ? &cookie->u.area : &update,
|
|
|
|
NULL, 0, 0, async, cookie);
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case QXL_IO_NOTIFY_CMD:
|
2011-07-20 13:20:50 +04:00
|
|
|
qemu_spice_wakeup(&d->ssd);
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
case QXL_IO_NOTIFY_CURSOR:
|
2011-07-20 13:20:50 +04:00
|
|
|
qemu_spice_wakeup(&d->ssd);
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
case QXL_IO_UPDATE_IRQ:
|
2011-09-05 09:45:59 +04:00
|
|
|
qxl_update_irq(d);
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
case QXL_IO_NOTIFY_OOM:
|
|
|
|
if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
d->oom_running = 1;
|
2011-07-20 13:20:52 +04:00
|
|
|
qxl_spice_oom(d);
|
2010-04-27 13:50:11 +04:00
|
|
|
d->oom_running = 0;
|
|
|
|
break;
|
|
|
|
case QXL_IO_SET_MODE:
|
|
|
|
qxl_set_mode(d, val, 0);
|
|
|
|
break;
|
|
|
|
case QXL_IO_LOG:
|
2012-09-12 17:13:27 +04:00
|
|
|
trace_qxl_io_log(d->id, d->ram->log_buf);
|
2010-04-27 13:50:11 +04:00
|
|
|
if (d->guestdebug) {
|
2011-09-03 17:48:25 +04:00
|
|
|
fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
|
2013-08-21 19:03:08 +04:00
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case QXL_IO_RESET:
|
|
|
|
qxl_hard_reset(d, 0);
|
|
|
|
break;
|
|
|
|
case QXL_IO_MEMSLOT_ADD:
|
2011-07-20 13:20:55 +04:00
|
|
|
if (val >= NUM_MEMSLOTS) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
|
2011-07-20 13:20:55 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (d->guest_slots[val].active) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d,
|
|
|
|
"QXL_IO_MEMSLOT_ADD: memory slot already active");
|
2011-07-20 13:20:55 +04:00
|
|
|
break;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
d->guest_slots[val].slot = d->ram->mem_slot;
|
2011-07-20 13:20:58 +04:00
|
|
|
qxl_add_memslot(d, val, 0, async);
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
case QXL_IO_MEMSLOT_DEL:
|
2011-07-20 13:20:55 +04:00
|
|
|
if (val >= NUM_MEMSLOTS) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
|
2011-07-20 13:20:55 +04:00
|
|
|
break;
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_del_memslot(d, val);
|
|
|
|
break;
|
|
|
|
case QXL_IO_CREATE_PRIMARY:
|
2011-07-20 13:20:55 +04:00
|
|
|
if (val != 0) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
|
2011-07-20 13:20:58 +04:00
|
|
|
async);
|
|
|
|
goto cancel_async;
|
2011-07-20 13:20:55 +04:00
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
d->guest_primary.surface = d->ram->create_surface;
|
2011-07-20 13:20:58 +04:00
|
|
|
qxl_create_guest_primary(d, 0, async);
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
case QXL_IO_DESTROY_PRIMARY:
|
2011-07-20 13:20:55 +04:00
|
|
|
if (val != 0) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
|
2011-07-20 13:20:58 +04:00
|
|
|
async);
|
|
|
|
goto cancel_async;
|
|
|
|
}
|
|
|
|
if (!qxl_destroy_primary(d, async)) {
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_io_destroy_primary_ignored(d->id,
|
|
|
|
qxl_mode_to_string(d->mode));
|
2011-07-20 13:20:58 +04:00
|
|
|
goto cancel_async;
|
2011-07-20 13:20:55 +04:00
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
case QXL_IO_DESTROY_SURFACE_WAIT:
|
2012-09-04 13:39:41 +04:00
|
|
|
if (val >= d->ssd.num_surfaces) {
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
|
2012-04-02 00:07:30 +04:00
|
|
|
"%" PRIu64 " >= NUM_SURFACES", async, val);
|
2011-07-20 13:20:58 +04:00
|
|
|
goto cancel_async;
|
|
|
|
}
|
|
|
|
qxl_spice_destroy_surface_wait(d, val, async);
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
2011-07-20 13:20:59 +04:00
|
|
|
case QXL_IO_FLUSH_RELEASE: {
|
|
|
|
QXLReleaseRing *ring = &d->ram->release_ring;
|
|
|
|
if (ring->prod - ring->cons + 1 == ring->num_items) {
|
|
|
|
fprintf(stderr,
|
|
|
|
"ERROR: no flush, full release ring [p%d,%dc]\n",
|
|
|
|
ring->prod, ring->cons);
|
|
|
|
}
|
|
|
|
qxl_push_free_res(d, 1 /* flush */);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case QXL_IO_FLUSH_SURFACES_ASYNC:
|
|
|
|
qxl_spice_flush_surfaces_async(d);
|
|
|
|
break;
|
2010-04-27 13:50:11 +04:00
|
|
|
case QXL_IO_DESTROY_ALL_SURFACES:
|
2011-07-20 13:20:58 +04:00
|
|
|
d->mode = QXL_MODE_UNDEFINED;
|
|
|
|
qxl_spice_destroy_surfaces(d, async);
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
2012-08-22 12:16:25 +04:00
|
|
|
case QXL_IO_MONITORS_CONFIG_ASYNC:
|
|
|
|
qxl_spice_monitors_config_async(d, 0);
|
|
|
|
break;
|
2010-04-27 13:50:11 +04:00
|
|
|
default:
|
2012-05-24 13:38:12 +04:00
|
|
|
qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
2011-07-20 13:20:58 +04:00
|
|
|
return;
|
|
|
|
cancel_async:
|
|
|
|
if (async) {
|
|
|
|
qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
|
|
|
|
qemu_mutex_lock(&d->async_lock);
|
|
|
|
d->current_async = QXL_UNDEFINED_IO;
|
|
|
|
qemu_mutex_unlock(&d->async_lock);
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint64_t ioport_read(void *opaque, hwaddr addr,
|
2011-08-08 17:08:57 +04:00
|
|
|
unsigned size)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
2012-09-12 17:13:26 +04:00
|
|
|
PCIQXLDevice *qxl = opaque;
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2012-09-12 17:13:26 +04:00
|
|
|
trace_qxl_io_read_unexpected(qxl->id);
|
2010-04-27 13:50:11 +04:00
|
|
|
return 0xff;
|
|
|
|
}
|
|
|
|
|
2011-08-08 17:08:57 +04:00
|
|
|
static const MemoryRegionOps qxl_io_ops = {
|
|
|
|
.read = ioport_read,
|
|
|
|
.write = ioport_write,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 1,
|
|
|
|
},
|
|
|
|
};
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2013-10-29 16:29:43 +04:00
|
|
|
static void qxl_update_irq_bh(void *opaque)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
PCIQXLDevice *d = opaque;
|
2011-09-05 09:45:59 +04:00
|
|
|
qxl_update_irq(d);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
|
|
|
|
{
|
|
|
|
uint32_t old_pending;
|
|
|
|
uint32_t le_events = cpu_to_le32(events);
|
|
|
|
|
2012-09-12 17:13:26 +04:00
|
|
|
trace_qxl_send_events(d->id, events);
|
2012-11-01 16:56:00 +04:00
|
|
|
if (!qemu_spice_display_is_running(&d->ssd)) {
|
|
|
|
/* spice-server tracks guest running state and should not do this */
|
|
|
|
fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
|
|
|
|
__func__);
|
|
|
|
trace_qxl_send_events_vm_stopped(d->id, events);
|
|
|
|
return;
|
|
|
|
}
|
2013-05-13 15:29:47 +04:00
|
|
|
old_pending = atomic_fetch_or(&d->ram->int_pending, le_events);
|
2010-04-27 13:50:11 +04:00
|
|
|
if ((old_pending & le_events) == le_events) {
|
|
|
|
return;
|
|
|
|
}
|
2013-10-29 16:29:43 +04:00
|
|
|
qemu_bh_schedule(d->update_irq);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* graphics console */
|
|
|
|
|
|
|
|
static void qxl_hw_update(void *opaque)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = opaque;
|
|
|
|
|
2014-09-24 19:05:45 +04:00
|
|
|
qxl_render_update(qxl);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2016-06-22 15:07:24 +03:00
|
|
|
static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
|
|
|
|
uint32_t height, int32_t stride)
|
|
|
|
{
|
2016-07-13 15:33:06 +03:00
|
|
|
uint64_t offset, size;
|
|
|
|
uint32_t slot;
|
2016-06-22 15:07:24 +03:00
|
|
|
bool rc;
|
|
|
|
|
|
|
|
rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
|
|
|
|
assert(rc == true);
|
2016-07-13 15:33:06 +03:00
|
|
|
size = (uint64_t)height * abs(stride);
|
|
|
|
trace_qxl_surfaces_dirty(qxl->id, offset, size);
|
2016-06-22 15:07:24 +03:00
|
|
|
qxl_set_dirty(qxl->guest_slots[slot].mr,
|
2016-07-13 15:33:06 +03:00
|
|
|
qxl->guest_slots[slot].offset + offset,
|
|
|
|
qxl->guest_slots[slot].offset + offset + size);
|
2016-06-22 15:07:24 +03:00
|
|
|
}
|
|
|
|
|
2012-02-15 13:22:15 +04:00
|
|
|
static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2012-02-15 13:22:16 +04:00
|
|
|
if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
|
2012-02-15 13:22:15 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* dirty the primary surface */
|
2016-06-22 15:07:24 +03:00
|
|
|
qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
|
|
|
|
qxl->guest_primary.surface.height,
|
|
|
|
qxl->guest_primary.surface.stride);
|
2012-02-15 13:22:15 +04:00
|
|
|
|
|
|
|
/* dirty the off-screen surfaces */
|
2012-09-04 13:39:41 +04:00
|
|
|
for (i = 0; i < qxl->ssd.num_surfaces; i++) {
|
2012-02-15 13:22:15 +04:00
|
|
|
QXLSurfaceCmd *cmd;
|
|
|
|
|
|
|
|
if (qxl->guest_surfaces.cmds[i] == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
|
|
|
|
MEMSLOT_GROUP_GUEST);
|
2012-04-25 13:13:18 +04:00
|
|
|
assert(cmd);
|
2012-02-15 13:22:15 +04:00
|
|
|
assert(cmd->type == QXL_SURFACE_CMD_CREATE);
|
2016-06-22 15:07:24 +03:00
|
|
|
qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
|
|
|
|
cmd->u.surface_create.height,
|
|
|
|
cmd->u.surface_create.stride);
|
2012-02-15 13:22:15 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-07-29 21:26:33 +04:00
|
|
|
static void qxl_vm_change_state_handler(void *opaque, int running,
|
|
|
|
RunState state)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = opaque;
|
|
|
|
|
2011-09-05 09:45:58 +04:00
|
|
|
if (running) {
|
|
|
|
/*
|
|
|
|
* if qxl_send_events was called from spice server context before
|
2011-09-05 09:45:59 +04:00
|
|
|
* migration ended, qxl_update_irq for these events might not have been
|
2011-09-05 09:45:58 +04:00
|
|
|
* called
|
|
|
|
*/
|
2011-09-05 09:45:59 +04:00
|
|
|
qxl_update_irq(qxl);
|
2012-02-15 13:22:15 +04:00
|
|
|
} else {
|
|
|
|
/* make sure surfaces are saved before migration */
|
|
|
|
qxl_dirty_surfaces(qxl);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* display change listener */
|
|
|
|
|
2012-11-13 17:51:41 +04:00
|
|
|
static void display_update(DisplayChangeListener *dcl,
|
|
|
|
int x, int y, int w, int h)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
2013-02-28 15:15:00 +04:00
|
|
|
PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
|
|
|
|
|
|
|
|
if (qxl->mode == QXL_MODE_VGA) {
|
|
|
|
qemu_spice_display_update(&qxl->ssd, x, y, w, h);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-02-28 18:03:04 +04:00
|
|
|
static void display_switch(DisplayChangeListener *dcl,
|
|
|
|
struct DisplaySurface *surface)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
2013-02-28 15:15:00 +04:00
|
|
|
PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
|
|
|
|
|
2013-02-28 19:42:28 +04:00
|
|
|
qxl->ssd.ds = surface;
|
2013-02-28 15:15:00 +04:00
|
|
|
if (qxl->mode == QXL_MODE_VGA) {
|
2013-02-28 18:03:04 +04:00
|
|
|
qemu_spice_display_switch(&qxl->ssd, surface);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-03-01 16:03:04 +04:00
|
|
|
static void display_refresh(DisplayChangeListener *dcl)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
2013-02-28 15:15:00 +04:00
|
|
|
PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
|
|
|
|
|
|
|
|
if (qxl->mode == QXL_MODE_VGA) {
|
|
|
|
qemu_spice_display_refresh(&qxl->ssd);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-11-13 17:51:41 +04:00
|
|
|
static DisplayChangeListenerOps display_listener_ops = {
|
|
|
|
.dpy_name = "spice/qxl",
|
2012-09-28 17:02:08 +04:00
|
|
|
.dpy_gfx_update = display_update,
|
2013-02-28 18:03:04 +04:00
|
|
|
.dpy_gfx_switch = display_switch,
|
2012-11-13 17:51:41 +04:00
|
|
|
.dpy_refresh = display_refresh,
|
2010-04-27 13:50:11 +04:00
|
|
|
};
|
|
|
|
|
2012-06-10 19:05:06 +04:00
|
|
|
static void qxl_init_ramsize(PCIQXLDevice *qxl)
|
2012-02-17 18:02:40 +04:00
|
|
|
{
|
2012-06-10 19:05:06 +04:00
|
|
|
/* vga mode framebuffer / primary surface (bar 0, first part) */
|
|
|
|
if (qxl->vgamem_size_mb < 8) {
|
|
|
|
qxl->vgamem_size_mb = 8;
|
|
|
|
}
|
2015-02-17 19:30:51 +03:00
|
|
|
/* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
|
|
|
|
* less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
|
|
|
|
*/
|
|
|
|
if (qxl->vgamem_size_mb > 256) {
|
|
|
|
qxl->vgamem_size_mb = 256;
|
|
|
|
}
|
2012-06-10 19:05:06 +04:00
|
|
|
qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
|
|
|
|
|
|
|
|
/* vga ram (bar 0, total) */
|
2012-02-17 18:03:24 +04:00
|
|
|
if (qxl->ram_size_mb != -1) {
|
|
|
|
qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
|
|
|
|
}
|
2012-06-10 19:05:06 +04:00
|
|
|
if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
|
|
|
|
qxl->vga.vram_size = qxl->vgamem_size * 2;
|
2012-02-17 18:02:40 +04:00
|
|
|
}
|
|
|
|
|
2011-10-14 20:05:48 +04:00
|
|
|
/* vram32 (surfaces, 32bit, bar 1) */
|
|
|
|
if (qxl->vram32_size_mb != -1) {
|
|
|
|
qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
|
|
|
|
}
|
|
|
|
if (qxl->vram32_size < 4096) {
|
|
|
|
qxl->vram32_size = 4096;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* vram (surfaces, 64bit, bar 4+5) */
|
2012-02-17 18:03:24 +04:00
|
|
|
if (qxl->vram_size_mb != -1) {
|
2016-06-08 15:40:48 +03:00
|
|
|
qxl->vram_size = (uint64_t)qxl->vram_size_mb * 1024 * 1024;
|
2012-02-17 18:03:24 +04:00
|
|
|
}
|
2011-10-14 20:05:48 +04:00
|
|
|
if (qxl->vram_size < qxl->vram32_size) {
|
|
|
|
qxl->vram_size = qxl->vram32_size;
|
2012-02-17 18:02:40 +04:00
|
|
|
}
|
2011-10-14 20:05:48 +04:00
|
|
|
|
2012-02-17 18:02:40 +04:00
|
|
|
if (qxl->revision == 1) {
|
2011-10-14 20:05:48 +04:00
|
|
|
qxl->vram32_size = 4096;
|
2012-02-17 18:02:40 +04:00
|
|
|
qxl->vram_size = 4096;
|
|
|
|
}
|
2015-02-17 19:30:52 +03:00
|
|
|
qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
|
|
|
|
qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
|
|
|
|
qxl->vram32_size = pow2ceil(qxl->vram32_size);
|
|
|
|
qxl->vram_size = pow2ceil(qxl->vram_size);
|
2012-02-17 18:02:40 +04:00
|
|
|
}
|
|
|
|
|
2015-01-19 17:52:36 +03:00
|
|
|
static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
uint8_t* config = qxl->pci.config;
|
|
|
|
uint32_t pci_device_rev;
|
|
|
|
uint32_t io_size;
|
|
|
|
|
|
|
|
qxl->mode = QXL_MODE_UNDEFINED;
|
|
|
|
qxl->generation = 1;
|
|
|
|
qxl->num_memslots = NUM_MEMSLOTS;
|
2011-07-20 13:20:53 +04:00
|
|
|
qemu_mutex_init(&qxl->track_lock);
|
2011-07-20 13:20:58 +04:00
|
|
|
qemu_mutex_init(&qxl->async_lock);
|
|
|
|
qxl->current_async = QXL_UNDEFINED_IO;
|
2012-05-24 20:18:54 +04:00
|
|
|
qxl->guest_bug = 0;
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
switch (qxl->revision) {
|
|
|
|
case 1: /* spice 0.4 -- qxl-1 */
|
|
|
|
pci_device_rev = QXL_REVISION_STABLE_V04;
|
2012-05-10 17:24:53 +04:00
|
|
|
io_size = 8;
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
case 2: /* spice 0.6 -- qxl-2 */
|
|
|
|
pci_device_rev = QXL_REVISION_STABLE_V06;
|
2012-05-10 17:24:53 +04:00
|
|
|
io_size = 16;
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
2011-07-20 13:21:00 +04:00
|
|
|
case 3: /* qxl-3 */
|
2012-08-22 12:16:25 +04:00
|
|
|
pci_device_rev = QXL_REVISION_STABLE_V10;
|
|
|
|
io_size = 32; /* PCI region size must be pow2 */
|
|
|
|
break;
|
|
|
|
case 4: /* qxl-4 */
|
|
|
|
pci_device_rev = QXL_REVISION_STABLE_V12;
|
2015-02-17 19:30:52 +03:00
|
|
|
io_size = pow2ceil(QXL_IO_RANGE_SIZE);
|
2011-07-20 13:21:00 +04:00
|
|
|
break;
|
2012-08-21 14:51:32 +04:00
|
|
|
default:
|
2015-01-19 17:52:36 +03:00
|
|
|
error_setg(errp, "Invalid revision %d for qxl device (max %d)",
|
|
|
|
qxl->revision, QXL_DEFAULT_REVISION);
|
|
|
|
return;
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
|
|
|
|
pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
|
|
|
|
|
|
|
|
qxl->rom_size = qxl_rom_size();
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 17:51:43 +03:00
|
|
|
qxl->rom_size, &error_fatal);
|
2011-12-20 17:59:12 +04:00
|
|
|
vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
|
2010-04-27 13:50:11 +04:00
|
|
|
init_qxl_rom(qxl);
|
|
|
|
init_qxl_ram(qxl);
|
|
|
|
|
2012-09-04 13:39:41 +04:00
|
|
|
qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 17:51:43 +03:00
|
|
|
qxl->vram_size, &error_fatal);
|
2011-12-20 17:59:12 +04:00
|
|
|
vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
|
|
|
|
&qxl->vram_bar, 0, qxl->vram32_size);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
|
2011-08-08 17:08:57 +04:00
|
|
|
"qxl-ioports", io_size);
|
|
|
|
if (qxl->id == 0) {
|
|
|
|
vga_dirty_log_start(&qxl->vga);
|
|
|
|
}
|
2012-08-23 15:02:33 +04:00
|
|
|
memory_region_set_flush_coalesced(&qxl->io_bar);
|
2011-08-08 17:08:57 +04:00
|
|
|
|
|
|
|
|
2011-08-08 17:09:31 +04:00
|
|
|
pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
|
|
|
|
PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2011-08-08 17:09:31 +04:00
|
|
|
pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
|
|
|
|
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2011-08-08 17:09:31 +04:00
|
|
|
pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
|
|
|
|
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2011-08-08 17:09:31 +04:00
|
|
|
pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
|
2011-10-14 20:05:48 +04:00
|
|
|
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
|
|
|
|
|
|
|
|
if (qxl->vram32_size < qxl->vram_size) {
|
|
|
|
/*
|
|
|
|
* Make the 64bit vram bar show up only in case it is
|
|
|
|
* configured to be larger than the 32bit vram bar.
|
|
|
|
*/
|
|
|
|
pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
|
|
|
|
PCI_BASE_ADDRESS_SPACE_MEMORY |
|
|
|
|
PCI_BASE_ADDRESS_MEM_TYPE_64 |
|
|
|
|
PCI_BASE_ADDRESS_MEM_PREFETCH,
|
|
|
|
&qxl->vram_bar);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* print pci bar details */
|
|
|
|
dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
|
|
|
|
qxl->id == 0 ? "pri" : "sec",
|
|
|
|
qxl->vga.vram_size / (1024*1024));
|
2016-06-08 15:40:48 +03:00
|
|
|
dprint(qxl, 1, "vram/32: %" PRIx64 "d MB [region 1]\n",
|
2011-10-14 20:05:48 +04:00
|
|
|
qxl->vram32_size / (1024*1024));
|
2016-06-08 15:40:48 +03:00
|
|
|
dprint(qxl, 1, "vram/64: %" PRIx64 "d MB %s\n",
|
2011-10-14 20:05:48 +04:00
|
|
|
qxl->vram_size / (1024*1024),
|
|
|
|
qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
qxl->ssd.qxl.base.sif = &qxl_interface.base;
|
2013-10-12 00:39:59 +04:00
|
|
|
if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
|
2015-01-19 17:52:36 +03:00
|
|
|
error_setg(errp, "qxl interface %d.%d not supported by spice-server",
|
|
|
|
SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
|
|
|
|
return;
|
2012-10-03 22:13:58 +04:00
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
|
|
|
|
|
2013-10-29 16:29:43 +04:00
|
|
|
qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_reset_state(qxl);
|
|
|
|
|
2012-02-25 01:19:31 +04:00
|
|
|
qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
|
2014-11-04 15:59:59 +03:00
|
|
|
qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2015-01-19 17:52:36 +03:00
|
|
|
static void qxl_realize_primary(PCIDevice *dev, Error **errp)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
2015-05-12 12:27:10 +03:00
|
|
|
PCIQXLDevice *qxl = PCI_QXL(dev);
|
2010-04-27 13:50:11 +04:00
|
|
|
VGACommonState *vga = &qxl->vga;
|
2015-01-19 17:52:36 +03:00
|
|
|
Error *local_err = NULL;
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
qxl->id = 0;
|
2012-06-10 19:05:06 +04:00
|
|
|
qxl_init_ramsize(qxl);
|
2014-08-26 16:16:30 +04:00
|
|
|
vga->vbe_size = qxl->vgamem_size;
|
2012-05-24 11:59:44 +04:00
|
|
|
vga->vram_size_mb = qxl->vga.vram_size >> 20;
|
2013-10-11 21:56:59 +04:00
|
|
|
vga_common_init(vga, OBJECT(dev), true);
|
2013-06-07 05:21:13 +04:00
|
|
|
vga_init(vga, OBJECT(dev),
|
|
|
|
pci_address_space(dev), pci_address_space_io(dev), false);
|
2014-04-29 17:38:39 +04:00
|
|
|
portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
|
2013-06-07 05:19:53 +04:00
|
|
|
vga, "vga");
|
2014-04-29 17:38:39 +04:00
|
|
|
portio_list_set_flush_coalesced(&qxl->vga_port_list);
|
|
|
|
portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2014-01-24 18:35:21 +04:00
|
|
|
vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
|
2013-03-05 18:24:14 +04:00
|
|
|
qemu_spice_display_init_common(&qxl->ssd);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2015-01-19 17:52:36 +03:00
|
|
|
qxl_realize_common(qxl, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
2012-11-02 12:37:27 +04:00
|
|
|
}
|
|
|
|
|
2012-11-13 17:51:41 +04:00
|
|
|
qxl->ssd.dcl.ops = &display_listener_ops;
|
2013-03-15 18:45:54 +04:00
|
|
|
qxl->ssd.dcl.con = vga->con;
|
2013-04-23 17:44:31 +04:00
|
|
|
register_displaychangelistener(&qxl->ssd.dcl);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2015-01-19 17:52:36 +03:00
|
|
|
static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
|
|
|
static int device_id = 1;
|
2015-05-12 12:27:10 +03:00
|
|
|
PCIQXLDevice *qxl = PCI_QXL(dev);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
qxl->id = device_id++;
|
2012-06-10 19:05:06 +04:00
|
|
|
qxl_init_ramsize(qxl);
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 17:51:43 +03:00
|
|
|
qxl->vga.vram_size, &error_fatal);
|
2011-12-20 17:59:12 +04:00
|
|
|
vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
|
2011-08-08 17:08:57 +04:00
|
|
|
qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
|
2014-01-24 18:35:21 +04:00
|
|
|
qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2015-01-19 17:52:36 +03:00
|
|
|
qxl_realize_common(qxl, errp);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void qxl_pre_save(void *opaque)
|
|
|
|
{
|
|
|
|
PCIQXLDevice* d = opaque;
|
|
|
|
uint8_t *ram_start = d->vga.vram_ptr;
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_pre_save(d->id);
|
2010-04-27 13:50:11 +04:00
|
|
|
if (d->last_release == NULL) {
|
|
|
|
d->last_release_offset = 0;
|
|
|
|
} else {
|
|
|
|
d->last_release_offset = (uint8_t *)d->last_release - ram_start;
|
|
|
|
}
|
|
|
|
assert(d->last_release_offset < d->vga.vram_size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qxl_pre_load(void *opaque)
|
|
|
|
{
|
|
|
|
PCIQXLDevice* d = opaque;
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_pre_load(d->id);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_hard_reset(d, 1);
|
|
|
|
qxl_exit_vga_mode(d);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-10-25 17:39:50 +04:00
|
|
|
static void qxl_create_memslots(PCIQXLDevice *d)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < NUM_MEMSLOTS; i++) {
|
|
|
|
if (!d->guest_slots[i].active) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
qxl_add_memslot(d, i, 0, QXL_SYNC);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
static int qxl_post_load(void *opaque, int version)
|
|
|
|
{
|
|
|
|
PCIQXLDevice* d = opaque;
|
|
|
|
uint8_t *ram_start = d->vga.vram_ptr;
|
|
|
|
QXLCommandExt *cmds;
|
2011-10-25 17:39:50 +04:00
|
|
|
int in, out, newmode;
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
assert(d->last_release_offset < d->vga.vram_size);
|
|
|
|
if (d->last_release_offset == 0) {
|
|
|
|
d->last_release = NULL;
|
|
|
|
} else {
|
|
|
|
d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
|
|
|
|
|
2012-03-18 16:46:14 +04:00
|
|
|
trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
|
2010-04-27 13:50:11 +04:00
|
|
|
newmode = d->mode;
|
|
|
|
d->mode = QXL_MODE_UNDEFINED;
|
2011-10-25 17:39:50 +04:00
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
switch (newmode) {
|
|
|
|
case QXL_MODE_UNDEFINED:
|
2012-11-28 19:08:22 +04:00
|
|
|
qxl_create_memslots(d);
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
case QXL_MODE_VGA:
|
2011-10-25 17:39:50 +04:00
|
|
|
qxl_create_memslots(d);
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_enter_vga_mode(d);
|
|
|
|
break;
|
|
|
|
case QXL_MODE_NATIVE:
|
2011-10-25 17:39:50 +04:00
|
|
|
qxl_create_memslots(d);
|
2011-07-20 13:20:58 +04:00
|
|
|
qxl_create_guest_primary(d, 1, QXL_SYNC);
|
2010-04-27 13:50:11 +04:00
|
|
|
|
|
|
|
/* replay surface-create and cursor-set commands */
|
2015-10-29 18:55:21 +03:00
|
|
|
cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
|
2012-09-04 13:39:41 +04:00
|
|
|
for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
|
2010-04-27 13:50:11 +04:00
|
|
|
if (d->guest_surfaces.cmds[in] == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
cmds[out].cmd.data = d->guest_surfaces.cmds[in];
|
|
|
|
cmds[out].cmd.type = QXL_CMD_SURFACE;
|
|
|
|
cmds[out].group_id = MEMSLOT_GROUP_GUEST;
|
|
|
|
out++;
|
|
|
|
}
|
2011-10-18 20:58:54 +04:00
|
|
|
if (d->guest_cursor) {
|
|
|
|
cmds[out].cmd.data = d->guest_cursor;
|
|
|
|
cmds[out].cmd.type = QXL_CMD_CURSOR;
|
|
|
|
cmds[out].group_id = MEMSLOT_GROUP_GUEST;
|
|
|
|
out++;
|
|
|
|
}
|
2011-07-20 13:20:52 +04:00
|
|
|
qxl_spice_loadvm_commands(d, cmds, out);
|
2011-08-21 07:09:37 +04:00
|
|
|
g_free(cmds);
|
2012-08-22 12:16:25 +04:00
|
|
|
if (d->guest_monitors_config) {
|
|
|
|
qxl_spice_monitors_config_async(d, 1);
|
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
break;
|
|
|
|
case QXL_MODE_COMPAT:
|
2011-10-25 17:39:50 +04:00
|
|
|
/* note: no need to call qxl_create_memslots, qxl_set_mode
|
|
|
|
* creates the mem slot. */
|
2010-04-27 13:50:11 +04:00
|
|
|
qxl_set_mode(d, d->shadow_rom.mode, 1);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-05 20:05:52 +03:00
|
|
|
#define QXL_SAVE_VERSION 21
|
2010-04-27 13:50:11 +04:00
|
|
|
|
2012-08-22 12:16:25 +04:00
|
|
|
static bool qxl_monitors_config_needed(void *opaque)
|
|
|
|
{
|
|
|
|
PCIQXLDevice *qxl = opaque;
|
|
|
|
|
|
|
|
return qxl->guest_monitors_config != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
static VMStateDescription qxl_memslot = {
|
|
|
|
.name = "qxl-memslot",
|
|
|
|
.version_id = QXL_SAVE_VERSION,
|
|
|
|
.minimum_version_id = QXL_SAVE_VERSION,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT64(slot.mem_start, struct guest_slots),
|
|
|
|
VMSTATE_UINT64(slot.mem_end, struct guest_slots),
|
|
|
|
VMSTATE_UINT32(active, struct guest_slots),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static VMStateDescription qxl_surface = {
|
|
|
|
.name = "qxl-surface",
|
|
|
|
.version_id = QXL_SAVE_VERSION,
|
|
|
|
.minimum_version_id = QXL_SAVE_VERSION,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32(width, QXLSurfaceCreate),
|
|
|
|
VMSTATE_UINT32(height, QXLSurfaceCreate),
|
|
|
|
VMSTATE_INT32(stride, QXLSurfaceCreate),
|
|
|
|
VMSTATE_UINT32(format, QXLSurfaceCreate),
|
|
|
|
VMSTATE_UINT32(position, QXLSurfaceCreate),
|
|
|
|
VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
|
|
|
|
VMSTATE_UINT32(flags, QXLSurfaceCreate),
|
|
|
|
VMSTATE_UINT32(type, QXLSurfaceCreate),
|
|
|
|
VMSTATE_UINT64(mem, QXLSurfaceCreate),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2012-08-22 12:16:25 +04:00
|
|
|
static VMStateDescription qxl_vmstate_monitors_config = {
|
|
|
|
.name = "qxl/monitors-config",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-09-23 16:09:54 +04:00
|
|
|
.needed = qxl_monitors_config_needed,
|
2012-08-22 12:16:25 +04:00
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-04-27 13:50:11 +04:00
|
|
|
static VMStateDescription qxl_vmstate = {
|
|
|
|
.name = "qxl",
|
|
|
|
.version_id = QXL_SAVE_VERSION,
|
|
|
|
.minimum_version_id = QXL_SAVE_VERSION,
|
|
|
|
.pre_save = qxl_pre_save,
|
|
|
|
.pre_load = qxl_pre_load,
|
|
|
|
.post_load = qxl_post_load,
|
2012-08-22 12:16:25 +04:00
|
|
|
.fields = (VMStateField[]) {
|
2010-04-27 13:50:11 +04:00
|
|
|
VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
|
|
|
|
VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
|
|
|
|
VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
|
|
|
|
VMSTATE_UINT32(num_free_res, PCIQXLDevice),
|
|
|
|
VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
|
|
|
|
VMSTATE_UINT32(mode, PCIQXLDevice),
|
|
|
|
VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
|
2011-01-05 20:05:52 +03:00
|
|
|
VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
|
|
|
|
VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
|
|
|
|
qxl_memslot, struct guest_slots),
|
|
|
|
VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
|
|
|
|
qxl_surface, QXLSurfaceCreate),
|
2012-09-04 13:39:41 +04:00
|
|
|
VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
|
|
|
|
VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
|
|
|
|
ssd.num_surfaces, 0,
|
|
|
|
vmstate_info_uint64, uint64_t),
|
2011-01-05 20:05:52 +03:00
|
|
|
VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
|
2010-04-27 13:50:11 +04:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
},
|
2014-09-23 16:09:54 +04:00
|
|
|
.subsections = (const VMStateDescription*[]) {
|
|
|
|
&qxl_vmstate_monitors_config,
|
|
|
|
NULL
|
2012-08-22 12:16:25 +04:00
|
|
|
}
|
2010-04-27 13:50:11 +04:00
|
|
|
};
|
|
|
|
|
2011-10-17 16:11:16 +04:00
|
|
|
static Property qxl_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
|
|
|
|
64 * 1024 * 1024),
|
2016-06-08 15:40:48 +03:00
|
|
|
DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size,
|
2011-10-17 16:11:16 +04:00
|
|
|
64 * 1024 * 1024),
|
|
|
|
DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
|
|
|
|
QXL_DEFAULT_REVISION),
|
|
|
|
DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
|
|
|
|
DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
|
|
|
|
DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
|
2012-02-17 18:03:24 +04:00
|
|
|
DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
|
2012-03-30 00:24:38 +04:00
|
|
|
DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
|
|
|
|
DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
|
2012-06-11 12:42:53 +04:00
|
|
|
DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
|
2012-09-04 13:39:41 +04:00
|
|
|
DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
|
2015-07-06 09:56:38 +03:00
|
|
|
#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
|
|
|
|
DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
|
|
|
|
#endif
|
2011-10-17 16:11:16 +04:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2015-05-12 12:27:10 +03:00
|
|
|
static void qxl_pci_class_init(ObjectClass *klass, void *data)
|
2011-12-04 22:22:06 +04:00
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 22:22:06 +04:00
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->vendor_id = REDHAT_PCI_VENDOR_ID;
|
|
|
|
k->device_id = QXL_DEVICE_ID_STABLE;
|
2013-07-29 18:17:45 +04:00
|
|
|
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
|
2011-12-08 07:34:16 +04:00
|
|
|
dc->reset = qxl_reset_handler;
|
|
|
|
dc->vmsd = &qxl_vmstate;
|
|
|
|
dc->props = qxl_properties;
|
2015-05-12 12:27:10 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo qxl_pci_type_info = {
|
|
|
|
.name = TYPE_PCI_QXL,
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(PCIQXLDevice),
|
|
|
|
.abstract = true,
|
|
|
|
.class_init = qxl_pci_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void qxl_primary_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->realize = qxl_realize_primary;
|
|
|
|
k->romfile = "vgabios-qxl.bin";
|
|
|
|
k->class_id = PCI_CLASS_DISPLAY_VGA;
|
|
|
|
dc->desc = "Spice QXL GPU (primary, vga compatible)";
|
2014-02-05 19:36:48 +04:00
|
|
|
dc->hotpluggable = false;
|
2011-12-04 22:22:06 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo qxl_primary_info = {
|
2011-12-08 07:34:16 +04:00
|
|
|
.name = "qxl-vga",
|
2015-05-12 12:27:10 +03:00
|
|
|
.parent = TYPE_PCI_QXL,
|
2011-12-08 07:34:16 +04:00
|
|
|
.class_init = qxl_primary_class_init,
|
2010-04-27 13:50:11 +04:00
|
|
|
};
|
|
|
|
|
2011-12-04 22:22:06 +04:00
|
|
|
static void qxl_secondary_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 22:22:06 +04:00
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
2015-01-19 17:52:36 +03:00
|
|
|
k->realize = qxl_realize_secondary;
|
2011-12-04 22:22:06 +04:00
|
|
|
k->class_id = PCI_CLASS_DISPLAY_OTHER;
|
2011-12-08 07:34:16 +04:00
|
|
|
dc->desc = "Spice QXL GPU (secondary)";
|
2011-12-04 22:22:06 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo qxl_secondary_info = {
|
2011-12-08 07:34:16 +04:00
|
|
|
.name = "qxl",
|
2015-05-12 12:27:10 +03:00
|
|
|
.parent = TYPE_PCI_QXL,
|
2011-12-08 07:34:16 +04:00
|
|
|
.class_init = qxl_secondary_class_init,
|
2010-04-27 13:50:11 +04:00
|
|
|
};
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
static void qxl_register_types(void)
|
2010-04-27 13:50:11 +04:00
|
|
|
{
|
2015-05-12 12:27:10 +03:00
|
|
|
type_register_static(&qxl_pci_type_info);
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&qxl_primary_info);
|
|
|
|
type_register_static(&qxl_secondary_info);
|
2010-04-27 13:50:11 +04:00
|
|
|
}
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
type_init(qxl_register_types)
|