2015-05-15 05:22:58 +03:00
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/*
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* Xilinx Zynq MPSoC emulation
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*
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* Copyright (C) 2015 Xilinx Inc
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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2015-12-07 19:23:45 +03:00
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#include "qemu/osdep.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
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#include "qapi/error.h"
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2016-01-19 23:51:44 +03:00
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#include "qemu-common.h"
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#include "cpu.h"
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2015-05-15 05:22:58 +03:00
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#include "hw/arm/xlnx-zynqmp.h"
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2015-05-15 05:23:04 +03:00
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#include "hw/intc/arm_gic_common.h"
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2015-05-15 05:23:01 +03:00
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#include "exec/address-spaces.h"
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2016-06-06 18:59:30 +03:00
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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2015-05-15 05:23:01 +03:00
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#define GIC_NUM_SPI_INTR 160
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2015-05-15 05:23:04 +03:00
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#define ARM_PHYS_TIMER_PPI 30
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#define ARM_VIRT_TIMER_PPI 27
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2015-05-15 05:23:01 +03:00
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#define GIC_BASE_ADDR 0xf9000000
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#define GIC_DIST_ADDR 0xf9010000
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#define GIC_CPU_ADDR 0xf9020000
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2015-09-08 19:38:45 +03:00
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#define SATA_INTR 133
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#define SATA_ADDR 0xFD0C0000
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#define SATA_NUM_PORTS 2
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2016-06-14 17:59:15 +03:00
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#define DP_ADDR 0xfd4a0000
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#define DP_IRQ 113
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#define DPDMA_ADDR 0xfd4c0000
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#define DPDMA_IRQ 116
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2015-05-15 05:23:12 +03:00
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static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
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0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
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};
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static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
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57, 59, 61, 63,
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};
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2015-05-15 05:23:21 +03:00
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static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
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0xFF000000, 0xFF010000,
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};
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static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
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21, 22,
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};
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2015-10-08 16:21:03 +03:00
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static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
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0xFF160000, 0xFF170000,
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};
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static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
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48, 49,
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};
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2016-01-21 17:15:03 +03:00
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static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
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0xFF040000, 0xFF050000,
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};
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static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
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19, 20,
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};
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2015-05-15 05:23:01 +03:00
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typedef struct XlnxZynqMPGICRegion {
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int region_index;
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uint32_t address;
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} XlnxZynqMPGICRegion;
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static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
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{ .region_index = 0, .address = GIC_DIST_ADDR, },
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{ .region_index = 1, .address = GIC_CPU_ADDR, },
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};
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2015-05-15 05:22:58 +03:00
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2015-05-15 05:23:04 +03:00
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static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
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{
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return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
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}
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2016-06-06 18:59:29 +03:00
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static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
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Error **errp)
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{
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Error *err = NULL;
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int i;
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for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
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char *name;
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object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
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"cortex-r5-" TYPE_ARM_CPU);
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object_property_add_child(OBJECT(s), "rpu-cpu[*]",
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OBJECT(&s->rpu_cpu[i]), &error_abort);
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name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
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if (strcmp(name, boot_cpu)) {
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/* Secondary CPUs start in PSCI powered-down state */
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object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
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"start-powered-off", &error_abort);
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} else {
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s->boot_cpu_ptr = &s->rpu_cpu[i];
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}
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g_free(name);
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object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
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&error_abort);
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object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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}
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}
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2015-05-15 05:22:58 +03:00
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static void xlnx_zynqmp_init(Object *obj)
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{
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XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
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int i;
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2015-06-19 16:17:45 +03:00
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for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
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object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
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2015-05-15 05:22:58 +03:00
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"cortex-a53-" TYPE_ARM_CPU);
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2015-06-19 16:17:45 +03:00
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object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
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2015-05-15 05:22:58 +03:00
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&error_abort);
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}
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2015-05-15 05:23:01 +03:00
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2016-01-13 01:39:18 +03:00
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object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
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(Object **)&s->ddr_ram,
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qdev_prop_allow_set_link_before_realize,
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OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
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2016-06-06 18:59:30 +03:00
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object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
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2015-05-15 05:23:01 +03:00
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qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
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2015-05-15 05:23:12 +03:00
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for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
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object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
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qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
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}
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2015-05-15 05:23:21 +03:00
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for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
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object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
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qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
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}
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2015-09-08 19:38:45 +03:00
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object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
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qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
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2015-10-08 16:21:03 +03:00
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for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
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object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
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TYPE_SYSBUS_SDHCI);
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qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
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sysbus_get_default());
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}
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2016-01-21 17:15:03 +03:00
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for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
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object_initialize(&s->spi[i], sizeof(s->spi[i]),
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TYPE_XILINX_SPIPS);
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qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
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}
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2016-06-14 17:59:15 +03:00
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object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
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qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
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object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
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qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
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2015-05-15 05:22:58 +03:00
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}
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static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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{
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XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
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2015-05-15 05:23:01 +03:00
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MemoryRegion *system_memory = get_system_memory();
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2015-05-15 05:22:58 +03:00
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uint8_t i;
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2016-01-13 01:39:18 +03:00
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uint64_t ram_size;
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2015-06-19 16:17:45 +03:00
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const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
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2016-01-13 01:39:18 +03:00
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ram_addr_t ddr_low_size, ddr_high_size;
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2015-05-15 05:23:12 +03:00
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qemu_irq gic_spi[GIC_NUM_SPI_INTR];
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2015-05-15 05:22:58 +03:00
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Error *err = NULL;
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2016-01-13 01:39:18 +03:00
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ram_size = memory_region_size(s->ddr_ram);
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/* Create the DDR Memory Regions. User friendly checks should happen at
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* the board level
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*/
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if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
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/* The RAM size is above the maximum available for the low DDR.
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* Create the high DDR memory region as well.
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*/
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assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
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ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
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ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
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memory_region_init_alias(&s->ddr_ram_high, NULL,
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"ddr-ram-high", s->ddr_ram,
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ddr_low_size, ddr_high_size);
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memory_region_add_subregion(get_system_memory(),
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XLNX_ZYNQMP_HIGH_RAM_START,
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&s->ddr_ram_high);
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} else {
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/* RAM must be non-zero */
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assert(ram_size);
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ddr_low_size = ram_size;
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}
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memory_region_init_alias(&s->ddr_ram_low, NULL,
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"ddr-ram-low", s->ddr_ram,
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0, ddr_low_size);
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memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
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2015-08-25 17:45:06 +03:00
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/* Create the four OCM banks */
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for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
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char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
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memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
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Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
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err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 17:51:43 +03:00
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XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
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2015-08-25 17:45:06 +03:00
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vmstate_register_ram_global(&s->ocm_ram[i]);
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memory_region_add_subregion(get_system_memory(),
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XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
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i * XLNX_ZYNQMP_OCM_RAM_SIZE,
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&s->ocm_ram[i]);
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g_free(ocm_name);
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}
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2015-05-15 05:23:01 +03:00
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
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qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
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2015-06-19 16:17:45 +03:00
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
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2015-05-15 05:23:01 +03:00
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2016-06-06 18:59:30 +03:00
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|
|
/* Realize APUs before realizing the GIC. KVM requires this. */
|
2015-06-19 16:17:45 +03:00
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
|
2015-06-19 16:17:45 +03:00
|
|
|
char *name;
|
2015-05-15 05:23:04 +03:00
|
|
|
|
2015-06-19 16:17:45 +03:00
|
|
|
object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
|
2015-05-15 05:22:58 +03:00
|
|
|
"psci-conduit", &error_abort);
|
2015-06-19 16:17:45 +03:00
|
|
|
|
|
|
|
name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
|
|
|
|
if (strcmp(name, boot_cpu)) {
|
2015-05-15 05:22:58 +03:00
|
|
|
/* Secondary CPUs start in PSCI powered-down state */
|
2015-06-19 16:17:45 +03:00
|
|
|
object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
|
2015-05-15 05:22:58 +03:00
|
|
|
"start-powered-off", &error_abort);
|
2015-06-19 16:17:45 +03:00
|
|
|
} else {
|
|
|
|
s->boot_cpu_ptr = &s->apu_cpu[i];
|
2015-05-15 05:22:58 +03:00
|
|
|
}
|
2015-07-10 03:51:29 +03:00
|
|
|
g_free(name);
|
2015-05-15 05:22:58 +03:00
|
|
|
|
2016-06-06 18:59:29 +03:00
|
|
|
object_property_set_bool(OBJECT(&s->apu_cpu[i]),
|
|
|
|
s->secure, "has_el3", NULL);
|
2015-06-19 16:17:45 +03:00
|
|
|
object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
|
2015-09-08 19:38:45 +03:00
|
|
|
"reset-cbar", &error_abort);
|
2015-06-19 16:17:45 +03:00
|
|
|
object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
|
|
|
|
&err);
|
2015-05-15 05:22:58 +03:00
|
|
|
if (err) {
|
2015-09-14 16:39:47 +03:00
|
|
|
error_propagate(errp, err);
|
2015-05-15 05:22:58 +03:00
|
|
|
return;
|
|
|
|
}
|
2016-06-06 18:59:30 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
|
|
|
|
if (err) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
|
|
|
|
SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
|
|
|
|
const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
|
|
|
|
MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
|
|
|
|
uint32_t addr = r->address;
|
|
|
|
int j;
|
|
|
|
|
|
|
|
sysbus_mmio_map(gic, r->region_index, addr);
|
|
|
|
|
|
|
|
for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
|
|
|
|
MemoryRegion *alias = &s->gic_mr[i][j];
|
|
|
|
|
|
|
|
addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
|
|
|
|
memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
|
|
|
|
0, XLNX_ZYNQMP_GIC_REGION_SIZE);
|
|
|
|
memory_region_add_subregion(system_memory, addr, alias);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
|
|
|
|
qemu_irq irq;
|
2015-05-15 05:23:01 +03:00
|
|
|
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
|
2015-06-19 16:17:45 +03:00
|
|
|
qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
|
|
|
|
ARM_CPU_IRQ));
|
2015-05-15 05:23:04 +03:00
|
|
|
irq = qdev_get_gpio_in(DEVICE(&s->gic),
|
|
|
|
arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
|
2015-06-19 16:17:45 +03:00
|
|
|
qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
|
2015-05-15 05:23:04 +03:00
|
|
|
irq = qdev_get_gpio_in(DEVICE(&s->gic),
|
|
|
|
arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
|
2015-06-19 16:17:45 +03:00
|
|
|
qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
|
2015-05-15 05:22:58 +03:00
|
|
|
}
|
2015-05-15 05:23:12 +03:00
|
|
|
|
2016-06-06 18:59:29 +03:00
|
|
|
if (s->has_rpu) {
|
|
|
|
xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
|
2015-06-19 16:17:45 +03:00
|
|
|
if (err) {
|
2015-09-14 16:39:47 +03:00
|
|
|
error_propagate(errp, err);
|
2015-06-19 16:17:45 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-06-19 16:17:45 +03:00
|
|
|
if (!s->boot_cpu_ptr) {
|
2015-12-18 18:35:19 +03:00
|
|
|
error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
|
2015-06-19 16:17:45 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-05-15 05:23:12 +03:00
|
|
|
for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
|
|
|
|
gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
|
|
|
|
NICInfo *nd = &nd_table[i];
|
|
|
|
|
|
|
|
if (nd->used) {
|
|
|
|
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
|
|
|
|
qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
|
|
|
|
}
|
2016-09-22 20:13:07 +03:00
|
|
|
object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
|
|
|
|
&error_abort);
|
2015-05-15 05:23:12 +03:00
|
|
|
object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
|
|
|
|
if (err) {
|
2015-09-14 16:39:47 +03:00
|
|
|
error_propagate(errp, err);
|
2015-05-15 05:23:12 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
|
|
|
|
gic_spi[gem_intr[i]]);
|
|
|
|
}
|
2015-05-15 05:23:21 +03:00
|
|
|
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
|
2016-06-06 18:59:31 +03:00
|
|
|
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
|
2015-05-15 05:23:21 +03:00
|
|
|
object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
|
|
|
|
if (err) {
|
2015-09-14 16:39:47 +03:00
|
|
|
error_propagate(errp, err);
|
2015-05-15 05:23:21 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
|
|
|
|
gic_spi[uart_intr[i]]);
|
|
|
|
}
|
2015-09-08 19:38:45 +03:00
|
|
|
|
|
|
|
object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
|
|
|
|
&error_abort);
|
|
|
|
object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
|
|
|
|
if (err) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
|
2015-10-08 16:21:03 +03:00
|
|
|
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
|
2016-02-18 17:16:18 +03:00
|
|
|
char *bus_name;
|
|
|
|
|
2015-10-08 16:21:03 +03:00
|
|
|
object_property_set_bool(OBJECT(&s->sdhci[i]), true,
|
|
|
|
"realized", &err);
|
|
|
|
if (err) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
|
|
|
|
sdhci_addr[i]);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
|
|
|
|
gic_spi[sdhci_intr[i]]);
|
2016-02-18 17:16:18 +03:00
|
|
|
/* Alias controller SD bus to the SoC itself */
|
|
|
|
bus_name = g_strdup_printf("sd-bus%d", i);
|
|
|
|
object_property_add_alias(OBJECT(s), bus_name,
|
|
|
|
OBJECT(&s->sdhci[i]), "sd-bus",
|
|
|
|
&error_abort);
|
|
|
|
g_free(bus_name);
|
2015-10-08 16:21:03 +03:00
|
|
|
}
|
2016-01-21 17:15:03 +03:00
|
|
|
|
|
|
|
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
|
|
|
|
gchar *bus_name;
|
|
|
|
|
|
|
|
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
|
|
|
|
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
|
|
|
|
gic_spi[spi_intr[i]]);
|
|
|
|
|
|
|
|
/* Alias controller SPI bus to the SoC itself */
|
|
|
|
bus_name = g_strdup_printf("spi%d", i);
|
|
|
|
object_property_add_alias(OBJECT(s), bus_name,
|
|
|
|
OBJECT(&s->spi[i]), "spi0",
|
|
|
|
&error_abort);
|
2016-06-14 17:59:15 +03:00
|
|
|
g_free(bus_name);
|
|
|
|
}
|
|
|
|
|
|
|
|
object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
|
|
|
|
if (err) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
|
|
|
|
|
|
|
|
object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
|
|
|
|
if (err) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
2016-01-21 17:15:03 +03:00
|
|
|
}
|
2016-06-14 17:59:15 +03:00
|
|
|
object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
|
|
|
|
&error_abort);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
|
2015-05-15 05:22:58 +03:00
|
|
|
}
|
|
|
|
|
2015-06-19 16:17:45 +03:00
|
|
|
static Property xlnx_zynqmp_props[] = {
|
|
|
|
DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
|
2016-06-06 18:59:29 +03:00
|
|
|
DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
|
2016-06-06 18:59:29 +03:00
|
|
|
DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
|
2015-06-19 16:17:45 +03:00
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
2015-05-15 05:22:58 +03:00
|
|
|
static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
2015-06-19 16:17:45 +03:00
|
|
|
dc->props = xlnx_zynqmp_props;
|
2015-05-15 05:22:58 +03:00
|
|
|
dc->realize = xlnx_zynqmp_realize;
|
qdev: Protect device-list-properties against broken devices
Several devices don't survive object_unref(object_new(T)): they crash
or hang during cleanup, or they leave dangling pointers behind.
This breaks at least device-list-properties, because
qmp_device_list_properties() needs to create a device to find its
properties. Broken in commit f4eb32b "qmp: show QOM properties in
device-list-properties", v2.1. Example reproducer:
$ qemu-system-aarch64 -nodefaults -display none -machine none -S -qmp stdio
{"QMP": {"version": {"qemu": {"micro": 50, "minor": 4, "major": 2}, "package": ""}, "capabilities": []}}
{ "execute": "qmp_capabilities" }
{"return": {}}
{ "execute": "device-list-properties", "arguments": { "typename": "pxa2xx-pcmcia" } }
qemu-system-aarch64: /home/armbru/work/qemu/memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed.
Aborted (core dumped)
[Exit 134 (SIGABRT)]
Unfortunately, I can't fix the problems in these devices right now.
Instead, add DeviceClass member cannot_destroy_with_object_finalize_yet
to mark them:
* Hang during cleanup (didn't debug, so I can't say why):
"realview_pci", "versatile_pci".
* Dangling pointer in cpus: most CPUs, plus "allwinner-a10", "digic",
"fsl,imx25", "fsl,imx31", "xlnx,zynqmp", because they create such
CPUs
* Assert kvm_enabled(): "host-x86_64-cpu", host-i386-cpu",
"host-powerpc64-cpu", "host-embedded-powerpc-cpu",
"host-powerpc-cpu" (the powerpc ones can't currently reach the
assertion, because the CPUs are only registered when KVM is enabled,
but the assertion is arguably in the wrong place all the same)
Make qmp_device_list_properties() fail cleanly when the device is so
marked. This improves device-list-properties from "crashes, hangs or
leaves dangling pointers behind" to "fails". Not a complete fix, just
a better-than-nothing work-around. In the above reproducer,
device-list-properties now fails with "Can't list properties of device
'pxa2xx-pcmcia'".
This also protects -device FOO,help, which uses the same machinery
since commit ef52358 "qdev-monitor: include QOM properties in -device
FOO, help output", v2.2. Example reproducer:
$ qemu-system-aarch64 -machine none -device pxa2xx-pcmcia,help
Before:
qemu-system-aarch64: .../memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed.
After:
Can't list properties of device 'pxa2xx-pcmcia'
Cc: "Andreas Färber" <afaerber@suse.de>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Anthony Green <green@moxielogic.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Jia Liu <proljc@gmail.com>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Richard Henderson <rth@twiddle.net>
Cc: qemu-ppc@nongnu.org
Cc: qemu-stable@nongnu.org
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <1443689999-12182-10-git-send-email-armbru@redhat.com>
2015-10-01 11:59:58 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Reason: creates an ARM CPU, thus use after free(), see
|
|
|
|
* arm_cpu_class_init()
|
|
|
|
*/
|
|
|
|
dc->cannot_destroy_with_object_finalize_yet = true;
|
2015-05-15 05:22:58 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo xlnx_zynqmp_type_info = {
|
|
|
|
.name = TYPE_XLNX_ZYNQMP,
|
|
|
|
.parent = TYPE_DEVICE,
|
|
|
|
.instance_size = sizeof(XlnxZynqMPState),
|
|
|
|
.instance_init = xlnx_zynqmp_init,
|
|
|
|
.class_init = xlnx_zynqmp_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void xlnx_zynqmp_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&xlnx_zynqmp_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(xlnx_zynqmp_register_types)
|