ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 12:46:40 +03:00
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/*
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* QEMU PowerPC PowerNV XSCOM bus definitions
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2020-10-16 17:53:46 +03:00
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* version 2.1 of the License, or (at your option) any later version.
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ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 12:46:40 +03:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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2019-03-15 17:51:21 +03:00
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#ifndef PPC_PNV_XSCOM_H
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#define PPC_PNV_XSCOM_H
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ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 12:46:40 +03:00
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#include "qom/object.h"
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2019-12-11 19:04:15 +03:00
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typedef struct PnvXScomInterface PnvXScomInterface;
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ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 12:46:40 +03:00
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#define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface"
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#define PNV_XSCOM_INTERFACE(obj) \
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2019-12-11 19:04:15 +03:00
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INTERFACE_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE)
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2020-09-03 23:43:22 +03:00
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typedef struct PnvXScomInterfaceClass PnvXScomInterfaceClass;
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2020-09-01 00:07:33 +03:00
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DECLARE_CLASS_CHECKERS(PnvXScomInterfaceClass, PNV_XSCOM_INTERFACE,
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ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 12:46:40 +03:00
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TYPE_PNV_XSCOM_INTERFACE)
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2020-09-03 23:43:22 +03:00
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struct PnvXScomInterfaceClass {
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ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 12:46:40 +03:00
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InterfaceClass parent;
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2017-12-15 16:56:01 +03:00
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int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset);
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2020-09-03 23:43:22 +03:00
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};
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ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 12:46:40 +03:00
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2016-10-22 12:46:41 +03:00
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/*
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2016-11-14 12:12:55 +03:00
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* Layout of the XSCOM PCB addresses of EX core 1 (POWER 8)
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2016-10-22 12:46:41 +03:00
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*
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* GPIO 0x1100xxxx
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* SCOM 0x1101xxxx
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* OHA 0x1102xxxx
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* CLOCK CTL 0x1103xxxx
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* FIR 0x1104xxxx
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* THERM 0x1105xxxx
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* <reserved> 0x1106xxxx
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* ..
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* 0x110Exxxx
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* PCB SLAVE 0x110Fxxxx
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*/
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2018-01-15 21:04:04 +03:00
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#define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
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#define PNV_XSCOM_EX_BASE(core) \
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(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
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#define PNV_XSCOM_EX_SIZE 0x100000
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2016-10-22 12:46:42 +03:00
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#define PNV_XSCOM_LPC_BASE 0xb0020
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#define PNV_XSCOM_LPC_SIZE 0x4
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2017-04-05 15:41:26 +03:00
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#define PNV_XSCOM_PSIHB_BASE 0x2010900
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#define PNV_XSCOM_PSIHB_SIZE 0x20
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2017-04-05 15:41:27 +03:00
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#define PNV_XSCOM_OCC_BASE 0x0066000
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#define PNV_XSCOM_OCC_SIZE 0x6000
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2019-12-11 11:29:11 +03:00
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#define PNV_XSCOM_PBA_BASE 0x2013f00
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#define PNV_XSCOM_PBA_SIZE 0x40
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2020-01-27 17:45:06 +03:00
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#define PNV_XSCOM_PBCQ_NEST_BASE 0x2012000
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#define PNV_XSCOM_PBCQ_NEST_SIZE 0x46
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#define PNV_XSCOM_PBCQ_PCI_BASE 0x9012000
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#define PNV_XSCOM_PBCQ_PCI_SIZE 0x15
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#define PNV_XSCOM_PBCQ_SPCI_BASE 0x9013c00
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#define PNV_XSCOM_PBCQ_SPCI_SIZE 0x5
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2019-12-05 21:44:51 +03:00
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/*
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* Layout of the XSCOM PCB addresses (POWER 9)
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*/
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2019-03-08 01:35:44 +03:00
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#define PNV9_XSCOM_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV9_XSCOM_EC_SIZE 0x100000
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#define PNV9_XSCOM_EQ_BASE(core) \
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((uint64_t)(((core) & 0x1C) + 0x40) << 22)
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#define PNV9_XSCOM_EQ_SIZE 0x100000
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2019-03-08 01:35:42 +03:00
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#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
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#define PNV9_XSCOM_OCC_SIZE 0x8000
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2019-12-11 11:29:11 +03:00
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#define PNV9_XSCOM_PBA_BASE 0x5012b00
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#define PNV9_XSCOM_PBA_SIZE 0x40
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2019-03-08 01:35:35 +03:00
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#define PNV9_XSCOM_PSIHB_BASE 0x5012900
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#define PNV9_XSCOM_PSIHB_SIZE 0x100
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2019-03-06 11:50:11 +03:00
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#define PNV9_XSCOM_XIVE_BASE 0x5013000
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#define PNV9_XSCOM_XIVE_SIZE 0x300
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ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge
These changes introduces models for the PCIe Host Bridge (PHB4) of the
POWER9 processor. It includes the PowerBus logic interface (PBCQ),
IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI
and LSI interrupt sources as found on a POWER9 system using the XIVE
interrupt controller.
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs. By default,
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Each PEC has a set "global" registers and some "per-stack" (per-PHB)
registers. Those are organized in two XSCOM ranges, the "Nest" range
and the "PCI" range, each range contains both some "PEC" registers and
some "per-stack" registers.
No default device layout is provided and PCI devices can be added on
any of the available PCIe Root Port (pcie.0 .. 2 of a Power9 chip)
with address 0x0 as the firwware (skiboot) only accepts a single
device per root port. To run a simple system with a network and a
storage adapters, use a command line options such as :
-device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
-netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0
-device megasas,id=scsi0,bus=pcie.1,addr=0x0
-drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none
-device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2
If more are needed, include a bridge.
Multi chip is supported, each chip adding its set of PHB4 controllers
and its PCI busses. The model doesn't emulate the EEH error handling.
This model is not ready for hotplug yet.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[ clg: - numerous cleanups
- commit log
- fix for broken LSI support
- PHB pic printinfo
- large QOM rework ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200127144506.11132-2-clg@kaod.org>
[dwg: Use device_class_set_props()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-27 17:45:05 +03:00
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#define PNV9_XSCOM_PEC_NEST_BASE 0x4010c00
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#define PNV9_XSCOM_PEC_NEST_SIZE 0x100
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#define PNV9_XSCOM_PEC_PCI_BASE 0xd010800
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#define PNV9_XSCOM_PEC_PCI_SIZE 0x200
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/* XSCOM PCI "pass-through" window to PHB SCOM */
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#define PNV9_XSCOM_PEC_PCI_STK0 0x100
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#define PNV9_XSCOM_PEC_PCI_STK1 0x140
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#define PNV9_XSCOM_PEC_PCI_STK2 0x180
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2019-12-05 21:44:51 +03:00
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/*
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* Layout of the XSCOM PCB addresses (POWER 10)
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*/
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#define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2))
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#define PNV10_XSCOM_EQ(chiplet) ((chiplet) << 24)
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#define PNV10_XSCOM_EC(proc) \
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((0x2 << 16) | ((1 << (3 - (proc))) << 12))
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#define PNV10_XSCOM_EQ_BASE(core) \
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((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
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#define PNV10_XSCOM_EQ_SIZE 0x100000
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#define PNV10_XSCOM_EC_BASE(core) \
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((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
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#define PNV10_XSCOM_EC_SIZE 0x100000
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2019-12-05 21:44:53 +03:00
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#define PNV10_XSCOM_PSIHB_BASE 0x3011D00
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#define PNV10_XSCOM_PSIHB_SIZE 0x100
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ppc/pnv: Add a XIVE2 controller to the POWER10 chip
The XIVE2 interrupt controller of the POWER10 processor follows the
same logic than on POWER9 but the HW interface has been largely
reviewed. It has a new register interface, different BARs, extra
VSDs, new layout for the XIVE2 structures, and a set of new features
which are described below.
This is a model of the POWER10 XIVE2 interrupt controller for the
PowerNV machine. It focuses primarily on the needs of the skiboot
firmware but some initial hypervisor support is implemented for KVM
use (escalation).
Support for new features will be implemented in time and will require
new support from the OS.
* XIVE2 BARS
The interrupt controller BARs have a different layout outlined below.
Each sub-engine has now own its range and the indirect TIMA access was
replaced with a set of pages, one per CPU, under the IC BAR:
- IC BAR (Interrupt Controller)
. 4 pages, one per sub-engine
. 128 indirect TIMA pages
- TM BAR (Thread Interrupt Management Area)
. 4 pages
- ESB BAR (ESB pages for IPIs)
. up to 1TB
- END BAR (ESB pages for ENDs)
. up to 2TB
- NVC BAR (Notification Virtual Crowd)
. up to 128
- NVPG BAR (Notification Virtual Process and Group)
. up to 1TB
- Direct mapped Thread Context Area (reads & writes)
OPAL does not use the grouping and crowd capability.
* Virtual Structure Tables
XIVE2 adds new tables types and also changes the field layout of the END
and NVP Virtualization Structure Descriptors.
- EAS
- END new layout
- NVT was splitted in :
. NVP (Processor), 32B
. NVG (Group), 32B
. NVC (Crowd == P9 block group) 32B
- IC for remote configuration
- SYNC for cache injection
- ERQ for event input queue
The setup is slighly different on XIVE2 because the indexing has changed
for some of the tables, block ID or the chip topology ID can be used.
* XIVE2 features
SCOM and MMIO registers have a new layout and XIVE2 adds a new global
capability and configuration registers.
The lowlevel hardware offers a set of new features among which :
- a configurable number of priorities : 1 - 8
- StoreEOI with load-after-store ordering is activated by default
- Gen2 TIMA layout
- A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility
- increase to 24bit for VP number
Other features will have some impact on the Hypervisor and guest OS
when activated, but this is not required for initial support of the
controller.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02 08:51:38 +03:00
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#define PNV10_XSCOM_XIVE2_BASE 0x2010800
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#define PNV10_XSCOM_XIVE2_SIZE 0x400
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2019-12-13 14:59:34 +03:00
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void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
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2019-12-13 15:00:18 +03:00
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int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
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2019-12-13 15:00:24 +03:00
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uint64_t xscom_base, uint64_t xscom_size,
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const char *compat, int compat_size);
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2019-12-13 14:59:34 +03:00
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void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
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MemoryRegion *mr);
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void pnv_xscom_region_init(MemoryRegion *mr,
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2021-02-25 21:20:03 +03:00
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Object *owner,
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2019-12-13 14:59:34 +03:00
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const MemoryRegionOps *ops,
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void *opaque,
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const char *name,
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uint64_t size);
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ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 12:46:40 +03:00
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2019-03-15 17:51:21 +03:00
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#endif /* PPC_PNV_XSCOM_H */
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