2007-11-11 03:04:49 +03:00
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/*
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* ARMV7M System emulation.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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2011-06-23 04:59:26 +04:00
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* This code is licensed under the GPL.
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2007-11-11 03:04:49 +03:00
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*/
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2015-12-07 19:23:45 +03:00
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#include "qemu/osdep.h"
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2017-02-20 18:35:57 +03:00
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#include "hw/arm/armv7m.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
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#include "qapi/error.h"
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2016-01-19 23:51:44 +03:00
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#include "cpu.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/sysbus.h"
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2019-05-23 16:47:43 +03:00
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#include "hw/arm/boot.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/loader.h"
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2019-08-12 08:23:51 +03:00
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#include "hw/qdev-properties.h"
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2009-09-20 18:58:02 +04:00
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#include "elf.h"
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2013-07-29 20:36:59 +04:00
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#include "sysemu/qtest.h"
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2019-08-12 08:23:38 +03:00
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#include "sysemu/reset.h"
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2013-07-29 20:36:59 +04:00
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#include "qemu/error-report.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2017-02-20 18:35:59 +03:00
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#include "exec/address-spaces.h"
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2018-03-02 13:45:36 +03:00
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#include "target/arm/idau.h"
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2007-11-11 03:04:49 +03:00
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/* Bitbanded IO. Each word corresponds to a single bit. */
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2011-06-23 04:59:26 +04:00
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/* Get the byte address of the real memory for a bitband access. */
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2017-02-20 18:36:01 +03:00
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static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
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2007-11-11 03:04:49 +03:00
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{
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2017-02-20 18:36:01 +03:00
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return s->base | (offset & 0x1ffffff) >> 5;
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2007-11-11 03:04:49 +03:00
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}
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2017-02-20 18:36:01 +03:00
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static MemTxResult bitband_read(void *opaque, hwaddr offset,
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uint64_t *data, unsigned size, MemTxAttrs attrs)
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2007-11-11 03:04:49 +03:00
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{
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2017-02-20 18:36:01 +03:00
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BitBandState *s = opaque;
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uint8_t buf[4];
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MemTxResult res;
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int bitpos, bit;
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hwaddr addr;
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assert(size <= 4);
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/* Find address in underlying memory and round down to multiple of size */
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addr = bitband_addr(s, offset) & (-size);
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2017-09-21 11:51:08 +03:00
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res = address_space_read(&s->source_as, addr, attrs, buf, size);
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2017-02-20 18:36:01 +03:00
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if (res) {
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return res;
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}
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/* Bit position in the N bytes read... */
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bitpos = (offset >> 2) & ((size * 8) - 1);
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/* ...converted to byte in buffer and bit in byte */
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bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
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*data = bit;
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return MEMTX_OK;
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2007-11-11 03:04:49 +03:00
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}
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2017-02-20 18:36:01 +03:00
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static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size, MemTxAttrs attrs)
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2007-11-11 03:04:49 +03:00
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{
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2017-02-20 18:36:01 +03:00
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BitBandState *s = opaque;
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uint8_t buf[4];
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MemTxResult res;
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int bitpos, bit;
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hwaddr addr;
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assert(size <= 4);
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/* Find address in underlying memory and round down to multiple of size */
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addr = bitband_addr(s, offset) & (-size);
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2017-09-21 11:51:08 +03:00
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res = address_space_read(&s->source_as, addr, attrs, buf, size);
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2017-02-20 18:36:01 +03:00
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if (res) {
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return res;
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}
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/* Bit position in the N bytes read... */
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bitpos = (offset >> 2) & ((size * 8) - 1);
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/* ...converted to byte in buffer and bit in byte */
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bit = 1 << (bitpos & 7);
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if (value & 1) {
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buf[bitpos >> 3] |= bit;
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} else {
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buf[bitpos >> 3] &= ~bit;
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}
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2017-09-21 11:51:08 +03:00
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return address_space_write(&s->source_as, addr, attrs, buf, size);
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2007-11-11 03:04:49 +03:00
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}
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2011-08-15 18:17:20 +04:00
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static const MemoryRegionOps bitband_ops = {
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2017-02-20 18:36:01 +03:00
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.read_with_attrs = bitband_read,
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.write_with_attrs = bitband_write,
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2011-08-15 18:17:20 +04:00
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.endianness = DEVICE_NATIVE_ENDIAN,
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2017-02-20 18:36:01 +03:00
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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2007-11-11 03:04:49 +03:00
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};
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2016-03-07 10:05:42 +03:00
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static void bitband_init(Object *obj)
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2007-11-11 03:04:49 +03:00
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{
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2016-03-07 10:05:42 +03:00
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BitBandState *s = BITBAND(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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2007-11-11 03:04:49 +03:00
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2017-02-20 18:36:01 +03:00
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memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
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2013-06-07 05:25:08 +04:00
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"bitband", 0x02000000);
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2011-11-27 13:38:10 +04:00
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sysbus_init_mmio(dev, &s->iomem);
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2009-06-03 18:16:49 +04:00
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}
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2017-02-20 18:36:01 +03:00
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static void bitband_realize(DeviceState *dev, Error **errp)
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{
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BitBandState *s = BITBAND(dev);
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if (!s->source_memory) {
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error_setg(errp, "source-memory property not set");
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return;
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}
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2017-09-21 11:51:08 +03:00
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address_space_init(&s->source_as, s->source_memory, "bitband-source");
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2017-02-20 18:36:01 +03:00
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}
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2007-11-11 03:04:49 +03:00
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/* Board init. */
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2010-04-05 22:34:51 +04:00
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2017-02-20 18:35:57 +03:00
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static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
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0x20000000, 0x40000000
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};
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static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
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0x22000000, 0x42000000
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};
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static void armv7m_instance_init(Object *obj)
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{
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ARMv7MState *s = ARMV7M(obj);
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int i;
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/* Can't init the cpu here, we don't yet know which model to use */
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2017-02-20 18:35:59 +03:00
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memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
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2018-07-16 15:59:21 +03:00
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sysbus_init_child_obj(obj, "nvnic", &s->nvic, sizeof(s->nvic), TYPE_NVIC);
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2017-02-20 18:35:57 +03:00
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object_property_add_alias(obj, "num-irq",
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OBJECT(&s->nvic), "num-irq", &error_abort);
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for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
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2018-07-16 15:59:21 +03:00
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sysbus_init_child_obj(obj, "bitband[*]", &s->bitband[i],
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sizeof(s->bitband[i]), TYPE_BITBAND);
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2017-02-20 18:35:57 +03:00
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}
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}
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static void armv7m_realize(DeviceState *dev, Error **errp)
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{
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ARMv7MState *s = ARMV7M(dev);
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2017-02-20 18:36:00 +03:00
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SysBusDevice *sbd;
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2017-02-20 18:35:57 +03:00
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Error *err = NULL;
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int i;
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2017-02-20 18:35:59 +03:00
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if (!s->board_memory) {
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error_setg(errp, "memory property was not set");
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return;
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}
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memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
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2019-02-01 17:55:41 +03:00
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s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu",
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&err, NULL));
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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2017-02-20 18:35:57 +03:00
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2017-02-20 18:35:59 +03:00
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object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
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&error_abort);
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2018-03-02 13:45:36 +03:00
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if (object_property_find(OBJECT(s->cpu), "idau", NULL)) {
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object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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}
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2018-03-02 13:45:37 +03:00
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if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) {
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object_property_set_uint(OBJECT(s->cpu), s->init_svtor,
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"init-svtor", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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}
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2019-02-01 17:55:41 +03:00
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if (object_property_find(OBJECT(s->cpu), "start-powered-off", NULL)) {
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object_property_set_bool(OBJECT(s->cpu), s->start_powered_off,
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"start-powered-off", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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}
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2019-05-17 20:40:45 +03:00
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if (object_property_find(OBJECT(s->cpu), "vfp", NULL)) {
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object_property_set_bool(OBJECT(s->cpu), s->vfp,
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"vfp", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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}
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if (object_property_find(OBJECT(s->cpu), "dsp", NULL)) {
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object_property_set_bool(OBJECT(s->cpu), s->dsp,
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"dsp", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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}
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2018-06-15 16:57:13 +03:00
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2019-02-01 17:55:41 +03:00
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/*
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* Tell the CPU where the NVIC is; it will fail realize if it doesn't
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* have one. Similarly, tell the NVIC where its CPU is.
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2018-06-15 16:57:13 +03:00
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*/
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s->cpu->env.nvic = &s->nvic;
|
2019-02-01 17:55:41 +03:00
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s->nvic.cpu = s->cpu;
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2018-06-15 16:57:13 +03:00
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2017-02-20 18:35:57 +03:00
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object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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/* Note that we must realize the NVIC after the CPU */
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object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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/* Alias the NVIC's input and output GPIOs as our own so the board
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* code can wire them up. (We do this in realize because the
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* NVIC doesn't create the input GPIO array until realize.)
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*/
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qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
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qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
|
2018-08-20 13:24:33 +03:00
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qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
|
2017-02-20 18:35:57 +03:00
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|
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|
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/* Wire the NVIC up to the CPU */
|
2017-02-20 18:36:00 +03:00
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sbd = SYS_BUS_DEVICE(&s->nvic);
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|
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sysbus_connect_irq(sbd, 0,
|
2017-02-20 18:35:57 +03:00
|
|
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qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
|
|
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|
2017-02-20 18:36:00 +03:00
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memory_region_add_subregion(&s->container, 0xe000e000,
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|
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sysbus_mmio_get_region(sbd, 0));
|
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|
|
|
2018-08-16 16:05:28 +03:00
|
|
|
if (s->enable_bitband) {
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for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
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Object *obj = OBJECT(&s->bitband[i]);
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SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
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object_property_set_int(obj, bitband_input_addr[i], "base", &err);
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|
if (err != NULL) {
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|
error_propagate(errp, err);
|
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|
return;
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|
|
|
}
|
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object_property_set_link(obj, OBJECT(s->board_memory),
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|
|
"source-memory", &error_abort);
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|
|
object_property_set_bool(obj, true, "realized", &err);
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|
|
if (err != NULL) {
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|
|
error_propagate(errp, err);
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|
|
return;
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|
|
}
|
|
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|
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|
memory_region_add_subregion(&s->container, bitband_output_addr[i],
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|
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sysbus_mmio_get_region(sbd, 0));
|
2017-02-20 18:35:57 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static Property armv7m_properties[] = {
|
2017-09-13 19:04:57 +03:00
|
|
|
DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
|
2017-09-07 15:54:51 +03:00
|
|
|
DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
|
|
|
|
MemoryRegion *),
|
2018-03-02 13:45:36 +03:00
|
|
|
DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
|
2018-03-02 13:45:37 +03:00
|
|
|
DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
|
2018-08-16 16:05:28 +03:00
|
|
|
DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
|
2019-02-01 17:55:41 +03:00
|
|
|
DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off,
|
|
|
|
false),
|
2019-05-17 20:40:45 +03:00
|
|
|
DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
|
|
|
|
DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
|
2017-02-20 18:35:57 +03:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void armv7m_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->realize = armv7m_realize;
|
2020-01-10 18:30:32 +03:00
|
|
|
device_class_set_props(dc, armv7m_properties);
|
2017-02-20 18:35:57 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo armv7m_info = {
|
|
|
|
.name = TYPE_ARMV7M,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(ARMv7MState),
|
|
|
|
.instance_init = armv7m_instance_init,
|
|
|
|
.class_init = armv7m_class_init,
|
|
|
|
};
|
|
|
|
|
2010-04-05 22:34:51 +04:00
|
|
|
static void armv7m_reset(void *opaque)
|
|
|
|
{
|
2012-05-04 18:11:34 +04:00
|
|
|
ARMCPU *cpu = opaque;
|
|
|
|
|
|
|
|
cpu_reset(CPU(cpu));
|
2010-04-05 22:34:51 +04:00
|
|
|
}
|
|
|
|
|
2017-02-20 18:35:55 +03:00
|
|
|
void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
|
|
|
|
{
|
|
|
|
int image_size;
|
|
|
|
uint64_t entry;
|
|
|
|
uint64_t lowaddr;
|
|
|
|
int big_endian;
|
2018-03-02 13:45:36 +03:00
|
|
|
AddressSpace *as;
|
|
|
|
int asidx;
|
|
|
|
CPUState *cs = CPU(cpu);
|
2007-11-11 03:04:49 +03:00
|
|
|
|
2009-09-20 18:58:02 +04:00
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
|
big_endian = 1;
|
|
|
|
#else
|
|
|
|
big_endian = 0;
|
|
|
|
#endif
|
|
|
|
|
2018-03-02 13:45:36 +03:00
|
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
|
|
|
|
asidx = ARMASIdx_S;
|
|
|
|
} else {
|
|
|
|
asidx = ARMASIdx_NS;
|
|
|
|
}
|
|
|
|
as = cpu_get_address_space(cs, asidx);
|
|
|
|
|
2013-07-29 20:36:59 +04:00
|
|
|
if (kernel_filename) {
|
2019-01-15 15:18:03 +03:00
|
|
|
image_size = load_elf_as(kernel_filename, NULL, NULL, NULL,
|
2020-01-27 01:55:04 +03:00
|
|
|
&entry, &lowaddr, NULL,
|
2018-03-02 13:45:36 +03:00
|
|
|
NULL, big_endian, EM_ARM, 1, 0, as);
|
2013-07-29 20:36:59 +04:00
|
|
|
if (image_size < 0) {
|
2018-03-02 13:45:36 +03:00
|
|
|
image_size = load_image_targphys_as(kernel_filename, 0,
|
|
|
|
mem_size, as);
|
2013-07-29 20:36:59 +04:00
|
|
|
lowaddr = 0;
|
|
|
|
}
|
|
|
|
if (image_size < 0) {
|
|
|
|
error_report("Could not load kernel '%s'", kernel_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
2007-11-11 03:04:49 +03:00
|
|
|
}
|
|
|
|
|
2017-02-20 18:35:55 +03:00
|
|
|
/* CPU objects (unlike devices) are not automatically reset on system
|
|
|
|
* reset, so we must always register a handler to do so. Unlike
|
|
|
|
* A-profile CPUs, we don't need to do anything special in the
|
|
|
|
* handler to arrange that it starts correctly.
|
|
|
|
* This is arguably the wrong place to do this, but it matches the
|
|
|
|
* way A-profile does it. Note that this means that every M profile
|
|
|
|
* board must call this function!
|
|
|
|
*/
|
2012-05-04 18:11:34 +04:00
|
|
|
qemu_register_reset(armv7m_reset, cpu);
|
2007-11-11 03:04:49 +03:00
|
|
|
}
|
2009-06-03 18:16:49 +04:00
|
|
|
|
2012-01-24 23:12:29 +04:00
|
|
|
static Property bitband_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("base", BitBandState, base, 0),
|
2017-09-07 15:54:50 +03:00
|
|
|
DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
|
|
|
|
TYPE_MEMORY_REGION, MemoryRegion *),
|
2012-01-24 23:12:29 +04:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void bitband_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 23:12:29 +04:00
|
|
|
|
2017-02-20 18:36:01 +03:00
|
|
|
dc->realize = bitband_realize;
|
2020-01-10 18:30:32 +03:00
|
|
|
device_class_set_props(dc, bitband_properties);
|
2012-01-24 23:12:29 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo bitband_info = {
|
2013-07-24 02:46:43 +04:00
|
|
|
.name = TYPE_BITBAND,
|
2011-12-08 07:34:16 +04:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(BitBandState),
|
2016-03-07 10:05:42 +03:00
|
|
|
.instance_init = bitband_init,
|
2011-12-08 07:34:16 +04:00
|
|
|
.class_init = bitband_class_init,
|
2009-07-15 15:43:31 +04:00
|
|
|
};
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
static void armv7m_register_types(void)
|
2009-06-03 18:16:49 +04:00
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&bitband_info);
|
2017-02-20 18:35:57 +03:00
|
|
|
type_register_static(&armv7m_info);
|
2009-06-03 18:16:49 +04:00
|
|
|
}
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
type_init(armv7m_register_types)
|