2008-07-23 23:17:46 +04:00
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-06-29 12:14:47 +03:00
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#ifndef PPC_TCG_TARGET_H
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#define PPC_TCG_TARGET_H
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2008-07-23 23:17:46 +04:00
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2014-04-30 22:39:20 +04:00
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#ifdef _ARCH_PPC64
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# define TCG_TARGET_REG_BITS 64
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#else
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# define TCG_TARGET_REG_BITS 32
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#endif
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2008-07-23 23:17:46 +04:00
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#define TCG_TARGET_NB_REGS 32
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2014-03-29 01:58:38 +04:00
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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2015-05-05 10:18:22 +03:00
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
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2008-07-23 23:17:46 +04:00
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2011-11-09 12:03:33 +04:00
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typedef enum {
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2014-03-25 19:06:43 +04:00
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TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3,
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TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7,
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TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11,
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TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15,
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TCG_REG_R16, TCG_REG_R17, TCG_REG_R18, TCG_REG_R19,
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TCG_REG_R20, TCG_REG_R21, TCG_REG_R22, TCG_REG_R23,
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TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27,
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TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31,
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TCG_REG_CALL_STACK = TCG_REG_R1,
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TCG_AREG0 = TCG_REG_R27
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2011-11-09 12:03:33 +04:00
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} TCGReg;
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2008-07-23 23:17:46 +04:00
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2013-02-02 11:43:42 +04:00
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/* optional instructions automatically implemented */
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#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
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#define TCG_TARGET_HAS_ext16u_i32 0
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2008-07-23 23:17:46 +04:00
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/* optional instructions */
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2011-08-18 01:11:46 +04:00
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#define TCG_TARGET_HAS_div_i32 1
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2013-03-12 10:24:55 +04:00
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#define TCG_TARGET_HAS_rem_i32 0
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2013-01-31 07:24:06 +04:00
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#define TCG_TARGET_HAS_rot_i32 1
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2011-08-18 01:11:46 +04:00
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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2013-01-31 09:16:38 +04:00
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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2011-08-22 14:40:00 +04:00
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#define TCG_TARGET_HAS_not_i32 1
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2011-08-18 01:11:46 +04:00
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#define TCG_TARGET_HAS_neg_i32 1
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2013-01-31 19:49:13 +04:00
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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#define TCG_TARGET_HAS_eqv_i32 1
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#define TCG_TARGET_HAS_nand_i32 1
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#define TCG_TARGET_HAS_nor_i32 1
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2013-01-31 20:39:30 +04:00
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#define TCG_TARGET_HAS_deposit_i32 1
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2016-10-14 20:04:32 +03:00
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#define TCG_TARGET_HAS_extract_i32 0
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#define TCG_TARGET_HAS_sextract_i32 0
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2013-02-02 01:00:05 +04:00
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#define TCG_TARGET_HAS_movcond_i32 1
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2013-02-20 11:51:49 +04:00
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#define TCG_TARGET_HAS_mulu2_i32 0
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2013-02-20 11:51:53 +04:00
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#define TCG_TARGET_HAS_muls2_i32 0
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2014-04-30 22:55:34 +04:00
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#define TCG_TARGET_HAS_muluh_i32 1
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2014-03-26 22:37:06 +04:00
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#define TCG_TARGET_HAS_mulsh_i32 1
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2010-02-19 01:44:39 +03:00
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2014-04-30 22:39:20 +04:00
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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2015-07-24 17:16:00 +03:00
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#define TCG_TARGET_HAS_extrl_i64_i32 0
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#define TCG_TARGET_HAS_extrh_i64_i32 0
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2011-08-18 01:11:46 +04:00
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#define TCG_TARGET_HAS_div_i64 1
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2013-03-12 10:24:55 +04:00
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#define TCG_TARGET_HAS_rem_i64 0
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2013-01-31 07:24:06 +04:00
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#define TCG_TARGET_HAS_rot_i64 1
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2011-08-18 01:11:46 +04:00
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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2014-04-30 22:39:20 +04:00
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#define TCG_TARGET_HAS_ext8u_i64 0
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#define TCG_TARGET_HAS_ext16u_i64 0
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#define TCG_TARGET_HAS_ext32u_i64 0
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2013-01-31 09:16:38 +04:00
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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2013-01-31 09:41:54 +04:00
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#define TCG_TARGET_HAS_bswap64_i64 1
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2011-08-22 14:40:00 +04:00
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#define TCG_TARGET_HAS_not_i64 1
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2011-08-18 01:11:46 +04:00
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#define TCG_TARGET_HAS_neg_i64 1
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2013-01-31 19:49:13 +04:00
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#define TCG_TARGET_HAS_andc_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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#define TCG_TARGET_HAS_eqv_i64 1
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#define TCG_TARGET_HAS_nand_i64 1
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#define TCG_TARGET_HAS_nor_i64 1
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2013-01-31 20:39:30 +04:00
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#define TCG_TARGET_HAS_deposit_i64 1
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2016-10-14 20:04:32 +03:00
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#define TCG_TARGET_HAS_extract_i64 0
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#define TCG_TARGET_HAS_sextract_i64 0
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2013-02-02 01:00:05 +04:00
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#define TCG_TARGET_HAS_movcond_i64 1
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2013-03-05 02:26:52 +04:00
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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2013-08-15 01:46:08 +04:00
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#define TCG_TARGET_HAS_mulu2_i64 0
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 1
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2014-04-30 22:39:20 +04:00
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#endif
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2008-07-23 23:17:46 +04:00
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2014-05-01 00:56:50 +04:00
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void flush_icache_range(uintptr_t start, uintptr_t stop);
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2012-12-06 15:15:58 +04:00
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#endif
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