mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

tcg-ppc64: Implement muluh, mulsh

Browse Source 
Using these instead of mulu2 and muls2 lets us avoid having to argument
overlap analysis in the backend.  Normal register allocation will DTRT.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-08-14 14:46:08 -07:00
parent 3c9a8f1756
commit 32f5717f07
2 changed files with 11 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
tcg/ppc64/tcg-target.c
View File

@ -1975,29 +1975,11 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
}
break;
case INDEX_op_mulu2_i64:
case INDEX_op_muls2_i64:
{
int oph = (opc == INDEX_op_mulu2_i64 ? MULHDU : MULHD);
TCGReg outl = args[0], outh = args[1];
a0 = args[2], a1 = args[3];
if (outl == a0 || outl == a1) {
if (outh == a0 || outh == a1) {
outl = TCG_REG_R0;
} else {
tcg_out32(s, oph | TAB(outh, a0, a1));
oph = 0;
}
}
tcg_out32(s, MULLD | TAB(outl, a0, a1));
if (oph != 0) {
tcg_out32(s, oph | TAB(outh, a0, a1));
}
if (outl != args[0]) {
tcg_out_mov(s, TCG_TYPE_I64, args[0], outl);
}
}
case INDEX_op_muluh_i64:
tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_mulsh_i64:
tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
break;
default:
@ -2124,8 +2106,8 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
{ INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },
{ INDEX_op_muls2_i64, { "r", "r", "r", "r" } },
{ INDEX_op_mulu2_i64, { "r", "r", "r", "r" } },
{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
{ INDEX_op_muluh_i64, { "r", "r", "r" } },
{ -1 },
};

8
tcg/ppc64/tcg-target.h
View File

@ -118,10 +118,10 @@ typedef enum {
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muls2_i64 1
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_AREG0 TCG_REG_R27