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qemu/target/xtensa/exc_helper.c

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target/xtensa: extract interrupt and exception helpers Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-14 06:51:54 +03:00
/*
* Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qemu/osdep.h"
exec/exec-all: Move 'qemu/log.h' include in units requiring it Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core component and shouldn't be used that way. Move the "qemu/log.h" inclusion locally to each unit requiring it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220207082756.82600-10-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-07 11:27:56 +03:00
#include "qemu/log.h"
target/xtensa: extract interrupt and exception helpers Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-14 06:51:54 +03:00
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
target/xtensa: Include missing 'qemu/atomic.h' header Since commit fa92bd4af7 ("target/xtensa: fix access to the INTERRUPT SR") these files use QEMU atomic API. Explicit the header inclusion instead of relying on implicit and indirect inclusion. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-10-philmd@linaro.org>
2023-08-29 00:41:49 +03:00
#include "qemu/atomic.h"
target/xtensa: extract interrupt and exception helpers Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-14 06:51:54 +03:00
#include "exec/exec-all.h"
void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
{
target/xtensa: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace xtensa_env_get_cpu with env_archcpu. The combination CPU(xtensa_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h" so that the definition of env_cpu is available. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-23 05:52:17 +03:00
CPUState *cs = env_cpu(env);
target/xtensa: extract interrupt and exception helpers Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-14 06:51:54 +03:00
cs->exception_index = excp;
if (excp == EXCP_YIELD) {
env->yield_needed = 0;
}
cpu_loop_exit(cs);
}
void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
{
uint32_t vector;
env->pc = pc;
if (env->sregs[PS] & PS_EXCM) {
if (env->config->ndepc) {
env->sregs[DEPC] = pc;
} else {
env->sregs[EPC1] = pc;
}
vector = EXC_DOUBLE;
} else {
env->sregs[EPC1] = pc;
vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
}
env->sregs[EXCCAUSE] = cause;
env->sregs[PS] |= PS_EXCM;
HELPER(exception)(env, vector);
}
void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
uint32_t pc, uint32_t cause, uint32_t vaddr)
{
env->sregs[EXCVADDR] = vaddr;
HELPER(exception_cause)(env, pc, cause);
}
void debug_exception_env(CPUXtensaState *env, uint32_t cause)
{
if (xtensa_get_cintlevel(env) < env->config->debug_level) {
HELPER(debug_exception)(env, env->pc, cause);
}
}
void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
{
unsigned level = env->config->debug_level;
env->pc = pc;
env->sregs[DEBUGCAUSE] = cause;
env->sregs[EPC1 + level - 1] = pc;
env->sregs[EPS2 + level - 2] = env->sregs[PS];
env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
(level << PS_INTLEVEL_SHIFT);
HELPER(exception)(env, EXC_DEBUG);
}
#ifndef CONFIG_USER_ONLY
void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
{
target/xtensa: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace xtensa_env_get_cpu with env_archcpu. The combination CPU(xtensa_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h" so that the definition of env_cpu is available. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-23 05:52:17 +03:00
CPUState *cpu = env_cpu(env);
target/xtensa: extract interrupt and exception helpers Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-14 06:51:54 +03:00
env->pc = pc;
env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
(intlevel << PS_INTLEVEL_SHIFT);
qemu_mutex_lock_iothread();
check_interrupts(env);
qemu_mutex_unlock_iothread();
if (env->pending_irq_level) {
target/xtensa: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace xtensa_env_get_cpu with env_archcpu. The combination CPU(xtensa_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h" so that the definition of env_cpu is available. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-23 05:52:17 +03:00
cpu_loop_exit(cpu);
target/xtensa: extract interrupt and exception helpers Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-14 06:51:54 +03:00
return;
}
cpu->halted = 1;
HELPER(exception)(env, EXCP_HLT);
}
void HELPER(check_interrupts)(CPUXtensaState *env)
{
qemu_mutex_lock_iothread();
check_interrupts(env);
qemu_mutex_unlock_iothread();
}
target/xtensa: fix access to the INTERRUPT SR INTERRUPT special register may be changed both by the core (by writing to INTSET and INTCLEAR registers) and by external events (by triggering and clearing HW IRQs). In MTTCG this state must be protected from concurrent access, otherwise interrupts may be lost or spurious interrupts may be detected. Use atomic operations to change INTSET SR. Fix wsr.intset so that it soesn't clear any bits. Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-24 06:26:52 +03:00
void HELPER(intset)(CPUXtensaState *env, uint32_t v)
{
qemu/atomic.h: rename atomic_ to qatomic_ clang's C11 atomic_fetch_*() functions only take a C11 atomic type pointer argument. QEMU uses direct types (int, etc) and this causes a compiler error when a QEMU code calls these functions in a source file that also included <stdatomic.h> via a system header file: $ CC=clang CXX=clang++ ./configure ... && make ../util/async.c:79:17: error: address argument to atomic operation must be a pointer to _Atomic type ('unsigned int *' invalid) Avoid using atomic_*() names in QEMU's atomic.h since that namespace is used by <stdatomic.h>. Prefix QEMU's APIs with 'q' so that atomic.h and <stdatomic.h> can co-exist. I checked /usr/include on my machine and searched GitHub for existing "qatomic_" users but there seem to be none. This patch was generated using: $ git grep -h -o '\<atomic\(64\)\?_[a-z0-9_]\+' include/qemu/atomic.h | \ sort -u >/tmp/changed_identifiers $ for identifier in $(</tmp/changed_identifiers); do sed -i "s%\<$identifier\>%q$identifier%g" \ $(git grep -I -l "\<$identifier\>") done I manually fixed line-wrap issues and misaligned rST tables. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200923105646.47864-1-stefanha@redhat.com>
2020-09-23 13:56:46 +03:00
qatomic_or(&env->sregs[INTSET],
target/xtensa: fix access to the INTERRUPT SR INTERRUPT special register may be changed both by the core (by writing to INTSET and INTCLEAR registers) and by external events (by triggering and clearing HW IRQs). In MTTCG this state must be protected from concurrent access, otherwise interrupts may be lost or spurious interrupts may be detected. Use atomic operations to change INTSET SR. Fix wsr.intset so that it soesn't clear any bits. Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-24 06:26:52 +03:00
v & env->config->inttype_mask[INTTYPE_SOFTWARE]);
}
target/xtensa: implement NMI support When NMI is configured it is taken regardless of INTENABLE SR contents, PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken. Add nmi_level to XtensaConfig, puth there NMI level from the overlay or XCHAL_NUM_INTLEVELS + 1 when NMI is not configured. Add NMI mask to INTENABLE SR and limit CINTLEVEL to nmi_level - 1 when determining pending IRQ level in check_interrupt(). Always take and clear pending interrupt at nmi_level in the handle_interrupt(). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-06 03:31:59 +03:00
static void intclear(CPUXtensaState *env, uint32_t v)
{
qemu/atomic.h: rename atomic_ to qatomic_ clang's C11 atomic_fetch_*() functions only take a C11 atomic type pointer argument. QEMU uses direct types (int, etc) and this causes a compiler error when a QEMU code calls these functions in a source file that also included <stdatomic.h> via a system header file: $ CC=clang CXX=clang++ ./configure ... && make ../util/async.c:79:17: error: address argument to atomic operation must be a pointer to _Atomic type ('unsigned int *' invalid) Avoid using atomic_*() names in QEMU's atomic.h since that namespace is used by <stdatomic.h>. Prefix QEMU's APIs with 'q' so that atomic.h and <stdatomic.h> can co-exist. I checked /usr/include on my machine and searched GitHub for existing "qatomic_" users but there seem to be none. This patch was generated using: $ git grep -h -o '\<atomic\(64\)\?_[a-z0-9_]\+' include/qemu/atomic.h | \ sort -u >/tmp/changed_identifiers $ for identifier in $(</tmp/changed_identifiers); do sed -i "s%\<$identifier\>%q$identifier%g" \ $(git grep -I -l "\<$identifier\>") done I manually fixed line-wrap issues and misaligned rST tables. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200923105646.47864-1-stefanha@redhat.com>
2020-09-23 13:56:46 +03:00
qatomic_and(&env->sregs[INTSET], ~v);
target/xtensa: implement NMI support When NMI is configured it is taken regardless of INTENABLE SR contents, PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken. Add nmi_level to XtensaConfig, puth there NMI level from the overlay or XCHAL_NUM_INTLEVELS + 1 when NMI is not configured. Add NMI mask to INTENABLE SR and limit CINTLEVEL to nmi_level - 1 when determining pending IRQ level in check_interrupt(). Always take and clear pending interrupt at nmi_level in the handle_interrupt(). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-06 03:31:59 +03:00
}
target/xtensa: fix access to the INTERRUPT SR INTERRUPT special register may be changed both by the core (by writing to INTSET and INTCLEAR registers) and by external events (by triggering and clearing HW IRQs). In MTTCG this state must be protected from concurrent access, otherwise interrupts may be lost or spurious interrupts may be detected. Use atomic operations to change INTSET SR. Fix wsr.intset so that it soesn't clear any bits. Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-24 06:26:52 +03:00
void HELPER(intclear)(CPUXtensaState *env, uint32_t v)
{
target/xtensa: implement NMI support When NMI is configured it is taken regardless of INTENABLE SR contents, PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken. Add nmi_level to XtensaConfig, puth there NMI level from the overlay or XCHAL_NUM_INTLEVELS + 1 when NMI is not configured. Add NMI mask to INTENABLE SR and limit CINTLEVEL to nmi_level - 1 when determining pending IRQ level in check_interrupt(). Always take and clear pending interrupt at nmi_level in the handle_interrupt(). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-06 03:31:59 +03:00
intclear(env, v & (env->config->inttype_mask[INTTYPE_SOFTWARE] |
env->config->inttype_mask[INTTYPE_EDGE]));
target/xtensa: fix access to the INTERRUPT SR INTERRUPT special register may be changed both by the core (by writing to INTSET and INTCLEAR registers) and by external events (by triggering and clearing HW IRQs). In MTTCG this state must be protected from concurrent access, otherwise interrupts may be lost or spurious interrupts may be detected. Use atomic operations to change INTSET SR. Fix wsr.intset so that it soesn't clear any bits. Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-24 06:26:52 +03:00
}
target/xtensa: extract interrupt and exception helpers Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-14 06:51:54 +03:00
static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
{
if (xtensa_option_enabled(env->config,
XTENSA_OPTION_RELOCATABLE_VECTOR)) {
return vector - env->config->vecbase + env->sregs[VECBASE];
} else {
return vector;
}
}
/*!
* Handle penging IRQ.
* For the high priority interrupt jump to the corresponding interrupt vector.
* For the level-1 interrupt convert it to either user, kernel or double
* exception with the 'level-1 interrupt' exception cause.
*/
static void handle_interrupt(CPUXtensaState *env)
{
int level = env->pending_irq_level;
target/xtensa: implement NMI support When NMI is configured it is taken regardless of INTENABLE SR contents, PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken. Add nmi_level to XtensaConfig, puth there NMI level from the overlay or XCHAL_NUM_INTLEVELS + 1 when NMI is not configured. Add NMI mask to INTENABLE SR and limit CINTLEVEL to nmi_level - 1 when determining pending IRQ level in check_interrupt(). Always take and clear pending interrupt at nmi_level in the handle_interrupt(). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-06 03:31:59 +03:00
if ((level > xtensa_get_cintlevel(env) &&
level <= env->config->nlevel &&
(env->config->level_mask[level] &
env->sregs[INTSET] & env->sregs[INTENABLE])) ||
level == env->config->nmi_level) {
target/xtensa: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace xtensa_env_get_cpu with env_archcpu. The combination CPU(xtensa_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h" so that the definition of env_cpu is available. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-23 05:52:17 +03:00
CPUState *cs = env_cpu(env);
target/xtensa: extract interrupt and exception helpers Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-14 06:51:54 +03:00
if (level > 1) {
target/xtensa: Assert that interrupt level is within bounds In handle_interrupt() we use level as an index into the interrupt_vector[] array. This is safe because we have checked it against env->config->nlevel, but Coverity can't see that (and it is only true because each CPU config sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it complains about a possible array overrun (CID 1507131) Add an assert() which will make Coverity happy and catch the unlikely case of a mis-set XCHAL_NUM_INTLEVELS in future. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org
2023-06-23 18:41:35 +03:00
/* env->config->nlevel check should have ensured this */
assert(level < sizeof(env->config->interrupt_vector));
target/xtensa: extract interrupt and exception helpers Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-14 06:51:54 +03:00
env->sregs[EPC1 + level - 1] = env->pc;
env->sregs[EPS2 + level - 2] = env->sregs[PS];
env->sregs[PS] =
(env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
env->pc = relocated_vector(env,
env->config->interrupt_vector[level]);
target/xtensa: implement NMI support When NMI is configured it is taken regardless of INTENABLE SR contents, PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken. Add nmi_level to XtensaConfig, puth there NMI level from the overlay or XCHAL_NUM_INTLEVELS + 1 when NMI is not configured. Add NMI mask to INTENABLE SR and limit CINTLEVEL to nmi_level - 1 when determining pending IRQ level in check_interrupt(). Always take and clear pending interrupt at nmi_level in the handle_interrupt(). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-06 03:31:59 +03:00
if (level == env->config->nmi_level) {
intclear(env, env->config->inttype_mask[INTTYPE_NMI]);
}
target/xtensa: extract interrupt and exception helpers Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-14 06:51:54 +03:00
} else {
env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
if (env->sregs[PS] & PS_EXCM) {
if (env->config->ndepc) {
env->sregs[DEPC] = env->pc;
} else {
env->sregs[EPC1] = env->pc;
}
cs->exception_index = EXC_DOUBLE;
} else {
env->sregs[EPC1] = env->pc;
cs->exception_index =
(env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
}
env->sregs[PS] |= PS_EXCM;
}
}
}
/* Called from cpu_handle_interrupt with BQL held */
void xtensa_cpu_do_interrupt(CPUState *cs)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
if (cs->exception_index == EXC_IRQ) {
qemu_log_mask(CPU_LOG_INT,
"%s(EXC_IRQ) level = %d, cintlevel = %d, "
"pc = %08x, a0 = %08x, ps = %08x, "
"intset = %08x, intenable = %08x, "
"ccount = %08x\n",
__func__, env->pending_irq_level,
xtensa_get_cintlevel(env),
env->pc, env->regs[0], env->sregs[PS],
env->sregs[INTSET], env->sregs[INTENABLE],
env->sregs[CCOUNT]);
handle_interrupt(env);
}
switch (cs->exception_index) {
case EXC_WINDOW_OVERFLOW4:
case EXC_WINDOW_UNDERFLOW4:
case EXC_WINDOW_OVERFLOW8:
case EXC_WINDOW_UNDERFLOW8:
case EXC_WINDOW_OVERFLOW12:
case EXC_WINDOW_UNDERFLOW12:
case EXC_KERNEL:
case EXC_USER:
case EXC_DOUBLE:
case EXC_DEBUG:
qemu_log_mask(CPU_LOG_INT, "%s(%d) "
"pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
__func__, cs->exception_index,
env->pc, env->regs[0], env->sregs[PS],
env->sregs[CCOUNT]);
if (env->config->exception_vector[cs->exception_index]) {
uint32_t vector;
vector = env->config->exception_vector[cs->exception_index];
env->pc = relocated_vector(env, vector);
} else {
qemu_log_mask(CPU_LOG_INT,
"%s(pc = %08x) bad exception_index: %d\n",
__func__, env->pc, cs->exception_index);
}
break;
case EXC_IRQ:
break;
default:
qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
__func__, env->pc, cs->exception_index);
break;
}
check_interrupts(env);
}
bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
cs->exception_index = EXC_IRQ;
xtensa_cpu_do_interrupt(cs);
return true;
}
return false;
}
target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210911165434.531552-23-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-11 19:54:32 +03:00
#endif /* !CONFIG_USER_ONLY */
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