2012-12-06 15:15:58 +04:00
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#ifndef HW_ESCC_H
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2016-06-29 16:29:06 +03:00
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#define HW_ESCC_H
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2012-12-06 15:15:58 +04:00
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2018-02-14 09:35:58 +03:00
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#include "chardev/char-fe.h"
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#include "chardev/char-serial.h"
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2019-08-12 08:23:31 +03:00
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#include "hw/sysbus.h"
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2018-02-14 09:35:58 +03:00
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#include "ui/input.h"
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2009-01-12 20:38:28 +03:00
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/* escc.c */
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2013-07-24 23:30:40 +04:00
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#define TYPE_ESCC "escc"
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2009-01-12 20:38:28 +03:00
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#define ESCC_SIZE 4
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2018-02-14 09:35:58 +03:00
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#define ESCC(obj) OBJECT_CHECK(ESCCState, (obj), TYPE_ESCC)
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typedef enum {
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escc_chn_a, escc_chn_b,
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} ESCCChnID;
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typedef enum {
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escc_serial, escc_kbd, escc_mouse,
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} ESCCChnType;
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#define ESCC_SERIO_QUEUE_SIZE 256
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typedef struct {
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uint8_t data[ESCC_SERIO_QUEUE_SIZE];
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int rptr, wptr, count;
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} ESCCSERIOQueue;
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#define ESCC_SERIAL_REGS 16
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typedef struct ESCCChannelState {
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qemu_irq irq;
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uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
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struct ESCCChannelState *otherchn;
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uint32_t reg;
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uint8_t wregs[ESCC_SERIAL_REGS], rregs[ESCC_SERIAL_REGS];
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ESCCSERIOQueue queue;
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CharBackend chr;
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int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
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int disabled;
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int clock;
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uint32_t vmstate_dummy;
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ESCCChnID chn; /* this channel, A (base+4) or B (base+0) */
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ESCCChnType type;
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uint8_t rx, tx;
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QemuInputHandlerState *hs;
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} ESCCChannelState;
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typedef struct ESCCState {
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SysBusDevice parent_obj;
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struct ESCCChannelState chn[2];
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uint32_t it_shift;
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2019-05-26 01:50:04 +03:00
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bool bit_swap;
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2018-02-14 09:35:58 +03:00
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MemoryRegion mmio;
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uint32_t disabled;
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uint32_t frequency;
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} ESCCState;
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2012-12-06 15:15:58 +04:00
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#endif
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