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qemu/include/hw/arm/xlnx-zynqmp.h

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arm: Introduce Xilinx ZynqMP SoC With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:22:58 +03:00
/*
* Xilinx Zynq MPSoC emulation
*
* Copyright (C) 2015 Xilinx Inc
* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef XLNX_ZYNQMP_H
#include "qemu-common.h"
#include "hw/arm/arm.h"
arm: xlnx-zynqmp: Add GIC Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:23:01 +03:00
#include "hw/intc/arm_gic.h"
arm: xlnx-zynqmp: Add GEM support There are 4x Cadence GEMs in ZynqMP. Add them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:23:12 +03:00
#include "hw/net/cadence_gem.h"
arm: xlnx-zynqmp: Add UART support There are 2x Cadence UARTs in Zynq MP. Add them. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:23:21 +03:00
#include "hw/char/cadence_uart.h"
xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP Connect the Sysbus AHCI device to ZynqMP. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com> [PMM: removed unnecessary brackets in error_propagate call] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-08 19:38:45 +03:00
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
target-arm: xlnx-zynqmp: Add sdhci support. Add two SYSBUS_SDHCI devices for xlnx-zynqmp Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-10-08 16:21:03 +03:00
#include "hw/sd/sdhci.h"
xlnx-zynqmp: Connect the SPI devices Connect the Xilinx SPI devices to the ZynqMP model. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [ PC changes * Use QOM alias for bus connectivity on SoC level ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [PMM: free the g_strdup_printf() string when finished with it] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21 17:15:03 +03:00
#include "hw/ssi/xilinx_spips.h"
arm: Introduce Xilinx ZynqMP SoC With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:22:58 +03:00
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
TYPE_XLNX_ZYNQMP)
arm: xlnx-zynqmp: Preface CPU variables with "apu" The CPUs currently supported by zynqmp are the APU (application processing unit) CPUs. There are other CPUs in Zynqmp so unqualified "cpus" in ambiguous. Preface the variables with "APU" accordingly, to prepare support adding the RPU (realtime processing unit) processors. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: ce32287fc365aea898465e981da3546a227e0811.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19 16:17:45 +03:00
#define XLNX_ZYNQMP_NUM_APU_CPUS 4
arm: xlnx-zynqmp: Add 2xCortexR5 CPUs Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset (this is true of real hardware) by default or selectable as the boot processor. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: da34128c73ca13fc4f8c3293e1a33d1e1e345655.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19 16:17:45 +03:00
#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
arm: xlnx-zynqmp: Add GEM support There are 4x Cadence GEMs in ZynqMP. Add them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:23:12 +03:00
#define XLNX_ZYNQMP_NUM_GEMS 4
arm: xlnx-zynqmp: Add UART support There are 2x Cadence UARTs in Zynq MP. Add them. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:23:21 +03:00
#define XLNX_ZYNQMP_NUM_UARTS 2
target-arm: xlnx-zynqmp: Add sdhci support. Add two SYSBUS_SDHCI devices for xlnx-zynqmp Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-10-08 16:21:03 +03:00
#define XLNX_ZYNQMP_NUM_SDHCI 2
xlnx-zynqmp: Connect the SPI devices Connect the Xilinx SPI devices to the ZynqMP model. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [ PC changes * Use QOM alias for bus connectivity on SoC level ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [PMM: free the g_strdup_printf() string when finished with it] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21 17:15:03 +03:00
#define XLNX_ZYNQMP_NUM_SPIS 2
arm: Introduce Xilinx ZynqMP SoC With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:22:58 +03:00
xlnx-zynqmp: Connect the four OCM banks The Xilinx EP108 has four separate OCM banks which are located adjacent to each other. This patch adds the four banks to the ZynqMP SoC. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: afa6ba31163a5d541a0bef4b0dc11f2597e0c495.1436813543.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-25 17:45:06 +03:00
#define XLNX_ZYNQMP_NUM_OCM_BANKS 4
#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
arm: xlnx-zynqmp: Add GIC Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:23:01 +03:00
#define XLNX_ZYNQMP_GIC_REGIONS 2
/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
* and under-decodes the 64k region. This mirrors the 4k regions to every 4k
* aligned address in the 64k region. To implement each GIC region needs a
* number of memory region aliases.
*/
arm: xlnx-zynqmp: Fix up GIC region size The GIC in ZynqMP cover a 64K address space, however the actual registers are decoded within a 4K address space and mirrored at the 4K boundaries. This change fixes the defined size for these regions as it was set to 0x4000/16K incorrectly. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1441719672-25296-1-git-send-email-nathan@nathanrossi.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14 16:39:47 +03:00
#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
arm: xlnx-zynqmp: Add GIC Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:23:01 +03:00
#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
xlnx-zynqmp: Add support for high DDR memory regions The Xilinx ZynqMP SoC and EP108 board supports three memory regions: - A 2GB region starting at 0 - A 32GB region starting at 32GB - A 256GB region starting at 768GB This patch adds support for the first two memory regions, which is automatically created based on the size specified by the QEMU memory command line argument. On hardware the physical memory region is one continuous region, it is then mapped into the three different regions by the DDRC. As we don't model the DDRC this is done at startup by QEMU. The board creates the memory region and then passes that memory region to the SoC. The SoC then maps the memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: a1e47db941d65733724a300fcd98b74fbeeaaf22.1452637205.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-13 01:39:18 +03:00
#define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull
#define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull
#define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull
#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
arm: Introduce Xilinx ZynqMP SoC With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:22:58 +03:00
typedef struct XlnxZynqMPState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
arm: xlnx-zynqmp: Preface CPU variables with "apu" The CPUs currently supported by zynqmp are the APU (application processing unit) CPUs. There are other CPUs in Zynqmp so unqualified "cpus" in ambiguous. Preface the variables with "APU" accordingly, to prepare support adding the RPU (realtime processing unit) processors. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: ce32287fc365aea898465e981da3546a227e0811.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19 16:17:45 +03:00
ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
arm: xlnx-zynqmp: Add 2xCortexR5 CPUs Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset (this is true of real hardware) by default or selectable as the boot processor. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: da34128c73ca13fc4f8c3293e1a33d1e1e345655.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19 16:17:45 +03:00
ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
arm: xlnx-zynqmp: Add GIC Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:23:01 +03:00
GICState gic;
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
xlnx-zynqmp: Add support for high DDR memory regions The Xilinx ZynqMP SoC and EP108 board supports three memory regions: - A 2GB region starting at 0 - A 32GB region starting at 32GB - A 256GB region starting at 768GB This patch adds support for the first two memory regions, which is automatically created based on the size specified by the QEMU memory command line argument. On hardware the physical memory region is one continuous region, it is then mapped into the three different regions by the DDRC. As we don't model the DDRC this is done at startup by QEMU. The board creates the memory region and then passes that memory region to the SoC. The SoC then maps the memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: a1e47db941d65733724a300fcd98b74fbeeaaf22.1452637205.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-13 01:39:18 +03:00
xlnx-zynqmp: Connect the four OCM banks The Xilinx EP108 has four separate OCM banks which are located adjacent to each other. This patch adds the four banks to the ZynqMP SoC. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: afa6ba31163a5d541a0bef4b0dc11f2597e0c495.1436813543.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-25 17:45:06 +03:00
MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
xlnx-zynqmp: Add support for high DDR memory regions The Xilinx ZynqMP SoC and EP108 board supports three memory regions: - A 2GB region starting at 0 - A 32GB region starting at 32GB - A 256GB region starting at 768GB This patch adds support for the first two memory regions, which is automatically created based on the size specified by the QEMU memory command line argument. On hardware the physical memory region is one continuous region, it is then mapped into the three different regions by the DDRC. As we don't model the DDRC this is done at startup by QEMU. The board creates the memory region and then passes that memory region to the SoC. The SoC then maps the memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: a1e47db941d65733724a300fcd98b74fbeeaaf22.1452637205.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-13 01:39:18 +03:00
MemoryRegion *ddr_ram;
MemoryRegion ddr_ram_low, ddr_ram_high;
arm: xlnx-zynqmp: Add GEM support There are 4x Cadence GEMs in ZynqMP. Add them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:23:12 +03:00
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
arm: xlnx-zynqmp: Add UART support There are 2x Cadence UARTs in Zynq MP. Add them. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:23:21 +03:00
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP Connect the Sysbus AHCI device to ZynqMP. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com> [PMM: removed unnecessary brackets in error_propagate call] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-08 19:38:45 +03:00
SysbusAHCIState sata;
target-arm: xlnx-zynqmp: Add sdhci support. Add two SYSBUS_SDHCI devices for xlnx-zynqmp Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-10-08 16:21:03 +03:00
SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
xlnx-zynqmp: Connect the SPI devices Connect the Xilinx SPI devices to the ZynqMP model. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [ PC changes * Use QOM alias for bus connectivity on SoC level ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [PMM: free the g_strdup_printf() string when finished with it] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21 17:15:03 +03:00
XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
arm: xlnx-zynqmp: Add boot-cpu property Add a string property that specifies the primary boot cpu. All CPUs except the one selected will start-powered-off. This allows for elf boots on any CPU, which prepares support for booting R5 elfs directly on the R5 processors. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 53331c00d80c7ce9c6a83712348773f1b38fae2b.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19 16:17:45 +03:00
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
arm: Introduce Xilinx ZynqMP SoC With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-15 05:22:58 +03:00
} XlnxZynqMPState;
#define XLNX_ZYNQMP_H
#endif
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