2014-09-10 16:12:28 +04:00
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/*
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* Virtio GPU Device
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*
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* Copyright Red Hat, Inc. 2013-2014
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*
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* Authors:
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* Dave Airlie <airlied@redhat.com>
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* Gerd Hoffmann <kraxel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2.
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* See the COPYING file in the top-level directory.
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*/
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2016-06-29 11:12:57 +03:00
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#ifndef HW_VIRTIO_GPU_H
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#define HW_VIRTIO_GPU_H
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2014-09-10 16:12:28 +04:00
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#include "qemu/queue.h"
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#include "ui/qemu-pixman.h"
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#include "ui/console.h"
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#include "hw/virtio/virtio.h"
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2016-08-08 12:31:40 +03:00
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#include "qemu/log.h"
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2019-05-24 16:09:46 +03:00
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#include "sysemu/vhost-user-backend.h"
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2014-09-10 16:12:28 +04:00
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#include "standard-headers/linux/virtio_gpu.h"
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2022-04-01 16:23:18 +03:00
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#include "standard-headers/linux/virtio_ids.h"
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2020-09-03 23:43:22 +03:00
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#include "qom/object.h"
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2018-05-25 16:27:50 +03:00
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2019-05-24 16:09:44 +03:00
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#define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base"
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2020-09-01 00:07:37 +03:00
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OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass,
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qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros
One of the goals of having less boilerplate on QOM declarations
is to avoid human error. Requiring an extra argument that is
never used is an opportunity for mistakes.
Remove the unused argument from OBJECT_DECLARE_TYPE and
OBJECT_DECLARE_SIMPLE_TYPE.
Coccinelle patch used to convert all users of the macros:
@@
declarer name OBJECT_DECLARE_TYPE;
identifier InstanceType, ClassType, lowercase, UPPERCASE;
@@
OBJECT_DECLARE_TYPE(InstanceType, ClassType,
- lowercase,
UPPERCASE);
@@
declarer name OBJECT_DECLARE_SIMPLE_TYPE;
identifier InstanceType, lowercase, UPPERCASE;
@@
OBJECT_DECLARE_SIMPLE_TYPE(InstanceType,
- lowercase,
UPPERCASE);
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Paul Durrant <paul@xen.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20200916182519.415636-4-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-16 21:25:17 +03:00
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VIRTIO_GPU_BASE)
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2019-05-24 16:09:44 +03:00
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2014-09-10 16:12:28 +04:00
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#define TYPE_VIRTIO_GPU "virtio-gpu-device"
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2021-04-30 14:35:36 +03:00
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OBJECT_DECLARE_TYPE(VirtIOGPU, VirtIOGPUClass, VIRTIO_GPU)
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2014-09-10 16:12:28 +04:00
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2021-04-30 14:35:33 +03:00
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#define TYPE_VIRTIO_GPU_GL "virtio-gpu-gl-device"
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OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUGL, VIRTIO_GPU_GL)
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2019-05-24 16:09:46 +03:00
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#define TYPE_VHOST_USER_GPU "vhost-user-gpu"
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2020-09-16 21:25:19 +03:00
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OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU)
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2019-05-24 16:09:46 +03:00
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2014-09-10 16:12:28 +04:00
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struct virtio_gpu_simple_resource {
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uint32_t resource_id;
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uint32_t width;
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uint32_t height;
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uint32_t format;
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2016-05-23 16:22:07 +03:00
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uint64_t *addrs;
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2014-09-10 16:12:28 +04:00
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struct iovec *iov;
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unsigned int iov_cnt;
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uint32_t scanout_bitmask;
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pixman_image_t *image;
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2023-06-06 14:56:47 +03:00
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#ifdef WIN32
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HANDLE handle;
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#endif
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2016-11-29 15:42:36 +03:00
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uint64_t hostmem;
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2021-05-27 02:14:18 +03:00
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uint64_t blob_size;
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void *blob;
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int dmabuf_fd;
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uint8_t *remapped;
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2014-09-10 16:12:28 +04:00
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QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
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};
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2021-05-27 02:14:21 +03:00
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struct virtio_gpu_framebuffer {
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pixman_format_code_t format;
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uint32_t bytes_pp;
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uint32_t width, height;
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uint32_t stride;
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uint32_t offset;
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};
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2014-09-10 16:12:28 +04:00
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struct virtio_gpu_scanout {
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QemuConsole *con;
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DisplaySurface *ds;
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uint32_t width, height;
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int x, y;
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int invalidate;
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uint32_t resource_id;
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2016-05-23 16:22:07 +03:00
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struct virtio_gpu_update_cursor cursor;
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2014-09-10 16:12:28 +04:00
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QEMUCursor *current_cursor;
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};
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struct virtio_gpu_requested_state {
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2020-09-27 17:57:51 +03:00
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uint16_t width_mm, height_mm;
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2014-09-10 16:12:28 +04:00
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uint32_t width, height;
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2022-02-26 14:55:16 +03:00
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uint32_t refresh_rate;
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2014-09-10 16:12:28 +04:00
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int x, y;
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};
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2019-05-24 16:09:44 +03:00
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enum virtio_gpu_base_conf_flags {
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2014-07-11 14:51:43 +04:00
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VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
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VIRTIO_GPU_FLAG_STATS_ENABLED,
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2019-02-21 11:10:54 +03:00
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VIRTIO_GPU_FLAG_EDID_ENABLED,
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2021-02-04 13:52:22 +03:00
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VIRTIO_GPU_FLAG_DMABUF_ENABLED,
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2021-05-27 02:14:23 +03:00
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VIRTIO_GPU_FLAG_BLOB_ENABLED,
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2014-07-11 14:51:43 +04:00
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};
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#define virtio_gpu_virgl_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
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#define virtio_gpu_stats_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
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2019-02-21 11:10:54 +03:00
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#define virtio_gpu_edid_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED))
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2021-02-04 13:52:22 +03:00
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#define virtio_gpu_dmabuf_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED))
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2021-05-27 02:14:23 +03:00
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#define virtio_gpu_blob_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_BLOB_ENABLED))
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2014-07-11 14:51:43 +04:00
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2019-05-24 16:09:44 +03:00
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struct virtio_gpu_base_conf {
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2014-09-10 16:12:28 +04:00
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uint32_t max_outputs;
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2014-07-11 14:51:43 +04:00
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uint32_t flags;
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2017-04-21 12:22:14 +03:00
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uint32_t xres;
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uint32_t yres;
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2014-09-10 16:12:28 +04:00
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};
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struct virtio_gpu_ctrl_command {
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VirtQueueElement elem;
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VirtQueue *vq;
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struct virtio_gpu_ctrl_hdr cmd_hdr;
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uint32_t error;
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bool finished;
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QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
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};
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2020-09-03 23:43:22 +03:00
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struct VirtIOGPUBase {
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2014-09-10 16:12:28 +04:00
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VirtIODevice parent_obj;
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2019-05-24 16:09:44 +03:00
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Error *migration_blocker;
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struct virtio_gpu_base_conf conf;
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struct virtio_gpu_config virtio_config;
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2020-09-14 16:42:23 +03:00
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const GraphicHwOps *hw_ops;
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2019-05-24 16:09:44 +03:00
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int renderer_blocked;
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int enable;
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struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
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int enabled_output_bitmask;
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struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
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2020-09-03 23:43:22 +03:00
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};
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2019-05-24 16:09:44 +03:00
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2020-09-03 23:43:22 +03:00
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struct VirtIOGPUBaseClass {
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2019-05-24 16:09:44 +03:00
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VirtioDeviceClass parent;
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2021-02-04 13:52:30 +03:00
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void (*gl_flushed)(VirtIOGPUBase *g);
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2020-09-03 23:43:22 +03:00
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};
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2019-05-24 16:09:44 +03:00
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#define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \
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DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \
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DEFINE_PROP_BIT("edid", _state, _conf.flags, \
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2019-06-07 11:34:44 +03:00
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VIRTIO_GPU_FLAG_EDID_ENABLED, true), \
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edid: set default resolution to 1280x800 (WXGA)
Currently QEMU defaults to a resolution of 1024x768 when exposing EDID
info to the guest OS. The EDID default info is important as this will
influence what resolution many guest OS will configure the screen with
on boot. It can also potentially influence what resolution the firmware
will configure the screen with, though until very recently EDK2 would
not handle EDID info.
One important thing to bear in mind is that the default graphics card
driver provided by Windows will leave the display set to whatever
resolution was enabled by the firmware on boot. Even if sufficient
VRAM is available, the resolution can't be changed without installing
new drivers. IOW, the default resolution choice is quite important
for usability of Windows.
Modern real world monitor hardware for desktop/laptop has supported
resolutions higher than 1024x768 for a long time now, perhaps as long
as 15+ years. There are quite a wide variety of native resolutions in
use today, however, and in wide screen form factors the height may not
be all that tall.
None the less, it is considered that there is scope for making the
QEMU default resolution slightly larger.
In considering what possible new default could be suitable, choices
considered were 1280x720 (720p), 1280x800 (WXGA) and 1280x1024 (SXGA).
In many ways, vertical space is the most important, and so 720p was
discarded due to loosing vertical space, despite being 25% wider.
The SXGA resolution would be good, but when taking into account
window titlebars/toolbars and window manager desktop UI, this might
be a little too tall for some users to fit the guest on their physical
montior.
This patch thus suggests a modest change to 1280x800 (WXGA). This
only consumes 1 MB per colour channel, allowing double buffered
framebuffer in 8 MB of VRAM. Width wise this is 25% larger than
QEMU's current default, but height wise this only adds 5%, so the
difference isn't massive on the QEMU side.
Overall there doesn't appear to be a compelling reason to stick
with 1024x768 resolution.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <20211129140508.1745130-1-berrange@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-11-29 17:05:08 +03:00
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DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1280), \
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DEFINE_PROP_UINT32("yres", _state, _conf.yres, 800)
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2019-05-24 16:09:44 +03:00
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2021-05-27 02:14:26 +03:00
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typedef struct VGPUDMABuf {
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QemuDmaBuf buf;
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uint32_t scanout_id;
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QTAILQ_ENTRY(VGPUDMABuf) next;
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} VGPUDMABuf;
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2020-09-03 23:43:22 +03:00
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struct VirtIOGPU {
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2019-05-24 16:09:44 +03:00
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VirtIOGPUBase parent_obj;
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uint64_t conf_max_hostmem;
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2014-09-10 16:12:28 +04:00
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VirtQueue *ctrl_vq;
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VirtQueue *cursor_vq;
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2019-05-24 16:09:44 +03:00
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QEMUBH *ctrl_bh;
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QEMUBH *cursor_bh;
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2014-09-10 16:12:28 +04:00
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QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
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2015-12-01 14:05:14 +03:00
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QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
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2014-09-10 16:12:28 +04:00
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QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
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2016-11-29 15:42:36 +03:00
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uint64_t hostmem;
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2014-09-10 16:12:28 +04:00
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2021-02-04 13:52:29 +03:00
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bool processing_cmdq;
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2014-09-10 16:12:28 +04:00
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QEMUTimer *fence_poll;
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QEMUTimer *print_stats;
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2014-07-11 14:51:43 +04:00
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uint32_t inflight;
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2014-09-10 16:12:28 +04:00
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struct {
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uint32_t max_inflight;
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uint32_t requests;
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uint32_t req_3d;
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uint32_t bytes_3d;
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} stats;
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2021-05-27 02:14:26 +03:00
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struct {
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QTAILQ_HEAD(, VGPUDMABuf) bufs;
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2021-11-04 09:51:52 +03:00
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VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS];
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2021-05-27 02:14:26 +03:00
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} dmabuf;
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2020-09-03 23:43:22 +03:00
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};
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2014-09-10 16:12:28 +04:00
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2021-04-30 14:35:36 +03:00
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struct VirtIOGPUClass {
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VirtIOGPUBaseClass parent;
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void (*handle_ctrl)(VirtIODevice *vdev, VirtQueue *vq);
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2021-04-30 14:35:39 +03:00
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void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
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2021-04-30 14:35:40 +03:00
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void (*update_cursor_data)(VirtIOGPU *g,
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struct virtio_gpu_scanout *s,
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uint32_t resource_id);
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2021-04-30 14:35:36 +03:00
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};
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2021-04-30 14:35:33 +03:00
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struct VirtIOGPUGL {
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struct VirtIOGPU parent_obj;
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2021-04-30 14:35:44 +03:00
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bool renderer_inited;
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bool renderer_reset;
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2021-04-30 14:35:33 +03:00
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};
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2020-09-03 23:43:22 +03:00
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struct VhostUserGPU {
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2019-05-24 16:09:46 +03:00
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VirtIOGPUBase parent_obj;
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2014-09-10 16:12:28 +04:00
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2019-05-24 16:09:46 +03:00
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VhostUserBackend *vhost;
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int vhost_gpu_fd; /* closed by the chardev */
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CharBackend vhost_chr;
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QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS];
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bool backend_blocked;
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2020-09-03 23:43:22 +03:00
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};
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2019-05-24 16:09:46 +03:00
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2014-09-10 16:12:28 +04:00
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#define VIRTIO_GPU_FILL_CMD(out) do { \
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size_t s; \
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s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
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&out, sizeof(out)); \
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if (s != sizeof(out)) { \
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qemu_log_mask(LOG_GUEST_ERROR, \
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"%s: command size incorrect %zu vs %zu\n", \
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__func__, s, sizeof(out)); \
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return; \
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} \
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} while (0)
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2019-05-24 16:09:44 +03:00
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/* virtio-gpu-base.c */
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bool virtio_gpu_base_device_realize(DeviceState *qdev,
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VirtIOHandleOutput ctrl_cb,
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VirtIOHandleOutput cursor_cb,
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Error **errp);
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void virtio_gpu_base_reset(VirtIOGPUBase *g);
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void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g,
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struct virtio_gpu_resp_display_info *dpy_info);
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2023-06-26 19:47:05 +03:00
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void virtio_gpu_base_generate_edid(VirtIOGPUBase *g, int scanout,
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struct virtio_gpu_resp_edid *edid);
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2014-09-10 16:12:28 +04:00
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/* virtio-gpu.c */
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void virtio_gpu_ctrl_response(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd,
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struct virtio_gpu_ctrl_hdr *resp,
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size_t resp_len);
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void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd,
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enum virtio_gpu_ctrl_type type);
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void virtio_gpu_get_display_info(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd);
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2019-02-21 11:10:54 +03:00
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void virtio_gpu_get_edid(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd);
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2018-08-29 15:21:00 +03:00
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int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
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2021-05-27 02:14:22 +03:00
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uint32_t nr_entries, uint32_t offset,
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2014-09-10 16:12:28 +04:00
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struct virtio_gpu_ctrl_command *cmd,
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2021-05-06 12:10:01 +03:00
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uint64_t **addr, struct iovec **iov,
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uint32_t *niov);
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2018-08-29 15:21:00 +03:00
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void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
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struct iovec *iov, uint32_t count);
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2015-12-01 15:18:38 +03:00
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void virtio_gpu_process_cmdq(VirtIOGPU *g);
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2021-04-30 14:35:34 +03:00
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void virtio_gpu_device_realize(DeviceState *qdev, Error **errp);
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2021-04-30 14:35:35 +03:00
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void virtio_gpu_reset(VirtIODevice *vdev);
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2021-04-30 14:35:39 +03:00
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void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
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2021-04-30 14:35:40 +03:00
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void virtio_gpu_update_cursor_data(VirtIOGPU *g,
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struct virtio_gpu_scanout *s,
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uint32_t resource_id);
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2014-09-10 16:12:28 +04:00
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2021-05-27 02:14:18 +03:00
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/* virtio-gpu-udmabuf.c */
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bool virtio_gpu_have_udmabuf(void);
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void virtio_gpu_init_udmabuf(struct virtio_gpu_simple_resource *res);
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void virtio_gpu_fini_udmabuf(struct virtio_gpu_simple_resource *res);
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2021-05-27 02:14:26 +03:00
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int virtio_gpu_update_dmabuf(VirtIOGPU *g,
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|
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uint32_t scanout_id,
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struct virtio_gpu_simple_resource *res,
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2021-11-04 09:51:52 +03:00
|
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struct virtio_gpu_framebuffer *fb,
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|
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struct virtio_gpu_rect *r);
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2021-05-27 02:14:18 +03:00
|
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|
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2014-07-11 14:51:43 +04:00
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|
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/* virtio-gpu-3d.c */
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void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd);
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|
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void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
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2021-07-02 15:32:21 +03:00
|
|
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void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g);
|
2014-07-11 14:51:43 +04:00
|
|
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void virtio_gpu_virgl_reset(VirtIOGPU *g);
|
|
|
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int virtio_gpu_virgl_init(VirtIOGPU *g);
|
2018-02-23 05:38:14 +03:00
|
|
|
int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g);
|
2019-05-24 16:09:44 +03:00
|
|
|
|
2014-09-10 16:12:28 +04:00
|
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#endif
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