2014-09-10 16:12:28 +04:00
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/*
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* Virtio GPU Device
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*
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* Copyright Red Hat, Inc. 2013-2014
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*
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* Authors:
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* Dave Airlie <airlied@redhat.com>
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* Gerd Hoffmann <kraxel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2.
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* See the COPYING file in the top-level directory.
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*/
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2016-06-29 11:12:57 +03:00
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#ifndef HW_VIRTIO_GPU_H
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#define HW_VIRTIO_GPU_H
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2014-09-10 16:12:28 +04:00
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#include "qemu/queue.h"
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#include "ui/qemu-pixman.h"
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#include "ui/console.h"
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#include "hw/virtio/virtio.h"
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#include "hw/pci/pci.h"
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2016-08-08 12:31:40 +03:00
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#include "qemu/log.h"
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2014-09-10 16:12:28 +04:00
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#include "standard-headers/linux/virtio_gpu.h"
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#define TYPE_VIRTIO_GPU "virtio-gpu-device"
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#define VIRTIO_GPU(obj) \
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OBJECT_CHECK(VirtIOGPU, (obj), TYPE_VIRTIO_GPU)
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#define VIRTIO_ID_GPU 16
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struct virtio_gpu_simple_resource {
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uint32_t resource_id;
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uint32_t width;
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uint32_t height;
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uint32_t format;
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2016-05-23 16:22:07 +03:00
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uint64_t *addrs;
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2014-09-10 16:12:28 +04:00
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struct iovec *iov;
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unsigned int iov_cnt;
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uint32_t scanout_bitmask;
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pixman_image_t *image;
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2016-11-29 15:42:36 +03:00
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uint64_t hostmem;
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2014-09-10 16:12:28 +04:00
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QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
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};
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struct virtio_gpu_scanout {
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QemuConsole *con;
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DisplaySurface *ds;
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uint32_t width, height;
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int x, y;
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int invalidate;
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uint32_t resource_id;
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2016-05-23 16:22:07 +03:00
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struct virtio_gpu_update_cursor cursor;
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2014-09-10 16:12:28 +04:00
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QEMUCursor *current_cursor;
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};
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struct virtio_gpu_requested_state {
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uint32_t width, height;
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int x, y;
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};
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2014-07-11 14:51:43 +04:00
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enum virtio_gpu_conf_flags {
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VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
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VIRTIO_GPU_FLAG_STATS_ENABLED,
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};
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#define virtio_gpu_virgl_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
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#define virtio_gpu_stats_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
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2014-09-10 16:12:28 +04:00
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struct virtio_gpu_conf {
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2016-11-29 15:42:36 +03:00
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uint64_t max_hostmem;
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2014-09-10 16:12:28 +04:00
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uint32_t max_outputs;
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2014-07-11 14:51:43 +04:00
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uint32_t flags;
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2017-04-21 12:22:14 +03:00
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uint32_t xres;
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uint32_t yres;
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2014-09-10 16:12:28 +04:00
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};
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struct virtio_gpu_ctrl_command {
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VirtQueueElement elem;
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VirtQueue *vq;
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struct virtio_gpu_ctrl_hdr cmd_hdr;
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uint32_t error;
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2015-12-01 15:18:38 +03:00
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bool waiting;
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2014-09-10 16:12:28 +04:00
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bool finished;
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QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
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};
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typedef struct VirtIOGPU {
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VirtIODevice parent_obj;
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QEMUBH *ctrl_bh;
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QEMUBH *cursor_bh;
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VirtQueue *ctrl_vq;
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VirtQueue *cursor_vq;
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int enable;
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int config_size;
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DeviceState *qdev;
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QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
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2015-12-01 14:05:14 +03:00
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QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
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2014-09-10 16:12:28 +04:00
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QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
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2016-05-19 13:25:59 +03:00
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struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
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struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
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2014-09-10 16:12:28 +04:00
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struct virtio_gpu_conf conf;
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2016-11-29 15:42:36 +03:00
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uint64_t hostmem;
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2014-09-10 16:12:28 +04:00
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int enabled_output_bitmask;
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struct virtio_gpu_config virtio_config;
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2014-07-11 14:51:43 +04:00
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bool use_virgl_renderer;
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bool renderer_inited;
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2016-06-14 16:44:07 +03:00
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int renderer_blocked;
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2014-09-10 16:12:28 +04:00
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QEMUTimer *fence_poll;
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QEMUTimer *print_stats;
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2014-07-11 14:51:43 +04:00
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uint32_t inflight;
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2014-09-10 16:12:28 +04:00
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struct {
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uint32_t max_inflight;
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uint32_t requests;
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uint32_t req_3d;
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uint32_t bytes_3d;
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} stats;
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2016-07-14 20:22:54 +03:00
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Error *migration_blocker;
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2014-09-10 16:12:28 +04:00
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} VirtIOGPU;
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extern const GraphicHwOps virtio_gpu_ops;
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/* to share between PCI and VGA */
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#define DEFINE_VIRTIO_GPU_PCI_PROPERTIES(_state) \
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DEFINE_PROP_BIT("ioeventfd", _state, flags, \
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VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, false), \
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DEFINE_PROP_UINT32("vectors", _state, nvectors, 3)
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#define VIRTIO_GPU_FILL_CMD(out) do { \
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size_t s; \
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s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
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&out, sizeof(out)); \
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if (s != sizeof(out)) { \
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qemu_log_mask(LOG_GUEST_ERROR, \
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"%s: command size incorrect %zu vs %zu\n", \
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__func__, s, sizeof(out)); \
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return; \
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} \
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} while (0)
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/* virtio-gpu.c */
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void virtio_gpu_ctrl_response(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd,
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struct virtio_gpu_ctrl_hdr *resp,
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size_t resp_len);
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void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd,
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enum virtio_gpu_ctrl_type type);
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void virtio_gpu_get_display_info(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd);
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int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
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struct virtio_gpu_ctrl_command *cmd,
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2016-05-23 16:22:07 +03:00
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uint64_t **addr, struct iovec **iov);
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2014-09-10 16:12:28 +04:00
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void virtio_gpu_cleanup_mapping_iov(struct iovec *iov, uint32_t count);
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2015-12-01 15:18:38 +03:00
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void virtio_gpu_process_cmdq(VirtIOGPU *g);
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2014-09-10 16:12:28 +04:00
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2014-07-11 14:51:43 +04:00
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/* virtio-gpu-3d.c */
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void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd);
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void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
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void virtio_gpu_virgl_reset(VirtIOGPU *g);
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2017-05-05 13:40:56 +03:00
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void virtio_gpu_gl_block(void *opaque, bool block);
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2014-07-11 14:51:43 +04:00
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int virtio_gpu_virgl_init(VirtIOGPU *g);
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2014-09-10 16:12:28 +04:00
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#endif
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