2017-07-24 11:52:47 +03:00
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/*
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* S390x DIAG instruction helper functions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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2021-07-07 13:53:16 +03:00
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#include "s390x-internal.h"
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2017-07-24 11:52:47 +03:00
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#include "hw/watchdog/wdt_diag288.h"
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#include "sysemu/cpus.h"
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#include "hw/s390x/ipl.h"
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2017-09-13 16:24:01 +03:00
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#include "hw/s390x/s390-virtio-ccw.h"
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2021-07-07 13:53:21 +03:00
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#include "sysemu/kvm.h"
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2021-07-07 13:53:23 +03:00
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#include "kvm/kvm_s390x.h"
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2023-06-24 23:06:44 +03:00
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#include "target/s390x/kvm/pv.h"
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2023-03-15 20:43:13 +03:00
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#include "qemu/error-report.h"
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2017-07-24 11:52:47 +03:00
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int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3)
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{
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uint64_t func = env->regs[r1];
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uint64_t timeout = env->regs[r1 + 1];
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uint64_t action = env->regs[r3];
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Object *obj;
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DIAG288State *diag288;
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DIAG288Class *diag288_class;
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if (r1 % 2 || action != 0) {
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return -1;
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}
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/* Timeout must be more than 15 seconds except for timer deletion */
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if (func != WDT_DIAG288_CANCEL && timeout < 15) {
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return -1;
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}
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obj = object_resolve_path_type("", TYPE_WDT_DIAG288, NULL);
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if (!obj) {
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return -1;
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}
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diag288 = DIAG288(obj);
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diag288_class = DIAG288_GET_CLASS(diag288);
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return diag288_class->handle_timer(diag288, func, timeout);
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}
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2019-11-27 20:50:45 +03:00
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static int diag308_parm_check(CPUS390XState *env, uint64_t r1, uint64_t addr,
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uintptr_t ra, bool write)
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{
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2020-03-23 11:36:06 +03:00
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/* Handled by the Ultravisor */
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if (s390_is_pv()) {
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return 0;
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}
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2019-11-27 20:50:45 +03:00
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if ((r1 & 1) || (addr & ~TARGET_PAGE_MASK)) {
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s390_program_interrupt(env, PGM_SPECIFICATION, ra);
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return -1;
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}
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if (!address_space_access_valid(&address_space_memory, addr,
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sizeof(IplParameterBlock), write,
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MEMTXATTRS_UNSPECIFIED)) {
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s390_program_interrupt(env, PGM_ADDRESSING, ra);
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return -1;
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}
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return 0;
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}
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2017-11-30 19:27:34 +03:00
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void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
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2017-07-24 11:52:47 +03:00
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{
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2020-03-23 11:36:06 +03:00
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bool valid;
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2019-03-23 05:21:48 +03:00
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CPUState *cs = env_cpu(env);
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2023-10-09 13:42:42 +03:00
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S390CPU *cpu = env_archcpu(env);
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2017-07-24 11:52:47 +03:00
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uint64_t addr = env->regs[r1];
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uint64_t subcode = env->regs[r3];
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IplParameterBlock *iplb;
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if (env->psw.mask & PSW_MASK_PSTATE) {
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2019-10-01 20:15:59 +03:00
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s390_program_interrupt(env, PGM_PRIVILEGED, ra);
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2017-07-24 11:52:47 +03:00
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return;
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}
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2019-11-27 20:50:45 +03:00
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if (subcode & ~0x0ffffULL) {
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2019-10-01 20:15:59 +03:00
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s390_program_interrupt(env, PGM_SPECIFICATION, ra);
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2017-07-24 11:52:47 +03:00
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return;
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}
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2020-03-23 11:36:06 +03:00
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if (subcode >= DIAG308_PV_SET && !s390_has_feat(S390_FEAT_UNPACK)) {
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s390_program_interrupt(env, PGM_SPECIFICATION, ra);
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return;
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}
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2017-07-24 11:52:47 +03:00
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switch (subcode) {
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2019-11-27 20:50:45 +03:00
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case DIAG308_RESET_MOD_CLR:
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2018-04-24 13:18:59 +03:00
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s390_ipl_reset_request(cs, S390_RESET_MODIFIED_CLEAR);
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2017-07-24 11:52:47 +03:00
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break;
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2019-11-27 20:50:45 +03:00
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case DIAG308_RESET_LOAD_NORM:
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2018-04-24 13:18:59 +03:00
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s390_ipl_reset_request(cs, S390_RESET_LOAD_NORMAL);
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2017-07-24 11:52:47 +03:00
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break;
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2019-11-27 20:50:45 +03:00
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case DIAG308_LOAD_CLEAR:
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/* Well we still lack the clearing bit... */
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2018-04-24 13:18:59 +03:00
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s390_ipl_reset_request(cs, S390_RESET_REIPL);
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2017-07-24 11:52:47 +03:00
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break;
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2019-11-27 20:50:45 +03:00
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case DIAG308_SET:
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2020-03-23 11:36:06 +03:00
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case DIAG308_PV_SET:
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2019-11-27 20:50:45 +03:00
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if (diag308_parm_check(env, r1, addr, ra, false)) {
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2017-07-24 11:52:47 +03:00
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return;
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}
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2017-10-07 02:49:21 +03:00
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iplb = g_new0(IplParameterBlock, 1);
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2020-03-19 16:19:16 +03:00
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if (!s390_is_pv()) {
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cpu_physical_memory_read(addr, iplb, sizeof(iplb->len));
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} else {
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s390_cpu_pv_mem_read(cpu, 0, iplb, sizeof(iplb->len));
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}
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2017-07-24 11:52:47 +03:00
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if (!iplb_valid_len(iplb)) {
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env->regs[r1 + 1] = DIAG_308_RC_INVALID;
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goto out;
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}
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2020-03-19 16:19:16 +03:00
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if (!s390_is_pv()) {
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cpu_physical_memory_read(addr, iplb, be32_to_cpu(iplb->len));
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} else {
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s390_cpu_pv_mem_read(cpu, 0, iplb, be32_to_cpu(iplb->len));
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}
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2017-07-24 11:52:47 +03:00
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2020-03-23 11:36:06 +03:00
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valid = subcode == DIAG308_PV_SET ? iplb_valid_pv(iplb) : iplb_valid(iplb);
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if (!valid) {
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2017-07-24 11:52:47 +03:00
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env->regs[r1 + 1] = DIAG_308_RC_INVALID;
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goto out;
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}
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s390_ipl_update_diag308(iplb);
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env->regs[r1 + 1] = DIAG_308_RC_OK;
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out:
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g_free(iplb);
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return;
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2019-11-27 20:50:45 +03:00
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case DIAG308_STORE:
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2020-03-23 11:36:06 +03:00
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case DIAG308_PV_STORE:
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2019-11-27 20:50:45 +03:00
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if (diag308_parm_check(env, r1, addr, ra, true)) {
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2017-07-24 11:52:47 +03:00
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return;
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}
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2020-03-23 11:36:06 +03:00
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if (subcode == DIAG308_PV_STORE) {
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iplb = s390_ipl_get_iplb_pv();
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} else {
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iplb = s390_ipl_get_iplb();
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}
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2020-03-19 16:19:16 +03:00
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if (!iplb) {
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env->regs[r1 + 1] = DIAG_308_RC_NO_CONF;
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return;
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}
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if (!s390_is_pv()) {
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2017-07-24 11:52:47 +03:00
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cpu_physical_memory_write(addr, iplb, be32_to_cpu(iplb->len));
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} else {
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2020-03-19 16:19:16 +03:00
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s390_cpu_pv_mem_write(cpu, 0, iplb, be32_to_cpu(iplb->len));
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2017-07-24 11:52:47 +03:00
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}
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2020-03-19 16:19:16 +03:00
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env->regs[r1 + 1] = DIAG_308_RC_OK;
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2017-07-24 11:52:47 +03:00
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return;
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2020-03-23 11:36:06 +03:00
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case DIAG308_PV_START:
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iplb = s390_ipl_get_iplb_pv();
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if (!iplb) {
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env->regs[r1 + 1] = DIAG_308_RC_NO_PV_CONF;
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return;
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}
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2021-07-07 13:53:21 +03:00
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if (kvm_enabled() && kvm_s390_get_hpage_1m()) {
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2020-03-23 11:36:06 +03:00
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error_report("Protected VMs can currently not be backed with "
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"huge pages");
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env->regs[r1 + 1] = DIAG_308_RC_INVAL_FOR_PV;
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return;
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}
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s390_ipl_reset_request(cs, S390_RESET_PV);
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break;
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2017-07-24 11:52:47 +03:00
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default:
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2019-10-01 20:15:59 +03:00
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s390_program_interrupt(env, PGM_SPECIFICATION, ra);
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2017-07-24 11:52:47 +03:00
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break;
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}
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}
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