2018-03-02 15:31:14 +03:00
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/*
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* QEMU RISC-V Board Compatible with SiFive Freedom U SDK
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017 SiFive, Inc.
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2019-09-06 19:20:17 +03:00
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* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
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2018-03-02 15:31:14 +03:00
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*
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* Provides a board compatible with the SiFive Freedom U SDK:
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*
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* 0) UART
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* 1) CLINT (Core Level Interruptor)
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* 2) PLIC (Platform Level Interrupt Controller)
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2019-09-06 19:20:10 +03:00
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* 3) PRCI (Power, Reset, Clock, Interrupt)
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2020-06-08 17:17:36 +03:00
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* 4) GPIO (General Purpose Input/Output Controller)
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* 5) OTP (One-Time Programmable) memory with stored serial number
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* 6) GEM (Gigabit Ethernet Controller) and management block
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2020-09-01 04:39:11 +03:00
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* 7) DMA (Direct Memory Access Controller)
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2018-03-02 15:31:14 +03:00
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*
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2019-09-06 19:20:05 +03:00
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* This board currently generates devicetree dynamically that indicates at least
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2019-09-06 19:20:06 +03:00
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* two harts and up to five harts.
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2018-03-02 15:31:14 +03:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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2019-11-16 18:08:50 +03:00
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#include "qapi/visitor.h"
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2018-03-02 15:31:14 +03:00
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#include "hw/boards.h"
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2020-06-08 17:17:38 +03:00
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#include "hw/irq.h"
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2018-03-02 15:31:14 +03:00
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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2019-09-06 19:20:06 +03:00
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#include "hw/cpu/cluster.h"
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2019-09-06 19:20:17 +03:00
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#include "hw/misc/unimp.h"
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2018-03-02 15:31:14 +03:00
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_u.h"
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2019-06-25 01:11:49 +03:00
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#include "hw/riscv/boot.h"
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2020-09-03 13:40:19 +03:00
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#include "hw/char/sifive_uart.h"
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2020-09-03 13:40:16 +03:00
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#include "hw/intc/sifive_clint.h"
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2020-09-03 13:40:17 +03:00
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#include "hw/intc/sifive_plic.h"
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2018-03-02 15:31:14 +03:00
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#include "chardev/char.h"
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2019-09-06 19:20:17 +03:00
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#include "net/eth.h"
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2018-03-02 15:31:14 +03:00
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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2020-06-08 17:17:38 +03:00
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#include "sysemu/runstate.h"
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2019-08-12 08:23:57 +03:00
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#include "sysemu/sysemu.h"
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2018-03-02 15:31:14 +03:00
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2018-03-04 01:52:13 +03:00
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#include <libfdt.h>
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2020-02-24 16:39:43 +03:00
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#if defined(TARGET_RISCV32)
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2020-05-01 16:45:55 +03:00
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# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
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2020-02-24 16:39:43 +03:00
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#else
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2020-05-01 16:45:55 +03:00
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# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin"
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2020-02-24 16:39:43 +03:00
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#endif
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2019-07-16 21:47:25 +03:00
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2018-03-02 15:31:14 +03:00
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} sifive_u_memmap[] = {
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2020-09-11 20:34:47 +03:00
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[SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
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[SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
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[SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
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[SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
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[SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
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[SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
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[SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
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[SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
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[SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
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[SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
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[SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
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[SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
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[SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
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[SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
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[SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
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[SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
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[SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
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2018-03-02 15:31:14 +03:00
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};
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2019-09-06 19:20:16 +03:00
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#define OTP_SERIAL 1
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2018-04-26 23:59:08 +03:00
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#define GEM_REVISION 0x10070109
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2019-09-06 19:19:53 +03:00
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static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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2018-03-02 15:31:14 +03:00
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uint64_t mem_size, const char *cmdline)
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{
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2019-09-06 19:20:06 +03:00
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MachineState *ms = MACHINE(qdev_get_machine());
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2018-03-02 15:31:14 +03:00
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void *fdt;
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int cpu;
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uint32_t *cells;
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char *nodename;
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2020-10-22 08:32:24 +03:00
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const char *dtb_filename;
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2019-09-06 19:20:11 +03:00
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char ethclk_names[] = "pclk\0hclk";
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2020-06-08 17:17:38 +03:00
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uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
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2019-09-06 19:20:17 +03:00
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uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
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2018-03-02 15:31:14 +03:00
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2020-10-22 08:32:24 +03:00
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dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
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if (dtb_filename) {
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fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size);
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if (!fdt) {
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error_report("load_device_tree() failed");
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exit(1);
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}
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goto update_bootargs;
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} else {
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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2018-03-02 15:31:14 +03:00
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}
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2019-09-06 19:20:19 +03:00
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qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
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qemu_fdt_setprop_string(fdt, "/", "compatible",
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"sifive,hifive-unleashed-a00");
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2018-03-02 15:31:14 +03:00
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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2018-05-11 20:22:48 +03:00
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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2018-03-02 15:31:14 +03:00
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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2019-09-06 19:20:09 +03:00
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hfclk_phandle = phandle++;
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nodename = g_strdup_printf("/hfclk");
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
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qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SIFIVE_U_HFCLK_FREQ);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
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qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
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g_free(nodename);
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rtcclk_phandle = phandle++;
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nodename = g_strdup_printf("/rtcclk");
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
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qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SIFIVE_U_RTCCLK_FREQ);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
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qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
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g_free(nodename);
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2018-03-02 15:31:14 +03:00
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nodename = g_strdup_printf("/memory@%lx",
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2020-09-11 20:34:47 +03:00
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(long)memmap[SIFIVE_U_DEV_DRAM].base);
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2018-03-02 15:31:14 +03:00
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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2020-09-11 20:34:47 +03:00
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memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
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2018-03-02 15:31:14 +03:00
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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2018-03-03 04:30:07 +03:00
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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2018-03-02 15:31:14 +03:00
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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2019-09-06 19:20:06 +03:00
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for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
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2019-05-17 18:51:24 +03:00
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int cpu_phandle = phandle++;
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2018-03-02 15:31:14 +03:00
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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2019-09-06 19:20:06 +03:00
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char *isa;
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2018-03-02 15:31:14 +03:00
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qemu_fdt_add_subnode(fdt, nodename);
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2019-09-06 19:20:06 +03:00
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/* cpu 0 is the management hart that does not have mmu */
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if (cpu != 0) {
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2020-03-07 15:48:39 +03:00
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#if defined(TARGET_RISCV32)
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
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#else
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2019-09-06 19:20:06 +03:00
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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2020-03-07 15:48:39 +03:00
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#endif
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2019-09-06 19:20:06 +03:00
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isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
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} else {
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isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
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}
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2018-03-02 15:31:14 +03:00
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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qemu_fdt_add_subnode(fdt, intc);
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2019-05-17 18:51:24 +03:00
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qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
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2018-03-02 15:31:14 +03:00
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qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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g_free(isa);
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g_free(intc);
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g_free(nodename);
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}
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2019-09-06 19:20:06 +03:00
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cells = g_new0(uint32_t, ms->smp.cpus * 4);
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for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
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2018-03-02 15:31:14 +03:00
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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2020-09-11 20:34:47 +03:00
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(long)memmap[SIFIVE_U_DEV_CLINT].base);
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2018-03-02 15:31:14 +03:00
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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2020-09-11 20:34:47 +03:00
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0x0, memmap[SIFIVE_U_DEV_CLINT].base,
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0x0, memmap[SIFIVE_U_DEV_CLINT].size);
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2018-03-02 15:31:14 +03:00
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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2019-09-06 19:20:06 +03:00
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cells, ms->smp.cpus * sizeof(uint32_t) * 4);
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2018-03-02 15:31:14 +03:00
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g_free(cells);
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g_free(nodename);
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2020-06-08 17:17:33 +03:00
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nodename = g_strdup_printf("/soc/otp@%lx",
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2020-09-11 20:34:47 +03:00
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(long)memmap[SIFIVE_U_DEV_OTP].base);
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2020-06-08 17:17:33 +03:00
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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2020-09-11 20:34:47 +03:00
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0x0, memmap[SIFIVE_U_DEV_OTP].base,
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0x0, memmap[SIFIVE_U_DEV_OTP].size);
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2020-06-08 17:17:33 +03:00
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"sifive,fu540-c000-otp");
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g_free(nodename);
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2019-09-06 19:20:10 +03:00
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prci_phandle = phandle++;
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|
|
nodename = g_strdup_printf("/soc/clock-controller@%lx",
|
2020-09-11 20:34:47 +03:00
|
|
|
(long)memmap[SIFIVE_U_DEV_PRCI].base);
|
2019-09-06 19:20:10 +03:00
|
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
|
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
|
|
|
|
hfclk_phandle, rtcclk_phandle);
|
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
2020-09-11 20:34:47 +03:00
|
|
|
0x0, memmap[SIFIVE_U_DEV_PRCI].base,
|
|
|
|
0x0, memmap[SIFIVE_U_DEV_PRCI].size);
|
2019-09-06 19:20:10 +03:00
|
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
|
|
|
"sifive,fu540-c000-prci");
|
|
|
|
g_free(nodename);
|
|
|
|
|
2019-05-17 18:51:24 +03:00
|
|
|
plic_phandle = phandle++;
|
2019-09-06 19:20:06 +03:00
|
|
|
cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
|
|
|
|
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
|
2018-03-02 15:31:14 +03:00
|
|
|
nodename =
|
|
|
|
g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
|
|
|
|
uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
|
2019-09-06 19:20:06 +03:00
|
|
|
/* cpu 0 is the management hart that does not have S-mode */
|
|
|
|
if (cpu == 0) {
|
|
|
|
cells[0] = cpu_to_be32(intc_phandle);
|
|
|
|
cells[1] = cpu_to_be32(IRQ_M_EXT);
|
|
|
|
} else {
|
|
|
|
cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
|
|
|
|
cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
|
|
|
|
cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
|
|
|
|
cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
|
|
|
|
}
|
2018-03-02 15:31:14 +03:00
|
|
|
g_free(nodename);
|
|
|
|
}
|
|
|
|
nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
|
2020-09-11 20:34:47 +03:00
|
|
|
(long)memmap[SIFIVE_U_DEV_PLIC].base);
|
2018-03-02 15:31:14 +03:00
|
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
|
|
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
|
|
|
|
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
|
|
|
|
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
|
2019-09-06 19:20:06 +03:00
|
|
|
cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
|
2018-03-02 15:31:14 +03:00
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
2020-09-11 20:34:47 +03:00
|
|
|
0x0, memmap[SIFIVE_U_DEV_PLIC].base,
|
|
|
|
0x0, memmap[SIFIVE_U_DEV_PLIC].size);
|
2018-05-11 20:24:00 +03:00
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
|
2019-09-06 19:19:51 +03:00
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
|
2018-03-02 15:31:14 +03:00
|
|
|
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
|
|
|
|
g_free(cells);
|
|
|
|
g_free(nodename);
|
|
|
|
|
2020-06-08 17:17:38 +03:00
|
|
|
gpio_phandle = phandle++;
|
2020-06-08 17:17:36 +03:00
|
|
|
nodename = g_strdup_printf("/soc/gpio@%lx",
|
2020-09-11 20:34:47 +03:00
|
|
|
(long)memmap[SIFIVE_U_DEV_GPIO].base);
|
2020-06-08 17:17:36 +03:00
|
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
2020-06-08 17:17:38 +03:00
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
|
2020-06-08 17:17:36 +03:00
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
|
|
|
|
prci_phandle, PRCI_CLK_TLCLK);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
|
|
|
|
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
|
|
|
|
qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
|
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
2020-09-11 20:34:47 +03:00
|
|
|
0x0, memmap[SIFIVE_U_DEV_GPIO].base,
|
|
|
|
0x0, memmap[SIFIVE_U_DEV_GPIO].size);
|
2020-06-08 17:17:36 +03:00
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
|
|
|
|
SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
|
|
|
|
SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
|
|
|
|
SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
|
|
|
|
SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
|
|
|
|
SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
|
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
|
|
|
|
g_free(nodename);
|
|
|
|
|
2020-06-08 17:17:38 +03:00
|
|
|
nodename = g_strdup_printf("/gpio-restart");
|
|
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
|
|
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
|
|
|
|
g_free(nodename);
|
|
|
|
|
2020-09-01 04:39:11 +03:00
|
|
|
nodename = g_strdup_printf("/soc/dma@%lx",
|
2020-09-11 20:34:47 +03:00
|
|
|
(long)memmap[SIFIVE_U_DEV_PDMA].base);
|
2020-09-01 04:39:11 +03:00
|
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
|
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
|
|
|
|
SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
|
|
|
|
SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
|
|
|
|
SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
2020-09-11 20:34:47 +03:00
|
|
|
0x0, memmap[SIFIVE_U_DEV_PDMA].base,
|
|
|
|
0x0, memmap[SIFIVE_U_DEV_PDMA].size);
|
2020-09-01 04:39:11 +03:00
|
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
|
|
|
"sifive,fu540-c000-pdma");
|
|
|
|
g_free(nodename);
|
|
|
|
|
2020-07-20 09:49:08 +03:00
|
|
|
nodename = g_strdup_printf("/soc/cache-controller@%lx",
|
2020-09-11 20:34:47 +03:00
|
|
|
(long)memmap[SIFIVE_U_DEV_L2CC].base);
|
2020-07-20 09:49:08 +03:00
|
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
2020-09-11 20:34:47 +03:00
|
|
|
0x0, memmap[SIFIVE_U_DEV_L2CC].base,
|
|
|
|
0x0, memmap[SIFIVE_U_DEV_L2CC].size);
|
2020-07-20 09:49:08 +03:00
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
|
|
|
|
SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
|
|
|
qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
|
|
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
|
|
|
"sifive,fu540-c000-ccache");
|
|
|
|
g_free(nodename);
|
|
|
|
|
2019-09-06 19:20:17 +03:00
|
|
|
phy_phandle = phandle++;
|
2018-04-26 23:59:08 +03:00
|
|
|
nodename = g_strdup_printf("/soc/ethernet@%lx",
|
2020-09-11 20:34:47 +03:00
|
|
|
(long)memmap[SIFIVE_U_DEV_GEM].base);
|
2018-04-26 23:59:08 +03:00
|
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
2019-09-06 19:20:17 +03:00
|
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
|
|
|
"sifive,fu540-c000-gem");
|
2018-04-26 23:59:08 +03:00
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
2020-09-11 20:34:47 +03:00
|
|
|
0x0, memmap[SIFIVE_U_DEV_GEM].base,
|
|
|
|
0x0, memmap[SIFIVE_U_DEV_GEM].size,
|
|
|
|
0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
|
|
|
|
0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
|
2018-04-26 23:59:08 +03:00
|
|
|
qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
|
|
|
|
qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
|
2019-09-06 19:20:17 +03:00
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
|
2019-09-06 19:19:51 +03:00
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
|
2018-12-13 21:34:52 +03:00
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
|
2019-09-06 19:20:11 +03:00
|
|
|
prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
|
2019-07-19 16:40:45 +03:00
|
|
|
qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
|
2018-12-13 21:34:52 +03:00
|
|
|
sizeof(ethclk_names));
|
2019-09-06 19:20:17 +03:00
|
|
|
qemu_fdt_setprop(fdt, nodename, "local-mac-address",
|
|
|
|
s->soc.gem.conf.macaddr.a, ETH_ALEN);
|
2019-09-06 19:19:51 +03:00
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
|
2019-09-21 08:41:31 +03:00
|
|
|
|
|
|
|
qemu_fdt_add_subnode(fdt, "/aliases");
|
|
|
|
qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
|
|
|
|
|
2018-04-26 23:59:08 +03:00
|
|
|
g_free(nodename);
|
|
|
|
|
|
|
|
nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
|
2020-09-11 20:34:47 +03:00
|
|
|
(long)memmap[SIFIVE_U_DEV_GEM].base);
|
2018-04-26 23:59:08 +03:00
|
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
2019-09-06 19:20:17 +03:00
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
|
2019-09-06 19:19:51 +03:00
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
|
2018-04-26 23:59:08 +03:00
|
|
|
g_free(nodename);
|
|
|
|
|
2019-09-06 19:20:13 +03:00
|
|
|
nodename = g_strdup_printf("/soc/serial@%lx",
|
2020-09-11 20:34:47 +03:00
|
|
|
(long)memmap[SIFIVE_U_DEV_UART0].base);
|
2018-03-02 15:31:14 +03:00
|
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
|
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
|
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
2020-09-11 20:34:47 +03:00
|
|
|
0x0, memmap[SIFIVE_U_DEV_UART0].base,
|
|
|
|
0x0, memmap[SIFIVE_U_DEV_UART0].size);
|
2019-09-06 19:20:11 +03:00
|
|
|
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
|
|
|
|
prci_phandle, PRCI_CLK_TLCLK);
|
2019-09-06 19:19:51 +03:00
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
|
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
|
2018-03-02 15:31:14 +03:00
|
|
|
|
|
|
|
qemu_fdt_add_subnode(fdt, "/chosen");
|
|
|
|
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
|
2019-07-19 16:40:44 +03:00
|
|
|
qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
|
|
|
|
|
2018-03-02 15:31:14 +03:00
|
|
|
g_free(nodename);
|
2020-10-22 08:32:24 +03:00
|
|
|
|
|
|
|
update_bootargs:
|
|
|
|
if (cmdline) {
|
|
|
|
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
|
|
|
|
}
|
2018-03-02 15:31:14 +03:00
|
|
|
}
|
|
|
|
|
2020-06-08 17:17:38 +03:00
|
|
|
static void sifive_u_machine_reset(void *opaque, int n, int level)
|
|
|
|
{
|
|
|
|
/* gpio pin active low triggers reset */
|
|
|
|
if (!level) {
|
|
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-03 01:57:22 +03:00
|
|
|
static void sifive_u_machine_init(MachineState *machine)
|
2018-03-02 15:31:14 +03:00
|
|
|
{
|
|
|
|
const struct MemmapEntry *memmap = sifive_u_memmap;
|
2019-10-09 02:32:14 +03:00
|
|
|
SiFiveUState *s = RISCV_U_MACHINE(machine);
|
2018-03-04 01:52:13 +03:00
|
|
|
MemoryRegion *system_memory = get_system_memory();
|
2018-03-02 15:31:14 +03:00
|
|
|
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
|
2019-10-09 02:32:11 +03:00
|
|
|
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
|
2020-09-11 20:34:47 +03:00
|
|
|
target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
|
2020-10-14 03:17:33 +03:00
|
|
|
target_ulong firmware_end_addr, kernel_start_addr;
|
2020-07-01 21:39:49 +03:00
|
|
|
uint32_t start_addr_hi32 = 0x00000000;
|
2018-03-04 01:52:13 +03:00
|
|
|
int i;
|
2020-07-01 21:39:47 +03:00
|
|
|
uint32_t fdt_load_addr;
|
2020-07-01 21:39:48 +03:00
|
|
|
uint64_t kernel_entry;
|
2018-03-02 15:31:14 +03:00
|
|
|
|
2018-04-26 21:15:24 +03:00
|
|
|
/* Initialize SoC */
|
qom: Less verbose object_initialize_child()
All users of object_initialize_child() pass the obvious child size
argument. Almost all pass &error_abort and no properties. Tiresome.
Rename object_initialize_child() to
object_initialize_child_with_props() to free the name. New
convenience wrapper object_initialize_child() automates the size
argument, and passes &error_abort and no properties.
Rename object_initialize_childv() to
object_initialize_child_with_propsv() for consistency.
Convert callers with this Coccinelle script:
@@
expression parent, propname, type;
expression child, size;
symbol error_abort;
@@
- object_initialize_child(parent, propname, OBJECT(child), size, type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, size, type, &error_abort, NULL)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, child, sizeof(*child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, &child, sizeof(child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, &child, type)
@@
expression parent, propname, type;
expression child, size, err;
expression list props;
@@
- object_initialize_child(parent, propname, child, size, type, err, props)
+ object_initialize_child_with_props(parent, propname, child, size, type, err, props)
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
[Rebased: machine opentitan is new (commit fe0fe4735e7)]
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-37-armbru@redhat.com>
2020-06-10 08:32:25 +03:00
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object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
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qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 19:05:54 +03:00
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object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
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&error_abort);
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2020-10-14 03:17:25 +03:00
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object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
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&error_abort);
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qdev: Convert bus-less devices to qdev_realize() with Coccinelle
All remaining conversions to qdev_realize() are for bus-less devices.
Coccinelle script:
// only correct for bus-less @dev!
@@
expression errp;
expression dev;
@@
- qdev_init_nofail(dev);
+ qdev_realize(dev, NULL, &error_fatal);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(dev, true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
2020-06-10 08:32:45 +03:00
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qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
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2018-03-02 15:31:14 +03:00
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/* register RAM */
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memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
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machine->ram_size, &error_fatal);
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2020-09-11 20:34:47 +03:00
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
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2018-04-26 21:15:24 +03:00
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main_mem);
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2018-03-02 15:31:14 +03:00
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2019-10-09 02:32:11 +03:00
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/* register QSPI0 Flash */
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memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
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2020-09-11 20:34:47 +03:00
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memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
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2019-10-09 02:32:11 +03:00
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flash0);
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2020-06-08 17:17:38 +03:00
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/* register gpio-restart */
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qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
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qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
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2018-03-02 15:31:14 +03:00
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/* create device tree */
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2019-09-06 19:19:53 +03:00
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create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
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2018-03-02 15:31:14 +03:00
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2020-06-16 03:50:39 +03:00
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if (s->start_in_flash) {
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/*
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* If start_in_flash property is given, assign s->msel to a value
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* that representing booting from QSPI0 memory-mapped flash.
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*
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* This also means that when both start_in_flash and msel properties
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* are given, start_in_flash takes the precedence over msel.
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*
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* Note this is to keep backward compatibility not to break existing
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* users that use start_in_flash property.
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*/
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s->msel = MSEL_MEMMAP_QSPI0_FLASH;
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}
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switch (s->msel) {
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case MSEL_MEMMAP_QSPI0_FLASH:
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2020-09-11 20:34:47 +03:00
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start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
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2020-06-16 03:50:39 +03:00
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break;
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case MSEL_L2LIM_QSPI0_FLASH:
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case MSEL_L2LIM_QSPI2_SD:
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2020-09-11 20:34:47 +03:00
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start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
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2020-06-16 03:50:39 +03:00
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break;
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default:
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2020-09-11 20:34:47 +03:00
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start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
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2020-06-16 03:50:39 +03:00
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break;
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}
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2020-10-14 03:17:33 +03:00
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firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME,
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start_addr, NULL);
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2019-06-25 01:11:52 +03:00
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2018-03-02 15:31:14 +03:00
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if (machine->kernel_filename) {
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2020-10-14 03:17:33 +03:00
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kernel_start_addr = riscv_calc_kernel_start_addr(machine,
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firmware_end_addr);
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kernel_entry = riscv_load_kernel(machine->kernel_filename,
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kernel_start_addr, NULL);
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2019-07-19 16:40:43 +03:00
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if (machine->initrd_filename) {
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hwaddr start;
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hwaddr end = riscv_load_initrd(machine->initrd_filename,
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machine->ram_size, kernel_entry,
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&start);
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2019-09-06 19:19:53 +03:00
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qemu_fdt_setprop_cell(s->fdt, "/chosen",
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2019-07-19 16:40:43 +03:00
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"linux,initrd-start", start);
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2019-09-06 19:19:53 +03:00
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qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
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2019-07-19 16:40:43 +03:00
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end);
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}
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2020-07-01 21:39:48 +03:00
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} else {
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/*
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* If dynamic firmware is used, it doesn't know where is the next mode
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* if kernel argument is not set.
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*/
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kernel_entry = 0;
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2018-03-02 15:31:14 +03:00
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}
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2020-07-01 21:39:47 +03:00
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/* Compute the fdt load address in dram */
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2020-09-11 20:34:47 +03:00
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fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
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2020-07-01 21:39:47 +03:00
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machine->ram_size, s->fdt);
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2020-07-01 21:39:49 +03:00
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#if defined(TARGET_RISCV64)
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start_addr_hi32 = start_addr >> 32;
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#endif
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2020-07-01 21:39:47 +03:00
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2018-03-02 15:31:14 +03:00
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/* reset vector */
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2020-07-01 21:39:47 +03:00
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uint32_t reset_vec[11] = {
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2020-06-16 03:50:39 +03:00
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s->msel, /* MSEL pin state */
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2020-07-01 21:39:48 +03:00
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0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
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0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
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2018-03-02 15:31:14 +03:00
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0xf1402573, /* csrr a0, mhartid */
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#if defined(TARGET_RISCV32)
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2020-07-01 21:39:47 +03:00
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0x0202a583, /* lw a1, 32(t0) */
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2018-03-02 15:31:14 +03:00
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0x0182a283, /* lw t0, 24(t0) */
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#elif defined(TARGET_RISCV64)
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2020-07-01 21:39:47 +03:00
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0x0202b583, /* ld a1, 32(t0) */
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0x0182b283, /* ld t0, 24(t0) */
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2018-03-02 15:31:14 +03:00
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#endif
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0x00028067, /* jr t0 */
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2019-10-09 02:32:18 +03:00
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start_addr, /* start: .dword */
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2020-07-01 21:39:49 +03:00
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start_addr_hi32,
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2020-07-01 21:39:47 +03:00
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fdt_load_addr, /* fdt_laddr: .dword */
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0x00000000,
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2020-07-01 21:39:48 +03:00
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/* fw_dyn: */
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2018-03-02 15:31:14 +03:00
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};
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2018-03-04 01:52:13 +03:00
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/* copy in the reset vector in little_endian byte order */
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2020-07-01 21:39:47 +03:00
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for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
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2018-03-04 01:52:13 +03:00
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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2020-09-11 20:34:47 +03:00
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memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
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2020-07-01 21:39:48 +03:00
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2020-09-11 20:34:47 +03:00
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riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
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memmap[SIFIVE_U_DEV_MROM].size,
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2020-07-01 21:39:48 +03:00
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sizeof(reset_vec), kernel_entry);
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2018-04-26 21:15:24 +03:00
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}
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2020-03-03 01:57:22 +03:00
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static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
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{
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SiFiveUState *s = RISCV_U_MACHINE(obj);
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return s->start_in_flash;
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}
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static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
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{
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SiFiveUState *s = RISCV_U_MACHINE(obj);
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s->start_in_flash = value;
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}
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2020-06-08 17:17:39 +03:00
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static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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2019-11-16 18:08:50 +03:00
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{
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visit_type_uint32(v, name, (uint32_t *)opaque, errp);
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}
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2020-06-08 17:17:39 +03:00
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static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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2019-11-16 18:08:50 +03:00
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{
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visit_type_uint32(v, name, (uint32_t *)opaque, errp);
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}
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2020-03-03 01:57:22 +03:00
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static void sifive_u_machine_instance_init(Object *obj)
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{
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SiFiveUState *s = RISCV_U_MACHINE(obj);
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s->start_in_flash = false;
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2020-06-08 17:17:40 +03:00
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s->msel = 0;
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object_property_add(obj, "msel", "uint32",
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sifive_u_machine_get_uint32_prop,
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sifive_u_machine_set_uint32_prop, NULL, &s->msel);
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object_property_set_description(obj, "msel",
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"Mode Select (MSEL[3:0]) pin state");
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2019-11-16 18:08:50 +03:00
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s->serial = OTP_SERIAL;
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qom: Drop parameter @errp of object_property_add() & friends
The only way object_property_add() can fail is when a property with
the same name already exists. Since our property names are all
hardcoded, failure is a programming error, and the appropriate way to
handle it is passing &error_abort.
Same for its variants, except for object_property_add_child(), which
additionally fails when the child already has a parent. Parentage is
also under program control, so this is a programming error, too.
We have a bit over 500 callers. Almost half of them pass
&error_abort, slightly fewer ignore errors, one test case handles
errors, and the remaining few callers pass them to their own callers.
The previous few commits demonstrated once again that ignoring
programming errors is a bad idea.
Of the few ones that pass on errors, several violate the Error API.
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call. ich9_pm_add_properties(), sparc32_ledma_realize(),
sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize()
are wrong that way.
When the one appropriate choice of argument is &error_abort, letting
users pick the argument is a bad idea.
Drop parameter @errp and assert the preconditions instead.
There's one exception to "duplicate property name is a programming
error": the way object_property_add() implements the magic (and
undocumented) "automatic arrayification". Don't drop @errp there.
Instead, rename object_property_add() to object_property_try_add(),
and add the obvious wrapper object_property_add().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-15-armbru@redhat.com>
[Two semantic rebase conflicts resolved]
2020-05-05 18:29:22 +03:00
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object_property_add(obj, "serial", "uint32",
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2020-06-08 17:17:39 +03:00
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sifive_u_machine_get_uint32_prop,
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sifive_u_machine_set_uint32_prop, NULL, &s->serial);
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2020-05-05 18:29:15 +03:00
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object_property_set_description(obj, "serial", "Board serial number");
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2020-03-03 01:57:22 +03:00
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}
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static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "RISC-V Board compatible with SiFive U SDK";
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mc->init = sifive_u_machine_init;
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mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
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mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
|
2020-10-14 03:17:25 +03:00
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#if defined(TARGET_RISCV32)
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mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34;
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#elif defined(TARGET_RISCV64)
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mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54;
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#endif
|
2020-03-03 01:57:22 +03:00
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mc->default_cpus = mc->min_cpus;
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2020-09-22 01:10:45 +03:00
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object_class_property_add_bool(oc, "start-in-flash",
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sifive_u_machine_get_start_in_flash,
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sifive_u_machine_set_start_in_flash);
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object_class_property_set_description(oc, "start-in-flash",
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"Set on to tell QEMU's ROM to jump to "
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"flash. Otherwise QEMU will jump to DRAM "
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"or L2LIM depending on the msel value");
|
2020-03-03 01:57:22 +03:00
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}
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static const TypeInfo sifive_u_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("sifive_u"),
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.parent = TYPE_MACHINE,
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.class_init = sifive_u_machine_class_init,
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.instance_init = sifive_u_machine_instance_init,
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.instance_size = sizeof(SiFiveUState),
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};
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static void sifive_u_machine_init_register_types(void)
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{
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type_register_static(&sifive_u_machine_typeinfo);
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}
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type_init(sifive_u_machine_init_register_types)
|
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|
2020-05-21 17:42:26 +03:00
|
|
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static void sifive_u_soc_instance_init(Object *obj)
|
2018-04-26 21:15:24 +03:00
|
|
|
{
|
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SiFiveUSoCState *s = RISCV_U_SOC(obj);
|
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|
|
qom: Less verbose object_initialize_child()
All users of object_initialize_child() pass the obvious child size
argument. Almost all pass &error_abort and no properties. Tiresome.
Rename object_initialize_child() to
object_initialize_child_with_props() to free the name. New
convenience wrapper object_initialize_child() automates the size
argument, and passes &error_abort and no properties.
Rename object_initialize_childv() to
object_initialize_child_with_propsv() for consistency.
Convert callers with this Coccinelle script:
@@
expression parent, propname, type;
expression child, size;
symbol error_abort;
@@
- object_initialize_child(parent, propname, OBJECT(child), size, type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, size, type, &error_abort, NULL)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, child, sizeof(*child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, &child, sizeof(child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, &child, type)
@@
expression parent, propname, type;
expression child, size, err;
expression list props;
@@
- object_initialize_child(parent, propname, child, size, type, err, props)
+ object_initialize_child_with_props(parent, propname, child, size, type, err, props)
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
[Rebased: machine opentitan is new (commit fe0fe4735e7)]
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-37-armbru@redhat.com>
2020-06-10 08:32:25 +03:00
|
|
|
object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
|
2019-09-06 19:20:06 +03:00
|
|
|
qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
|
|
|
|
|
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
This is the same transformation as in the previous commit, except
sysbus_init_child_obj() and realize are too separated for the commit's
Coccinelle script to handle, typically because sysbus_init_child_obj()
is in a device's instance_init() method, and the matching realize is
in its realize() method.
Perhaps a Coccinelle wizard could make it transform that pattern, but
I'm just a bungler, and the best I can do is transforming the two
separate parts separately:
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(child, true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
@@
- qdev_init_nofail(DEVICE(child));
+ sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
expression dev;
@@
dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
identifier dev;
@@
DeviceState *dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression parent, name, size, type;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
This script is *unsound*: we need to manually verify init and realize
conversions are properly paired.
This commit has only the pairs where object_initialize_child()'s
@child and sysbus_realize()'s @dev argument text match exactly within
the same source file.
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 08:32:37 +03:00
|
|
|
object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
|
|
|
|
TYPE_RISCV_HART_ARRAY);
|
2019-09-06 19:20:06 +03:00
|
|
|
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
|
|
|
|
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
|
|
|
|
qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
|
2020-09-01 04:38:58 +03:00
|
|
|
qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
|
2019-09-06 19:20:06 +03:00
|
|
|
|
qom: Less verbose object_initialize_child()
All users of object_initialize_child() pass the obvious child size
argument. Almost all pass &error_abort and no properties. Tiresome.
Rename object_initialize_child() to
object_initialize_child_with_props() to free the name. New
convenience wrapper object_initialize_child() automates the size
argument, and passes &error_abort and no properties.
Rename object_initialize_childv() to
object_initialize_child_with_propsv() for consistency.
Convert callers with this Coccinelle script:
@@
expression parent, propname, type;
expression child, size;
symbol error_abort;
@@
- object_initialize_child(parent, propname, OBJECT(child), size, type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, size, type, &error_abort, NULL)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, child, sizeof(*child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, &child, sizeof(child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, &child, type)
@@
expression parent, propname, type;
expression child, size, err;
expression list props;
@@
- object_initialize_child(parent, propname, child, size, type, err, props)
+ object_initialize_child_with_props(parent, propname, child, size, type, err, props)
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
[Rebased: machine opentitan is new (commit fe0fe4735e7)]
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-37-armbru@redhat.com>
2020-06-10 08:32:25 +03:00
|
|
|
object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
|
2019-09-06 19:20:06 +03:00
|
|
|
qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
|
|
|
|
|
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
This is the same transformation as in the previous commit, except
sysbus_init_child_obj() and realize are too separated for the commit's
Coccinelle script to handle, typically because sysbus_init_child_obj()
is in a device's instance_init() method, and the matching realize is
in its realize() method.
Perhaps a Coccinelle wizard could make it transform that pattern, but
I'm just a bungler, and the best I can do is transforming the two
separate parts separately:
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(child, true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
@@
- qdev_init_nofail(DEVICE(child));
+ sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
expression dev;
@@
dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
identifier dev;
@@
DeviceState *dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression parent, name, size, type;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
This script is *unsound*: we need to manually verify init and realize
conversions are properly paired.
This commit has only the pairs where object_initialize_child()'s
@child and sysbus_realize()'s @dev argument text match exactly within
the same source file.
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 08:32:37 +03:00
|
|
|
object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
|
|
|
|
TYPE_RISCV_HART_ARRAY);
|
2018-04-26 23:59:08 +03:00
|
|
|
|
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
This is the same transformation as in the previous commit, except
sysbus_init_child_obj() and realize are too separated for the commit's
Coccinelle script to handle, typically because sysbus_init_child_obj()
is in a device's instance_init() method, and the matching realize is
in its realize() method.
Perhaps a Coccinelle wizard could make it transform that pattern, but
I'm just a bungler, and the best I can do is transforming the two
separate parts separately:
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(child, true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
@@
- qdev_init_nofail(DEVICE(child));
+ sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
expression dev;
@@
dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
identifier dev;
@@
DeviceState *dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression parent, name, size, type;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
This script is *unsound*: we need to manually verify init and realize
conversions are properly paired.
This commit has only the pairs where object_initialize_child()'s
@child and sysbus_realize()'s @dev argument text match exactly within
the same source file.
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 08:32:37 +03:00
|
|
|
object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
|
|
|
|
object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
|
|
|
|
object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
|
2020-06-08 17:17:36 +03:00
|
|
|
object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
|
2020-09-01 04:39:11 +03:00
|
|
|
object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
|
2018-04-26 21:15:24 +03:00
|
|
|
}
|
|
|
|
|
2020-05-21 17:42:26 +03:00
|
|
|
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
|
2018-04-26 21:15:24 +03:00
|
|
|
{
|
2019-05-18 23:54:23 +03:00
|
|
|
MachineState *ms = MACHINE(qdev_get_machine());
|
2018-04-26 21:15:24 +03:00
|
|
|
SiFiveUSoCState *s = RISCV_U_SOC(dev);
|
|
|
|
const struct MemmapEntry *memmap = sifive_u_memmap;
|
|
|
|
MemoryRegion *system_memory = get_system_memory();
|
|
|
|
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
|
2019-10-09 02:32:07 +03:00
|
|
|
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
|
2019-05-17 18:51:25 +03:00
|
|
|
char *plic_hart_config;
|
|
|
|
size_t plic_hart_config_len;
|
2018-04-26 23:59:08 +03:00
|
|
|
int i;
|
|
|
|
NICInfo *nd = &nd_table[0];
|
2018-04-26 21:15:24 +03:00
|
|
|
|
2020-10-14 03:17:25 +03:00
|
|
|
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
|
|
|
|
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
|
|
|
|
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
|
|
|
|
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
|
|
|
|
|
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
This is the same transformation as in the previous commit, except
sysbus_init_child_obj() and realize are too separated for the commit's
Coccinelle script to handle, typically because sysbus_init_child_obj()
is in a device's instance_init() method, and the matching realize is
in its realize() method.
Perhaps a Coccinelle wizard could make it transform that pattern, but
I'm just a bungler, and the best I can do is transforming the two
separate parts separately:
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(child, true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
@@
- qdev_init_nofail(DEVICE(child));
+ sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
expression dev;
@@
dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
identifier dev;
@@
DeviceState *dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression parent, name, size, type;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
This script is *unsound*: we need to manually verify init and realize
conversions are properly paired.
This commit has only the pairs where object_initialize_child()'s
@child and sysbus_realize()'s @dev argument text match exactly within
the same source file.
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 08:32:37 +03:00
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
|
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
|
2019-09-06 19:20:06 +03:00
|
|
|
/*
|
|
|
|
* The cluster must be realized after the RISC-V hart array container,
|
|
|
|
* as the container's CPU object is only created on realize, and the
|
|
|
|
* CPU must exist and have been parented into the cluster before the
|
|
|
|
* cluster is realized.
|
|
|
|
*/
|
qdev: Convert bus-less devices to qdev_realize() with Coccinelle
All remaining conversions to qdev_realize() are for bus-less devices.
Coccinelle script:
// only correct for bus-less @dev!
@@
expression errp;
expression dev;
@@
- qdev_init_nofail(dev);
+ qdev_realize(dev, NULL, &error_fatal);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(dev, true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
2020-06-10 08:32:45 +03:00
|
|
|
qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
|
|
|
|
qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
|
2018-04-26 21:15:24 +03:00
|
|
|
|
|
|
|
/* boot rom */
|
2020-02-22 20:12:57 +03:00
|
|
|
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
|
2020-09-11 20:34:47 +03:00
|
|
|
memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
|
|
|
|
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
|
2018-04-26 21:15:24 +03:00
|
|
|
mask_rom);
|
2018-03-02 15:31:14 +03:00
|
|
|
|
2019-10-09 02:32:07 +03:00
|
|
|
/*
|
|
|
|
* Add L2-LIM at reset size.
|
|
|
|
* This should be reduced in size as the L2 Cache Controller WayEnable
|
|
|
|
* register is incremented. Unfortunately I don't see a nice (or any) way
|
|
|
|
* to handle reducing or blocking out the L2 LIM while still allowing it
|
|
|
|
* be re returned to all enabled after a reset. For the time being, just
|
|
|
|
* leave it enabled all the time. This won't break anything, but will be
|
|
|
|
* too generous to misbehaving guests.
|
|
|
|
*/
|
|
|
|
memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
|
2020-09-11 20:34:47 +03:00
|
|
|
memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
|
|
|
|
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
|
2019-10-09 02:32:07 +03:00
|
|
|
l2lim_mem);
|
|
|
|
|
2019-05-17 18:51:25 +03:00
|
|
|
/* create PLIC hart topology configuration string */
|
2019-05-18 23:54:23 +03:00
|
|
|
plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
|
|
|
|
ms->smp.cpus;
|
2019-05-17 18:51:25 +03:00
|
|
|
plic_hart_config = g_malloc0(plic_hart_config_len);
|
2019-05-18 23:54:23 +03:00
|
|
|
for (i = 0; i < ms->smp.cpus; i++) {
|
2019-05-17 18:51:25 +03:00
|
|
|
if (i != 0) {
|
2019-09-06 19:20:07 +03:00
|
|
|
strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
|
|
|
|
plic_hart_config_len);
|
|
|
|
} else {
|
|
|
|
strncat(plic_hart_config, "M", plic_hart_config_len);
|
2019-05-17 18:51:25 +03:00
|
|
|
}
|
|
|
|
plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
|
|
|
|
}
|
|
|
|
|
2018-03-02 15:31:14 +03:00
|
|
|
/* MMIO */
|
2020-09-11 20:34:47 +03:00
|
|
|
s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
|
2020-05-15 07:55:33 +03:00
|
|
|
plic_hart_config, 0,
|
2018-03-02 15:31:14 +03:00
|
|
|
SIFIVE_U_PLIC_NUM_SOURCES,
|
|
|
|
SIFIVE_U_PLIC_NUM_PRIORITIES,
|
|
|
|
SIFIVE_U_PLIC_PRIORITY_BASE,
|
|
|
|
SIFIVE_U_PLIC_PENDING_BASE,
|
|
|
|
SIFIVE_U_PLIC_ENABLE_BASE,
|
|
|
|
SIFIVE_U_PLIC_ENABLE_STRIDE,
|
|
|
|
SIFIVE_U_PLIC_CONTEXT_BASE,
|
|
|
|
SIFIVE_U_PLIC_CONTEXT_STRIDE,
|
2020-09-11 20:34:47 +03:00
|
|
|
memmap[SIFIVE_U_DEV_PLIC].size);
|
2019-12-10 10:14:37 +03:00
|
|
|
g_free(plic_hart_config);
|
2020-09-11 20:34:47 +03:00
|
|
|
sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
|
2018-04-26 23:54:12 +03:00
|
|
|
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
|
2020-09-11 20:34:47 +03:00
|
|
|
sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
|
2018-12-14 03:19:03 +03:00
|
|
|
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
|
2020-09-11 20:34:47 +03:00
|
|
|
sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
|
|
|
|
memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
|
2020-09-01 04:39:10 +03:00
|
|
|
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
|
|
|
|
SIFIVE_CLINT_TIMEBASE_FREQ, false);
|
2018-04-26 23:59:08 +03:00
|
|
|
|
2020-06-30 12:03:42 +03:00
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
|
|
|
|
return;
|
|
|
|
}
|
2020-09-11 20:34:47 +03:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
|
2019-09-06 19:20:10 +03:00
|
|
|
|
2020-06-08 17:17:36 +03:00
|
|
|
qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
|
2020-06-30 12:03:42 +03:00
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
|
|
|
|
return;
|
|
|
|
}
|
2020-09-11 20:34:47 +03:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
|
2020-06-08 17:17:36 +03:00
|
|
|
|
|
|
|
/* Pass all GPIOs to the SOC layer so they are available to the board */
|
|
|
|
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
|
|
|
|
|
|
|
|
/* Connect GPIO interrupts to the PLIC */
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->plic),
|
|
|
|
SIFIVE_U_GPIO_IRQ0 + i));
|
2020-09-01 04:39:11 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* PDMA */
|
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
|
2020-09-11 20:34:47 +03:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
|
2020-09-01 04:39:11 +03:00
|
|
|
|
|
|
|
/* Connect PDMA interrupts to the PLIC */
|
|
|
|
for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->plic),
|
|
|
|
SIFIVE_U_PDMA_IRQ0 + i));
|
2020-06-08 17:17:36 +03:00
|
|
|
}
|
|
|
|
|
2020-03-03 02:08:51 +03:00
|
|
|
qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
|
2020-06-30 12:03:42 +03:00
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
|
|
|
|
return;
|
|
|
|
}
|
2020-09-11 20:34:47 +03:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
|
2019-09-06 19:20:16 +03:00
|
|
|
|
2020-07-15 17:04:40 +03:00
|
|
|
/* FIXME use qdev NIC properties instead of nd_table[] */
|
2018-04-26 23:59:08 +03:00
|
|
|
if (nd->used) {
|
|
|
|
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
|
|
|
|
qdev_set_nic_properties(DEVICE(&s->gem), nd);
|
|
|
|
}
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 19:05:54 +03:00
|
|
|
object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
|
2018-04-26 23:59:08 +03:00
|
|
|
&error_abort);
|
error: Eliminate error_propagate() with Coccinelle, part 1
When all we do with an Error we receive into a local variable is
propagating to somewhere else, we can just as well receive it there
right away. Convert
if (!foo(..., &err)) {
...
error_propagate(errp, err);
...
return ...
}
to
if (!foo(..., errp)) {
...
...
return ...
}
where nothing else needs @err. Coccinelle script:
@rule1 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
binary operator op;
constant c1, c2;
symbol false;
@@
if (
(
- fun(args, &err, args2)
+ fun(args, errp, args2)
|
- !fun(args, &err, args2)
+ !fun(args, errp, args2)
|
- fun(args, &err, args2) op c1
+ fun(args, errp, args2) op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
)
}
@rule2 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
expression var;
binary operator op;
constant c1, c2;
symbol false;
@@
- var = fun(args, &err, args2);
+ var = fun(args, errp, args2);
... when != err
if (
(
var
|
!var
|
var op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
|
return var;
)
}
@depends on rule1 || rule2@
identifier err;
@@
- Error *err = NULL;
... when != err
Not exactly elegant, I'm afraid.
The "when != lbl:" is necessary to avoid transforming
if (fun(args, &err)) {
goto out
}
...
out:
error_propagate(errp, err);
even though other paths to label out still need the error_propagate().
For an actual example, see sclp_realize().
Without the "when strict", Coccinelle transforms vfio_msix_setup(),
incorrectly. I don't know what exactly "when strict" does, only that
it helps here.
The match of return is narrower than what I want, but I can't figure
out how to express "return where the operand doesn't use @err". For
an example where it's too narrow, see vfio_intx_enable().
Silently fails to convert hw/arm/armsse.c, because Coccinelle gets
confused by ARMSSE being used both as typedef and function-like macro
there. Converted manually.
Line breaks tidied up manually. One nested declaration of @local_err
deleted manually. Preexisting unwanted blank line dropped in
hw/riscv/sifive_e.c.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20200707160613.848843-35-armbru@redhat.com>
2020-07-07 19:06:02 +03:00
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
|
2018-04-26 23:59:08 +03:00
|
|
|
return;
|
|
|
|
}
|
2020-09-11 20:34:47 +03:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
|
2018-04-26 23:59:08 +03:00
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
|
2020-06-08 17:17:32 +03:00
|
|
|
qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
|
2019-09-06 19:20:17 +03:00
|
|
|
|
|
|
|
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
|
2020-09-11 20:34:47 +03:00
|
|
|
memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
|
2020-06-16 03:50:41 +03:00
|
|
|
|
|
|
|
create_unimplemented_device("riscv.sifive.u.dmc",
|
2020-09-11 20:34:47 +03:00
|
|
|
memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
|
2020-07-20 09:49:08 +03:00
|
|
|
|
|
|
|
create_unimplemented_device("riscv.sifive.u.l2cc",
|
2020-09-11 20:34:47 +03:00
|
|
|
memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
|
2018-03-02 15:31:14 +03:00
|
|
|
}
|
|
|
|
|
2020-05-21 17:42:26 +03:00
|
|
|
static Property sifive_u_soc_props[] = {
|
2020-03-03 02:08:51 +03:00
|
|
|
DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
|
2020-10-14 03:17:25 +03:00
|
|
|
DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
|
2020-03-03 02:08:51 +03:00
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
2020-05-21 17:42:26 +03:00
|
|
|
static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
|
2018-04-26 21:15:24 +03:00
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
2020-05-21 17:42:26 +03:00
|
|
|
device_class_set_props(dc, sifive_u_soc_props);
|
|
|
|
dc->realize = sifive_u_soc_realize;
|
2018-04-26 21:15:24 +03:00
|
|
|
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
|
|
|
|
dc->user_creatable = false;
|
|
|
|
}
|
|
|
|
|
2020-05-21 17:42:26 +03:00
|
|
|
static const TypeInfo sifive_u_soc_type_info = {
|
2018-04-26 21:15:24 +03:00
|
|
|
.name = TYPE_RISCV_U_SOC,
|
|
|
|
.parent = TYPE_DEVICE,
|
|
|
|
.instance_size = sizeof(SiFiveUSoCState),
|
2020-05-21 17:42:26 +03:00
|
|
|
.instance_init = sifive_u_soc_instance_init,
|
|
|
|
.class_init = sifive_u_soc_class_init,
|
2018-04-26 21:15:24 +03:00
|
|
|
};
|
|
|
|
|
2020-05-21 17:42:26 +03:00
|
|
|
static void sifive_u_soc_register_types(void)
|
2018-04-26 21:15:24 +03:00
|
|
|
{
|
2020-05-21 17:42:26 +03:00
|
|
|
type_register_static(&sifive_u_soc_type_info);
|
2018-04-26 21:15:24 +03:00
|
|
|
}
|
|
|
|
|
2020-05-21 17:42:26 +03:00
|
|
|
type_init(sifive_u_soc_register_types)
|