qemu/tcg/arm/tcg-target.opc.h

/*
 * Copyright (c) 2019 Linaro
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or
 * (at your option) any later version.
 *
 * See the COPYING file in the top-level directory for details.
 *
 * Target-specific opcodes for host vector expansion.  These will be
 * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
 * consider these to be UNSPEC with names.
 */

DEF(arm_sli_vec, 1, 2, 1, IMPLVEC)
DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
tcg/arm: Add host vector framework Add registers and function stubs. The functionality is disabled via use_neon_instructions defined to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2021-05-04 02:47:52 +03:00			`/*`
			`* Copyright (c) 2019 Linaro`
			`*`
			`* This work is licensed under the terms of the GNU GPL, version 2 or`
			`* (at your option) any later version.`
			`*`
			`* See the COPYING file in the top-level directory for details.`
			`*`
			`* Target-specific opcodes for host vector expansion. These will be`
			`* emitted by tcg_expand_vec_op. For those familiar with GCC internals,`
			`* consider these to be UNSPEC with names.`
			`*/`
tcg/arm: Implement TCG_TARGET_HAS_shv_vec The three vector shift by vector operations are all implemented via expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec, as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the instruction stream, and therefore also do not appear in tcg_target_op_def. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-09-05 23:13:10 +03:00
tcg/arm: Implement TCG_TARGET_HAS_roti_vec Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec. For NEON, this is shift-right followed by shift-left-and-insert. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-09-05 23:26:48 +03:00			`DEF(arm_sli_vec, 1, 2, 1, IMPLVEC)`
tcg/arm: Implement TCG_TARGET_HAS_shv_vec The three vector shift by vector operations are all implemented via expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec, as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the instruction stream, and therefore also do not appear in tcg_target_op_def. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-09-05 23:13:10 +03:00			`DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)`
			`DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)`