2004-03-14 15:20:30 +03:00
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/*
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* QEMU 8253/8254 interval timer emulation
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2007-09-17 01:08:06 +04:00
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*
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2004-03-14 15:20:30 +03:00
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* Copyright (c) 2003-2004 Fabrice Bellard
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2007-09-17 01:08:06 +04:00
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*
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2004-03-14 15:20:30 +03:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2007-11-17 20:14:51 +03:00
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#include "hw.h"
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#include "pc.h"
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#include "isa.h"
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#include "qemu-timer.h"
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2004-03-14 15:20:30 +03:00
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2004-03-31 22:58:38 +04:00
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//#define DEBUG_PIT
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2004-05-04 03:18:25 +04:00
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#define RW_STATE_LSB 1
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#define RW_STATE_MSB 2
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#define RW_STATE_WORD0 3
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#define RW_STATE_WORD1 4
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2004-03-14 15:20:30 +03:00
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2004-05-04 03:18:25 +04:00
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typedef struct PITChannelState {
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int count; /* can be 65536 */
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uint16_t latched_count;
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uint8_t count_latched;
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uint8_t status_latched;
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uint8_t status;
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uint8_t read_state;
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uint8_t write_state;
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uint8_t write_latch;
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uint8_t rw_mode;
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uint8_t mode;
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uint8_t bcd; /* not supported */
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uint8_t gate; /* timer start */
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int64_t count_load_time;
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/* irq handling */
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int64_t next_transition_time;
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QEMUTimer *irq_timer;
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2007-04-07 22:14:41 +04:00
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qemu_irq irq;
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2004-05-04 03:18:25 +04:00
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} PITChannelState;
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2011-02-13 22:54:40 +03:00
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typedef struct PITState {
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ISADevice dev;
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2011-08-11 02:28:15 +04:00
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MemoryRegion ioports;
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2011-02-13 22:54:40 +03:00
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uint32_t irq;
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uint32_t iobase;
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2004-05-04 03:18:25 +04:00
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PITChannelState channels[3];
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2011-02-13 22:54:40 +03:00
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} PITState;
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2004-05-04 03:18:25 +04:00
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static PITState pit_state;
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2004-03-14 15:20:30 +03:00
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2004-03-31 22:58:38 +04:00
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
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2004-03-14 15:20:30 +03:00
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static int pit_get_count(PITChannelState *s)
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{
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uint64_t d;
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int counter;
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2011-03-11 18:47:48 +03:00
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d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
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2009-09-10 05:04:26 +04:00
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get_ticks_per_sec());
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2004-03-14 15:20:30 +03:00
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switch(s->mode) {
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case 0:
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case 1:
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case 4:
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case 5:
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counter = (s->count - d) & 0xffff;
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break;
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case 3:
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/* XXX: may be incorrect for odd counts */
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counter = s->count - ((2 * d) % s->count);
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break;
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default:
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counter = s->count - (d % s->count);
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break;
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}
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return counter;
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}
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/* get pit output bit */
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2004-05-04 03:18:25 +04:00
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static int pit_get_out1(PITChannelState *s, int64_t current_time)
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2004-03-14 15:20:30 +03:00
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{
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uint64_t d;
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int out;
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2009-09-10 05:04:26 +04:00
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
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get_ticks_per_sec());
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2004-03-14 15:20:30 +03:00
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switch(s->mode) {
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default:
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case 0:
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out = (d >= s->count);
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break;
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case 1:
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out = (d < s->count);
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break;
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case 2:
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if ((d % s->count) == 0 && d != 0)
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out = 1;
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else
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out = 0;
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break;
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case 3:
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out = (d % s->count) < ((s->count + 1) >> 1);
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break;
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case 4:
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case 5:
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out = (d == s->count);
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break;
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}
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return out;
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}
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2011-02-13 22:54:40 +03:00
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int pit_get_out(ISADevice *dev, int channel, int64_t current_time)
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2004-05-04 03:18:25 +04:00
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{
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2011-02-13 22:54:40 +03:00
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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2004-05-04 03:18:25 +04:00
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PITChannelState *s = &pit->channels[channel];
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return pit_get_out1(s, current_time);
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}
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2004-03-31 22:58:38 +04:00
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/* return -1 if no transition will occur. */
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2007-09-17 01:08:06 +04:00
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static int64_t pit_get_next_transition_time(PITChannelState *s,
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2004-03-31 22:58:38 +04:00
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int64_t current_time)
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2004-03-14 15:20:30 +03:00
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{
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2004-03-31 22:58:38 +04:00
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uint64_t d, next_time, base;
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int period2;
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2004-03-14 15:20:30 +03:00
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2009-09-10 05:04:26 +04:00
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
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get_ticks_per_sec());
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2004-03-14 15:20:30 +03:00
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switch(s->mode) {
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default:
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case 0:
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case 1:
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2004-03-31 22:58:38 +04:00
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if (d < s->count)
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next_time = s->count;
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else
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return -1;
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2004-03-14 15:20:30 +03:00
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break;
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case 2:
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2004-03-31 22:58:38 +04:00
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base = (d / s->count) * s->count;
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if ((d - base) == 0 && d != 0)
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next_time = base + s->count;
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else
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next_time = base + s->count + 1;
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2004-03-14 15:20:30 +03:00
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break;
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case 3:
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2004-03-31 22:58:38 +04:00
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base = (d / s->count) * s->count;
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period2 = ((s->count + 1) >> 1);
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2007-09-17 01:08:06 +04:00
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if ((d - base) < period2)
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2004-03-31 22:58:38 +04:00
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next_time = base + period2;
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else
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next_time = base + s->count;
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2004-03-14 15:20:30 +03:00
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break;
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case 4:
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case 5:
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2004-03-31 22:58:38 +04:00
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if (d < s->count)
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next_time = s->count;
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else if (d == s->count)
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next_time = s->count + 1;
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2004-03-14 15:20:30 +03:00
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else
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2004-03-31 22:58:38 +04:00
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return -1;
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2004-03-14 15:20:30 +03:00
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break;
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}
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2004-03-31 22:58:38 +04:00
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/* convert to timer units */
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2009-09-10 05:04:26 +04:00
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next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(),
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PIT_FREQ);
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2004-04-03 00:58:56 +04:00
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/* fix potential rounding problems */
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/* XXX: better solution: use a clock at PIT_FREQ Hz */
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if (next_time <= current_time)
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next_time = current_time + 1;
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2004-03-31 22:58:38 +04:00
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return next_time;
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2004-03-14 15:20:30 +03:00
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}
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/* val must be 0 or 1 */
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2011-02-13 22:54:40 +03:00
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void pit_set_gate(ISADevice *dev, int channel, int val)
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2004-03-14 15:20:30 +03:00
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{
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2011-02-13 22:54:40 +03:00
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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2004-05-04 03:18:25 +04:00
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PITChannelState *s = &pit->channels[channel];
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2004-03-14 15:20:30 +03:00
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switch(s->mode) {
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default:
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case 0:
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case 4:
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/* XXX: just disable/enable counting */
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break;
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case 1:
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case 5:
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if (s->gate < val) {
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/* restart counting on rising edge */
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2011-03-11 18:47:48 +03:00
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s->count_load_time = qemu_get_clock_ns(vm_clock);
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2004-03-31 22:58:38 +04:00
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pit_irq_timer_update(s, s->count_load_time);
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2004-03-14 15:20:30 +03:00
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}
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break;
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case 2:
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case 3:
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if (s->gate < val) {
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/* restart counting on rising edge */
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2011-03-11 18:47:48 +03:00
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s->count_load_time = qemu_get_clock_ns(vm_clock);
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2004-03-31 22:58:38 +04:00
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pit_irq_timer_update(s, s->count_load_time);
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2004-03-14 15:20:30 +03:00
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}
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/* XXX: disable/enable counting */
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break;
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}
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s->gate = val;
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}
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2011-02-13 22:54:40 +03:00
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int pit_get_gate(ISADevice *dev, int channel)
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2004-05-04 03:18:25 +04:00
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{
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2011-02-13 22:54:40 +03:00
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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2004-05-04 03:18:25 +04:00
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PITChannelState *s = &pit->channels[channel];
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return s->gate;
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}
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2011-02-13 22:54:40 +03:00
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int pit_get_initial_count(ISADevice *dev, int channel)
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2006-04-25 01:58:30 +04:00
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{
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2011-02-13 22:54:40 +03:00
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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2006-04-25 01:58:30 +04:00
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PITChannelState *s = &pit->channels[channel];
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return s->count;
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}
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2011-02-13 22:54:40 +03:00
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int pit_get_mode(ISADevice *dev, int channel)
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2006-04-25 01:58:30 +04:00
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{
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2011-02-13 22:54:40 +03:00
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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2006-04-25 01:58:30 +04:00
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PITChannelState *s = &pit->channels[channel];
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return s->mode;
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}
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2004-03-14 15:20:30 +03:00
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static inline void pit_load_count(PITChannelState *s, int val)
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{
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if (val == 0)
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val = 0x10000;
|
2011-03-11 18:47:48 +03:00
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s->count_load_time = qemu_get_clock_ns(vm_clock);
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2004-03-14 15:20:30 +03:00
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s->count = val;
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2004-03-31 22:58:38 +04:00
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pit_irq_timer_update(s, s->count_load_time);
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2004-03-14 15:20:30 +03:00
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}
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2004-05-04 03:18:25 +04:00
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/* if already latched, do not latch again */
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static void pit_latch_count(PITChannelState *s)
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{
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if (!s->count_latched) {
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s->latched_count = pit_get_count(s);
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s->count_latched = s->rw_mode;
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}
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}
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2004-03-15 00:46:48 +03:00
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static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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2004-03-14 15:20:30 +03:00
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{
|
2004-05-04 03:18:25 +04:00
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PITState *pit = opaque;
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2004-03-14 15:20:30 +03:00
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int channel, access;
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PITChannelState *s;
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addr &= 3;
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if (addr == 3) {
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channel = val >> 6;
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2004-05-04 03:18:25 +04:00
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if (channel == 3) {
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/* read back command */
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for(channel = 0; channel < 3; channel++) {
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s = &pit->channels[channel];
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if (val & (2 << channel)) {
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if (!(val & 0x20)) {
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pit_latch_count(s);
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}
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if (!(val & 0x10) && !s->status_latched) {
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/* status latch */
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/* XXX: add BCD and null count */
|
2011-03-11 18:47:48 +03:00
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s->status = (pit_get_out1(s, qemu_get_clock_ns(vm_clock)) << 7) |
|
2004-05-04 03:18:25 +04:00
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(s->rw_mode << 4) |
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(s->mode << 1) |
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s->bcd;
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s->status_latched = 1;
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}
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}
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}
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} else {
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s = &pit->channels[channel];
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access = (val >> 4) & 3;
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if (access == 0) {
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pit_latch_count(s);
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} else {
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s->rw_mode = access;
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s->read_state = access;
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s->write_state = access;
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s->mode = (val >> 1) & 7;
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s->bcd = val & 1;
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|
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/* XXX: update irq timer ? */
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|
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}
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
|
|
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} else {
|
2004-05-04 03:18:25 +04:00
|
|
|
s = &pit->channels[addr];
|
|
|
|
switch(s->write_state) {
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|
|
|
default:
|
2004-03-14 15:20:30 +03:00
|
|
|
case RW_STATE_LSB:
|
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|
|
pit_load_count(s, val);
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|
|
break;
|
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|
|
case RW_STATE_MSB:
|
|
|
|
pit_load_count(s, val << 8);
|
|
|
|
break;
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|
|
|
case RW_STATE_WORD0:
|
2004-05-04 03:18:25 +04:00
|
|
|
s->write_latch = val;
|
|
|
|
s->write_state = RW_STATE_WORD1;
|
|
|
|
break;
|
2004-03-14 15:20:30 +03:00
|
|
|
case RW_STATE_WORD1:
|
2004-05-04 03:18:25 +04:00
|
|
|
pit_load_count(s, s->write_latch | (val << 8));
|
|
|
|
s->write_state = RW_STATE_WORD0;
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-03-15 00:46:48 +03:00
|
|
|
static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
|
2004-03-14 15:20:30 +03:00
|
|
|
{
|
2004-05-04 03:18:25 +04:00
|
|
|
PITState *pit = opaque;
|
2004-03-14 15:20:30 +03:00
|
|
|
int ret, count;
|
|
|
|
PITChannelState *s;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-03-14 15:20:30 +03:00
|
|
|
addr &= 3;
|
2004-05-04 03:18:25 +04:00
|
|
|
s = &pit->channels[addr];
|
|
|
|
if (s->status_latched) {
|
|
|
|
s->status_latched = 0;
|
|
|
|
ret = s->status;
|
|
|
|
} else if (s->count_latched) {
|
|
|
|
switch(s->count_latched) {
|
|
|
|
default:
|
|
|
|
case RW_STATE_LSB:
|
|
|
|
ret = s->latched_count & 0xff;
|
|
|
|
s->count_latched = 0;
|
|
|
|
break;
|
|
|
|
case RW_STATE_MSB:
|
2004-03-14 15:20:30 +03:00
|
|
|
ret = s->latched_count >> 8;
|
2004-05-04 03:18:25 +04:00
|
|
|
s->count_latched = 0;
|
|
|
|
break;
|
|
|
|
case RW_STATE_WORD0:
|
2004-03-14 15:20:30 +03:00
|
|
|
ret = s->latched_count & 0xff;
|
2004-05-04 03:18:25 +04:00
|
|
|
s->count_latched = RW_STATE_MSB;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch(s->read_state) {
|
|
|
|
default:
|
|
|
|
case RW_STATE_LSB:
|
|
|
|
count = pit_get_count(s);
|
|
|
|
ret = count & 0xff;
|
|
|
|
break;
|
|
|
|
case RW_STATE_MSB:
|
|
|
|
count = pit_get_count(s);
|
|
|
|
ret = (count >> 8) & 0xff;
|
|
|
|
break;
|
|
|
|
case RW_STATE_WORD0:
|
|
|
|
count = pit_get_count(s);
|
|
|
|
ret = count & 0xff;
|
|
|
|
s->read_state = RW_STATE_WORD1;
|
|
|
|
break;
|
|
|
|
case RW_STATE_WORD1:
|
|
|
|
count = pit_get_count(s);
|
|
|
|
ret = (count >> 8) & 0xff;
|
|
|
|
s->read_state = RW_STATE_WORD0;
|
|
|
|
break;
|
|
|
|
}
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-03-31 22:58:38 +04:00
|
|
|
static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
|
|
|
|
{
|
|
|
|
int64_t expire_time;
|
|
|
|
int irq_level;
|
|
|
|
|
|
|
|
if (!s->irq_timer)
|
|
|
|
return;
|
|
|
|
expire_time = pit_get_next_transition_time(s, current_time);
|
2004-05-04 03:18:25 +04:00
|
|
|
irq_level = pit_get_out1(s, current_time);
|
2007-04-07 22:14:41 +04:00
|
|
|
qemu_set_irq(s->irq, irq_level);
|
2004-03-31 22:58:38 +04:00
|
|
|
#ifdef DEBUG_PIT
|
|
|
|
printf("irq_level=%d next_delay=%f\n",
|
2007-09-17 01:08:06 +04:00
|
|
|
irq_level,
|
2009-09-10 05:04:26 +04:00
|
|
|
(double)(expire_time - current_time) / get_ticks_per_sec());
|
2004-03-31 22:58:38 +04:00
|
|
|
#endif
|
|
|
|
s->next_transition_time = expire_time;
|
|
|
|
if (expire_time != -1)
|
|
|
|
qemu_mod_timer(s->irq_timer, expire_time);
|
|
|
|
else
|
|
|
|
qemu_del_timer(s->irq_timer);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pit_irq_timer(void *opaque)
|
|
|
|
{
|
|
|
|
PITChannelState *s = opaque;
|
|
|
|
|
|
|
|
pit_irq_timer_update(s, s->next_transition_time);
|
|
|
|
}
|
|
|
|
|
2009-08-20 21:42:31 +04:00
|
|
|
static const VMStateDescription vmstate_pit_channel = {
|
|
|
|
.name = "pit channel",
|
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 2,
|
|
|
|
.minimum_version_id_old = 2,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_INT32(count, PITChannelState),
|
|
|
|
VMSTATE_UINT16(latched_count, PITChannelState),
|
|
|
|
VMSTATE_UINT8(count_latched, PITChannelState),
|
|
|
|
VMSTATE_UINT8(status_latched, PITChannelState),
|
|
|
|
VMSTATE_UINT8(status, PITChannelState),
|
|
|
|
VMSTATE_UINT8(read_state, PITChannelState),
|
|
|
|
VMSTATE_UINT8(write_state, PITChannelState),
|
|
|
|
VMSTATE_UINT8(write_latch, PITChannelState),
|
|
|
|
VMSTATE_UINT8(rw_mode, PITChannelState),
|
|
|
|
VMSTATE_UINT8(mode, PITChannelState),
|
|
|
|
VMSTATE_UINT8(bcd, PITChannelState),
|
|
|
|
VMSTATE_UINT8(gate, PITChannelState),
|
|
|
|
VMSTATE_INT64(count_load_time, PITChannelState),
|
|
|
|
VMSTATE_INT64(next_transition_time, PITChannelState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
2004-03-31 22:58:38 +04:00
|
|
|
}
|
2009-08-20 21:42:31 +04:00
|
|
|
};
|
2004-03-31 22:58:38 +04:00
|
|
|
|
2009-08-20 21:42:31 +04:00
|
|
|
static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
|
2004-03-31 22:58:38 +04:00
|
|
|
{
|
2004-05-04 03:18:25 +04:00
|
|
|
PITState *pit = opaque;
|
2004-03-31 22:58:38 +04:00
|
|
|
PITChannelState *s;
|
|
|
|
int i;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-03-31 22:58:38 +04:00
|
|
|
if (version_id != 1)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
for(i = 0; i < 3; i++) {
|
2004-05-04 03:18:25 +04:00
|
|
|
s = &pit->channels[i];
|
2007-12-17 02:41:11 +03:00
|
|
|
s->count=qemu_get_be32(f);
|
2004-03-31 22:58:38 +04:00
|
|
|
qemu_get_be16s(f, &s->latched_count);
|
2004-05-04 03:18:25 +04:00
|
|
|
qemu_get_8s(f, &s->count_latched);
|
|
|
|
qemu_get_8s(f, &s->status_latched);
|
|
|
|
qemu_get_8s(f, &s->status);
|
|
|
|
qemu_get_8s(f, &s->read_state);
|
|
|
|
qemu_get_8s(f, &s->write_state);
|
|
|
|
qemu_get_8s(f, &s->write_latch);
|
|
|
|
qemu_get_8s(f, &s->rw_mode);
|
2004-03-31 22:58:38 +04:00
|
|
|
qemu_get_8s(f, &s->mode);
|
|
|
|
qemu_get_8s(f, &s->bcd);
|
|
|
|
qemu_get_8s(f, &s->gate);
|
2007-12-17 02:41:11 +03:00
|
|
|
s->count_load_time=qemu_get_be64(f);
|
2004-03-31 22:58:38 +04:00
|
|
|
if (s->irq_timer) {
|
2007-12-17 02:41:11 +03:00
|
|
|
s->next_transition_time=qemu_get_be64(f);
|
2004-03-31 22:58:38 +04:00
|
|
|
qemu_get_timer(f, s->irq_timer);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-08-20 21:42:31 +04:00
|
|
|
static const VMStateDescription vmstate_pit = {
|
|
|
|
.name = "i8254",
|
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 2,
|
|
|
|
.minimum_version_id_old = 1,
|
|
|
|
.load_state_old = pit_load_old,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState),
|
|
|
|
VMSTATE_TIMER(channels[0].irq_timer, PITState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2011-02-13 22:54:40 +03:00
|
|
|
static void pit_reset(DeviceState *dev)
|
2004-03-14 15:20:30 +03:00
|
|
|
{
|
2011-02-13 22:54:40 +03:00
|
|
|
PITState *pit = container_of(dev, PITState, dev.qdev);
|
2004-03-14 15:20:30 +03:00
|
|
|
PITChannelState *s;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for(i = 0;i < 3; i++) {
|
2004-05-04 03:18:25 +04:00
|
|
|
s = &pit->channels[i];
|
2004-03-14 15:20:30 +03:00
|
|
|
s->mode = 3;
|
|
|
|
s->gate = (i != 2);
|
|
|
|
pit_load_count(s, 0);
|
|
|
|
}
|
2004-06-20 16:58:36 +04:00
|
|
|
}
|
|
|
|
|
2008-12-18 02:28:44 +03:00
|
|
|
/* When HPET is operating in legacy mode, i8254 timer0 is disabled */
|
|
|
|
void hpet_pit_disable(void) {
|
|
|
|
PITChannelState *s;
|
|
|
|
s = &pit_state.channels[0];
|
2009-01-26 23:32:18 +03:00
|
|
|
if (s->irq_timer)
|
|
|
|
qemu_del_timer(s->irq_timer);
|
2008-12-18 02:28:44 +03:00
|
|
|
}
|
|
|
|
|
2008-12-19 01:42:43 +03:00
|
|
|
/* When HPET is reset or leaving legacy mode, it must reenable i8254
|
2008-12-18 02:28:44 +03:00
|
|
|
* timer 0
|
|
|
|
*/
|
|
|
|
|
|
|
|
void hpet_pit_enable(void)
|
|
|
|
{
|
|
|
|
PITState *pit = &pit_state;
|
|
|
|
PITChannelState *s;
|
|
|
|
s = &pit->channels[0];
|
|
|
|
s->mode = 3;
|
|
|
|
s->gate = 1;
|
|
|
|
pit_load_count(s, 0);
|
|
|
|
}
|
|
|
|
|
2011-08-11 02:28:15 +04:00
|
|
|
static const MemoryRegionPortio pit_portio[] = {
|
|
|
|
{ 0, 4, 1, .write = pit_ioport_write },
|
|
|
|
{ 0, 3, 1, .read = pit_ioport_read },
|
|
|
|
PORTIO_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps pit_ioport_ops = {
|
|
|
|
.old_portio = pit_portio
|
|
|
|
};
|
|
|
|
|
2011-02-13 22:54:40 +03:00
|
|
|
static int pit_initfn(ISADevice *dev)
|
2004-06-20 16:58:36 +04:00
|
|
|
{
|
2011-02-13 22:54:40 +03:00
|
|
|
PITState *pit = DO_UPCAST(PITState, dev, dev);
|
2004-06-20 16:58:36 +04:00
|
|
|
PITChannelState *s;
|
|
|
|
|
|
|
|
s = &pit->channels[0];
|
|
|
|
/* the timer 0 is connected to an IRQ */
|
2011-03-11 18:47:48 +03:00
|
|
|
s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
|
2011-02-19 20:56:22 +03:00
|
|
|
s->irq = isa_get_irq(pit->irq);
|
2004-03-14 15:20:30 +03:00
|
|
|
|
2011-08-11 02:28:15 +04:00
|
|
|
memory_region_init_io(&pit->ioports, &pit_ioport_ops, pit, "pit", 4);
|
|
|
|
isa_register_ioport(dev, &pit->ioports, pit->iobase);
|
2004-06-20 16:58:36 +04:00
|
|
|
|
2011-03-06 18:09:49 +03:00
|
|
|
qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2);
|
|
|
|
|
2011-02-13 22:54:40 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ISADeviceInfo pit_info = {
|
|
|
|
.qdev.name = "isa-pit",
|
|
|
|
.qdev.size = sizeof(PITState),
|
|
|
|
.qdev.vmsd = &vmstate_pit,
|
|
|
|
.qdev.reset = pit_reset,
|
|
|
|
.qdev.no_user = 1,
|
|
|
|
.init = pit_initfn,
|
|
|
|
.qdev.props = (Property[]) {
|
|
|
|
DEFINE_PROP_UINT32("irq", PITState, irq, -1),
|
|
|
|
DEFINE_PROP_HEX32("iobase", PITState, iobase, -1),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static void pit_register(void)
|
|
|
|
{
|
|
|
|
isa_qdev_register(&pit_info);
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
2011-02-13 22:54:40 +03:00
|
|
|
device_init(pit_register)
|