use new timer API
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@689 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
dff38e7b40
commit
b0a21b5334
172
hw/i8254.c
172
hw/i8254.c
@ -43,6 +43,8 @@
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#include "cpu.h"
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#include "vl.h"
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//#define DEBUG_PIT
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#define RW_STATE_LSB 0
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#define RW_STATE_MSB 1
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#define RW_STATE_WORD0 2
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@ -52,12 +54,14 @@
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PITChannelState pit_channels[3];
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
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static int pit_get_count(PITChannelState *s)
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{
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uint64_t d;
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int counter;
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d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
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d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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case 0:
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case 1:
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@ -77,12 +81,12 @@ static int pit_get_count(PITChannelState *s)
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}
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/* get pit output bit */
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int pit_get_out(PITChannelState *s)
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int pit_get_out(PITChannelState *s, int64_t current_time)
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{
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uint64_t d;
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int out;
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d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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default:
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case 0:
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@ -108,53 +112,51 @@ int pit_get_out(PITChannelState *s)
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return out;
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}
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/* get the number of 0 to 1 transitions we had since we call this
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function */
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/* XXX: maybe better to use ticks precision to avoid getting edges
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twice if checks are done at very small intervals */
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int pit_get_out_edges(PITChannelState *s)
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/* return -1 if no transition will occur. */
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static int64_t pit_get_next_transition_time(PITChannelState *s,
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int64_t current_time)
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{
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uint64_t d1, d2;
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int64_t ticks;
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int ret, v;
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uint64_t d, next_time, base;
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int period2;
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ticks = cpu_get_ticks();
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d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
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PIT_FREQ, ticks_per_sec);
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d2 = muldiv64(ticks - s->count_load_time,
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PIT_FREQ, ticks_per_sec);
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s->count_last_edge_check_time = ticks;
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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default:
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case 0:
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if (d1 < s->count && d2 >= s->count)
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ret = 1;
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else
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ret = 0;
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break;
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case 1:
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ret = 0;
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if (d < s->count)
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next_time = s->count;
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else
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return -1;
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break;
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case 2:
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d1 /= s->count;
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d2 /= s->count;
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ret = d2 - d1;
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base = (d / s->count) * s->count;
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if ((d - base) == 0 && d != 0)
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next_time = base + s->count;
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else
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next_time = base + s->count + 1;
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break;
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case 3:
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v = s->count - ((s->count + 1) >> 1);
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d1 = (d1 + v) / s->count;
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d2 = (d2 + v) / s->count;
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ret = d2 - d1;
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base = (d / s->count) * s->count;
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period2 = ((s->count + 1) >> 1);
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if ((d - base) < period2)
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next_time = base + period2;
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else
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next_time = base + s->count;
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break;
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case 4:
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case 5:
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if (d1 < s->count && d2 >= s->count)
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ret = 1;
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if (d < s->count)
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next_time = s->count;
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else if (d == s->count)
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next_time = s->count + 1;
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else
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ret = 0;
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return -1;
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break;
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}
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return ret;
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/* convert to timer units */
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next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
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return next_time;
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}
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/* val must be 0 or 1 */
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@ -170,16 +172,16 @@ void pit_set_gate(PITChannelState *s, int val)
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case 5:
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if (s->gate < val) {
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/* restart counting on rising edge */
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s->count_load_time = cpu_get_ticks();
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s->count_last_edge_check_time = s->count_load_time;
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s->count_load_time = qemu_get_clock(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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}
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break;
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case 2:
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case 3:
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if (s->gate < val) {
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/* restart counting on rising edge */
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s->count_load_time = cpu_get_ticks();
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s->count_last_edge_check_time = s->count_load_time;
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s->count_load_time = qemu_get_clock(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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}
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/* XXX: disable/enable counting */
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break;
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@ -191,14 +193,9 @@ static inline void pit_load_count(PITChannelState *s, int val)
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{
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if (val == 0)
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val = 0x10000;
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s->count_load_time = cpu_get_ticks();
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s->count_last_edge_check_time = s->count_load_time;
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s->count_load_time = qemu_get_clock(vm_clock);
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s->count = val;
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if (s == &pit_channels[0] && val <= pit_min_timer_count) {
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fprintf(stderr,
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"\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.6 guest Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
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PIT_FREQ / pit_min_timer_count);
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}
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pit_irq_timer_update(s, s->count_load_time);
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}
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static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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@ -222,6 +219,7 @@ static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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s->mode = (val >> 1) & 7;
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s->bcd = val & 1;
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s->rw_state = access - 1 + RW_STATE_LSB;
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/* XXX: update irq timer ? */
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break;
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}
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} else {
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@ -279,18 +277,100 @@ static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
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return ret;
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}
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void pit_init(int base)
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
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{
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int64_t expire_time;
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int irq_level;
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if (!s->irq_timer)
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return;
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expire_time = pit_get_next_transition_time(s, current_time);
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irq_level = pit_get_out(s, current_time);
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pic_set_irq(s->irq, irq_level);
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#ifdef DEBUG_PIT
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printf("irq_level=%d next_delay=%f\n",
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irq_level,
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(double)(expire_time - current_time) / ticks_per_sec);
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#endif
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s->next_transition_time = expire_time;
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if (expire_time != -1)
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qemu_mod_timer(s->irq_timer, expire_time);
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else
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qemu_del_timer(s->irq_timer);
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}
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static void pit_irq_timer(void *opaque)
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{
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PITChannelState *s = opaque;
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pit_irq_timer_update(s, s->next_transition_time);
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}
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static void pit_save(QEMUFile *f, void *opaque)
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{
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PITChannelState *s;
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int i;
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for(i = 0; i < 3; i++) {
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s = &pit_channels[i];
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qemu_put_be32s(f, &s->count);
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qemu_put_be16s(f, &s->latched_count);
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qemu_put_8s(f, &s->rw_state);
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qemu_put_8s(f, &s->mode);
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qemu_put_8s(f, &s->bcd);
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qemu_put_8s(f, &s->gate);
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qemu_put_be64s(f, &s->count_load_time);
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if (s->irq_timer) {
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qemu_put_be64s(f, &s->next_transition_time);
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qemu_put_timer(f, s->irq_timer);
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}
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}
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}
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static int pit_load(QEMUFile *f, void *opaque, int version_id)
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{
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PITChannelState *s;
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int i;
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if (version_id != 1)
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return -EINVAL;
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for(i = 0; i < 3; i++) {
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s = &pit_channels[i];
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qemu_get_be32s(f, &s->count);
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qemu_get_be16s(f, &s->latched_count);
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qemu_get_8s(f, &s->rw_state);
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qemu_get_8s(f, &s->mode);
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qemu_get_8s(f, &s->bcd);
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qemu_get_8s(f, &s->gate);
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qemu_get_be64s(f, &s->count_load_time);
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if (s->irq_timer) {
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qemu_get_be64s(f, &s->next_transition_time);
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qemu_get_timer(f, s->irq_timer);
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}
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}
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return 0;
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}
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void pit_init(int base, int irq)
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{
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PITChannelState *s;
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int i;
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for(i = 0;i < 3; i++) {
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s = &pit_channels[i];
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if (i == 0) {
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/* the timer 0 is connected to an IRQ */
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s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
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s->irq = irq;
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}
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s->mode = 3;
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s->gate = (i != 2);
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pit_load_count(s, 0);
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}
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register_savevm("i8254", base, 1, pit_save, pit_load, NULL);
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register_ioport_write(base, 4, 1, pit_ioport_write, NULL);
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register_ioport_read(base, 3, 1, pit_ioport_read, NULL);
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}
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64
hw/i8259.c
64
hw/i8259.c
@ -122,7 +122,7 @@ static int pic_get_irq(PicState *s)
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/* raise irq to CPU if necessary. must be called every time the active
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irq may change */
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void pic_update_irq(void)
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static void pic_update_irq(void)
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{
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int irq2, irq;
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@ -160,7 +160,6 @@ void pic_update_irq(void)
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#ifdef DEBUG_IRQ_LATENCY
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int64_t irq_time[16];
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int64_t cpu_get_ticks(void);
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#endif
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#if defined(DEBUG_PIC)
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int irq_level[16];
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@ -376,11 +375,62 @@ uint32_t pic_intack_read(CPUState *env)
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return ret;
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}
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void pic_init(void)
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static void pic_save(QEMUFile *f, void *opaque)
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{
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register_ioport_write(0x20, 2, 1, pic_ioport_write, &pics[0]);
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register_ioport_read(0x20, 2, 1, pic_ioport_read, &pics[0]);
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register_ioport_write(0xa0, 2, 1, pic_ioport_write, &pics[1]);
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register_ioport_read(0xa0, 2, 1, pic_ioport_read, &pics[1]);
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PicState *s = opaque;
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qemu_put_8s(f, &s->last_irr);
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qemu_put_8s(f, &s->irr);
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qemu_put_8s(f, &s->imr);
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qemu_put_8s(f, &s->isr);
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qemu_put_8s(f, &s->priority_add);
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qemu_put_8s(f, &s->irq_base);
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qemu_put_8s(f, &s->read_reg_select);
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qemu_put_8s(f, &s->poll);
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qemu_put_8s(f, &s->special_mask);
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qemu_put_8s(f, &s->init_state);
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qemu_put_8s(f, &s->auto_eoi);
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qemu_put_8s(f, &s->rotate_on_auto_eoi);
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qemu_put_8s(f, &s->special_fully_nested_mode);
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qemu_put_8s(f, &s->init4);
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}
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static int pic_load(QEMUFile *f, void *opaque, int version_id)
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{
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PicState *s = opaque;
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if (version_id != 1)
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return -EINVAL;
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qemu_get_8s(f, &s->last_irr);
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qemu_get_8s(f, &s->irr);
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qemu_get_8s(f, &s->imr);
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qemu_get_8s(f, &s->isr);
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qemu_get_8s(f, &s->priority_add);
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qemu_get_8s(f, &s->irq_base);
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qemu_get_8s(f, &s->read_reg_select);
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qemu_get_8s(f, &s->poll);
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qemu_get_8s(f, &s->special_mask);
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qemu_get_8s(f, &s->init_state);
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qemu_get_8s(f, &s->auto_eoi);
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qemu_get_8s(f, &s->rotate_on_auto_eoi);
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qemu_get_8s(f, &s->special_fully_nested_mode);
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qemu_get_8s(f, &s->init4);
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return 0;
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}
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/* XXX: add generic master/slave system */
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static void pic_init1(int io_addr, PicState *s)
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{
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register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
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register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
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register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
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}
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void pic_init(void)
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{
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pic_init1(0x20, &pics[0]);
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pic_init1(0xa0, &pics[1]);
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}
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@ -471,5 +471,5 @@ void ne2000_init(int base, int irq, NetDriverState *nd)
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ne2000_reset(s);
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add_fd_read_handler(nd->fd, ne2000_can_receive, ne2000_receive, s);
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qemu_add_fd_read_handler(nd->fd, ne2000_can_receive, ne2000_receive, s);
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}
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78
hw/pc.c
78
hw/pc.c
@ -58,50 +58,69 @@
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int speaker_data_on;
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int dummy_refresh_clock;
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static fdctrl_t *floppy_controller;
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static RTCState *rtc_state;
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
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{
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}
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE 0x14
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#define REG_IBM_CENTURY_BYTE 0x32
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#define REG_IBM_PS2_CENTURY_BYTE 0x37
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static inline int to_bcd(RTCState *s, int a)
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{
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return ((a / 10) << 4) | (a % 10);
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}
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static void cmos_init(int ram_size, int boot_device)
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{
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RTCState *s = &rtc_state;
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RTCState *s = rtc_state;
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int val;
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int fd0, fd1, nb;
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/* various important CMOS locations needed by PC/Bochs bios */
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time_t ti;
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struct tm *tm;
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s->cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
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s->cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */
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/* set the CMOS date */
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time(&ti);
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tm = gmtime(&ti);
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rtc_set_date(s, tm);
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val = to_bcd(s, (tm->tm_year / 100) + 19);
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rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
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rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
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/* various important CMOS locations needed by PC/Bochs bios */
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/* memory size */
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val = (ram_size / 1024) - 1024;
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if (val > 65535)
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val = 65535;
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s->cmos_data[0x17] = val;
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s->cmos_data[0x18] = val >> 8;
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s->cmos_data[0x30] = val;
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s->cmos_data[0x31] = val >> 8;
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rtc_set_memory(s, 0x17, val);
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rtc_set_memory(s, 0x18, val >> 8);
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rtc_set_memory(s, 0x30, val);
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rtc_set_memory(s, 0x31, val >> 8);
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val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
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if (val > 65535)
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val = 65535;
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s->cmos_data[0x34] = val;
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s->cmos_data[0x35] = val >> 8;
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rtc_set_memory(s, 0x34, val);
|
||||
rtc_set_memory(s, 0x35, val >> 8);
|
||||
|
||||
switch(boot_device) {
|
||||
case 'a':
|
||||
case 'b':
|
||||
s->cmos_data[0x3d] = 0x01; /* floppy boot */
|
||||
rtc_set_memory(s, 0x3d, 0x01); /* floppy boot */
|
||||
break;
|
||||
default:
|
||||
case 'c':
|
||||
s->cmos_data[0x3d] = 0x02; /* hard drive boot */
|
||||
rtc_set_memory(s, 0x3d, 0x02); /* hard drive boot */
|
||||
break;
|
||||
case 'd':
|
||||
s->cmos_data[0x3d] = 0x03; /* CD-ROM boot */
|
||||
rtc_set_memory(s, 0x3d, 0x03); /* CD-ROM boot */
|
||||
break;
|
||||
}
|
||||
|
||||
@ -110,35 +129,38 @@ static void cmos_init(int ram_size, int boot_device)
|
||||
fd0 = fdctrl_get_drive_type(floppy_controller, 0);
|
||||
fd1 = fdctrl_get_drive_type(floppy_controller, 1);
|
||||
|
||||
s->cmos_data[0x10] = 0;
|
||||
val = 0;
|
||||
switch (fd0) {
|
||||
case 0:
|
||||
/* 1.44 Mb 3"5 drive */
|
||||
s->cmos_data[0x10] |= 0x40;
|
||||
val |= 0x40;
|
||||
break;
|
||||
case 1:
|
||||
/* 2.88 Mb 3"5 drive */
|
||||
s->cmos_data[0x10] |= 0x60;
|
||||
val |= 0x60;
|
||||
break;
|
||||
case 2:
|
||||
/* 1.2 Mb 5"5 drive */
|
||||
s->cmos_data[0x10] |= 0x20;
|
||||
val |= 0x20;
|
||||
break;
|
||||
}
|
||||
switch (fd1) {
|
||||
case 0:
|
||||
/* 1.44 Mb 3"5 drive */
|
||||
s->cmos_data[0x10] |= 0x04;
|
||||
val |= 0x04;
|
||||
break;
|
||||
case 1:
|
||||
/* 2.88 Mb 3"5 drive */
|
||||
s->cmos_data[0x10] |= 0x06;
|
||||
val |= 0x06;
|
||||
break;
|
||||
case 2:
|
||||
/* 1.2 Mb 5"5 drive */
|
||||
s->cmos_data[0x10] |= 0x02;
|
||||
val |= 0x02;
|
||||
break;
|
||||
}
|
||||
rtc_set_memory(s, 0x10, val);
|
||||
|
||||
val = 0;
|
||||
nb = 0;
|
||||
if (fd0 < 3)
|
||||
nb++;
|
||||
@ -148,12 +170,16 @@ static void cmos_init(int ram_size, int boot_device)
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
s->cmos_data[REG_EQUIPMENT_BYTE] |= 0x01; /* 1 drive, ready for boot */
|
||||
val |= 0x01; /* 1 drive, ready for boot */
|
||||
break;
|
||||
case 2:
|
||||
s->cmos_data[REG_EQUIPMENT_BYTE] |= 0x41; /* 2 drives, ready for boot */
|
||||
val |= 0x41; /* 2 drives, ready for boot */
|
||||
break;
|
||||
}
|
||||
val |= 0x02; /* FPU is there */
|
||||
val |= 0x04; /* PS/2 mouse installed */
|
||||
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
|
||||
|
||||
}
|
||||
|
||||
static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
|
||||
@ -165,7 +191,7 @@ static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
|
||||
static uint32_t speaker_ioport_read(void *opaque, uint32_t addr)
|
||||
{
|
||||
int out;
|
||||
out = pit_get_out(&pit_channels[2]);
|
||||
out = pit_get_out(&pit_channels[2], qemu_get_clock(vm_clock));
|
||||
dummy_refresh_clock ^= 1;
|
||||
return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
|
||||
(dummy_refresh_clock << 4);
|
||||
@ -345,12 +371,12 @@ void pc_init(int ram_size, int vga_ram_size, int boot_device,
|
||||
vga_initialize(ds, phys_ram_base + ram_size, ram_size,
|
||||
vga_ram_size);
|
||||
|
||||
rtc_init(0x70, 8);
|
||||
rtc_state = rtc_init(0x70, 8);
|
||||
register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
|
||||
register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
|
||||
|
||||
pic_init();
|
||||
pit_init(0x40);
|
||||
pit_init(0x40, 0);
|
||||
|
||||
fd = serial_open_device();
|
||||
serial_init(0x3f8, 4, fd);
|
||||
|
||||
@ -288,7 +288,7 @@ SerialState *serial_init(int base, int irq, int fd)
|
||||
register_ioport_read(base, 8, 1, serial_ioport_read, s);
|
||||
|
||||
if (fd != 0) {
|
||||
add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s);
|
||||
qemu_add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s);
|
||||
s->out_fd = fd;
|
||||
} else {
|
||||
serial_console = s;
|
||||
|
||||
94
hw/vga.c
94
hw/vga.c
@ -1578,6 +1578,98 @@ static CPUWriteMemoryFunc *vga_mem_write[3] = {
|
||||
vga_mem_writel,
|
||||
};
|
||||
|
||||
static void vga_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
VGAState *s = opaque;
|
||||
int i;
|
||||
|
||||
qemu_put_be32s(f, &s->latch);
|
||||
qemu_put_8s(f, &s->sr_index);
|
||||
qemu_put_buffer(f, s->sr, 8);
|
||||
qemu_put_8s(f, &s->gr_index);
|
||||
qemu_put_buffer(f, s->gr, 16);
|
||||
qemu_put_8s(f, &s->ar_index);
|
||||
qemu_put_buffer(f, s->ar, 21);
|
||||
qemu_put_be32s(f, &s->ar_flip_flop);
|
||||
qemu_put_8s(f, &s->cr_index);
|
||||
qemu_put_buffer(f, s->cr, 256);
|
||||
qemu_put_8s(f, &s->msr);
|
||||
qemu_put_8s(f, &s->fcr);
|
||||
qemu_put_8s(f, &s->st00);
|
||||
qemu_put_8s(f, &s->st01);
|
||||
|
||||
qemu_put_8s(f, &s->dac_state);
|
||||
qemu_put_8s(f, &s->dac_sub_index);
|
||||
qemu_put_8s(f, &s->dac_read_index);
|
||||
qemu_put_8s(f, &s->dac_write_index);
|
||||
qemu_put_buffer(f, s->dac_cache, 3);
|
||||
qemu_put_buffer(f, s->palette, 768);
|
||||
|
||||
qemu_put_be32s(f, &s->bank_offset);
|
||||
#ifdef CONFIG_BOCHS_VBE
|
||||
qemu_put_byte(f, 1);
|
||||
qemu_put_be16s(f, &s->vbe_index);
|
||||
for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
|
||||
qemu_put_be16s(f, &s->vbe_regs[i]);
|
||||
qemu_put_be32s(f, &s->vbe_start_addr);
|
||||
qemu_put_be32s(f, &s->vbe_line_offset);
|
||||
qemu_put_be32s(f, &s->vbe_bank_mask);
|
||||
#else
|
||||
qemu_put_byte(f, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static int vga_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
VGAState *s = opaque;
|
||||
int is_vbe, i;
|
||||
|
||||
if (version_id != 1)
|
||||
return -EINVAL;
|
||||
|
||||
qemu_get_be32s(f, &s->latch);
|
||||
qemu_get_8s(f, &s->sr_index);
|
||||
qemu_get_buffer(f, s->sr, 8);
|
||||
qemu_get_8s(f, &s->gr_index);
|
||||
qemu_get_buffer(f, s->gr, 16);
|
||||
qemu_get_8s(f, &s->ar_index);
|
||||
qemu_get_buffer(f, s->ar, 21);
|
||||
qemu_get_be32s(f, &s->ar_flip_flop);
|
||||
qemu_get_8s(f, &s->cr_index);
|
||||
qemu_get_buffer(f, s->cr, 256);
|
||||
qemu_get_8s(f, &s->msr);
|
||||
qemu_get_8s(f, &s->fcr);
|
||||
qemu_get_8s(f, &s->st00);
|
||||
qemu_get_8s(f, &s->st01);
|
||||
|
||||
qemu_get_8s(f, &s->dac_state);
|
||||
qemu_get_8s(f, &s->dac_sub_index);
|
||||
qemu_get_8s(f, &s->dac_read_index);
|
||||
qemu_get_8s(f, &s->dac_write_index);
|
||||
qemu_get_buffer(f, s->dac_cache, 3);
|
||||
qemu_get_buffer(f, s->palette, 768);
|
||||
|
||||
qemu_get_be32s(f, &s->bank_offset);
|
||||
is_vbe = qemu_get_byte(f);
|
||||
#ifdef CONFIG_BOCHS_VBE
|
||||
if (!is_vbe)
|
||||
return -EINVAL;
|
||||
qemu_get_be16s(f, &s->vbe_index);
|
||||
for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
|
||||
qemu_get_be16s(f, &s->vbe_regs[i]);
|
||||
qemu_get_be32s(f, &s->vbe_start_addr);
|
||||
qemu_get_be32s(f, &s->vbe_line_offset);
|
||||
qemu_get_be32s(f, &s->vbe_bank_mask);
|
||||
#else
|
||||
if (is_vbe)
|
||||
return -EINVAL;
|
||||
#endif
|
||||
|
||||
/* force refresh */
|
||||
s->graphic_mode = -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
|
||||
unsigned long vga_ram_offset, int vga_ram_size)
|
||||
{
|
||||
@ -1614,6 +1706,8 @@ int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
|
||||
s->vram_size = vga_ram_size;
|
||||
s->ds = ds;
|
||||
|
||||
register_savevm("vga", 0, 1, vga_save, vga_load, s);
|
||||
|
||||
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
|
||||
|
||||
register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user