2004-03-14 15:20:30 +03:00
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/*
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2008-08-11 18:17:04 +04:00
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* QEMU 16550A UART emulation
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2007-09-17 01:08:06 +04:00
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*
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2004-03-14 15:20:30 +03:00
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* Copyright (c) 2003-2004 Fabrice Bellard
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2008-08-11 18:17:04 +04:00
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* Copyright (c) 2008 Citrix Systems, Inc.
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2007-09-17 01:08:06 +04:00
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*
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2004-03-14 15:20:30 +03:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2012-10-17 11:54:19 +04:00
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2013-02-05 20:06:20 +04:00
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#include "hw/char/serial.h"
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2013-04-08 18:55:25 +04:00
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#include "sysemu/char.h"
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2012-12-17 21:20:00 +04:00
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#include "qemu/timer.h"
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2012-12-17 21:19:49 +04:00
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#include "exec/address-spaces.h"
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2004-03-14 15:20:30 +03:00
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//#define DEBUG_SERIAL
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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2008-08-11 18:17:04 +04:00
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#define UART_IIR_CTI 0x0C /* Character Timeout Indication */
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#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
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#define UART_IIR_FE 0xC0 /* Fifo enabled */
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2004-03-14 15:20:30 +03:00
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_OUT1 0x04 /* Out1 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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#define UART_LSR_FE 0x08 /* Frame error indicator */
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#define UART_LSR_PE 0x04 /* Parity error indicator */
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#define UART_LSR_OE 0x02 /* Overrun error indicator */
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#define UART_LSR_DR 0x01 /* Receiver data ready */
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2008-08-11 18:17:04 +04:00
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#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
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2004-03-14 15:20:30 +03:00
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2008-08-11 18:17:04 +04:00
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/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
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#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
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#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
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#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
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#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
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#define UART_FCR_DMS 0x08 /* DMA Mode Select */
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#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
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#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
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#define UART_FCR_FE 0x01 /* FIFO Enable */
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#define MAX_XMIT_RETRY 4
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2010-09-13 16:32:32 +04:00
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#ifdef DEBUG_SERIAL
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#define DPRINTF(fmt, ...) \
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2010-09-13 23:21:57 +04:00
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do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
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2010-09-13 16:32:32 +04:00
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#else
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#define DPRINTF(fmt, ...) \
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2010-09-13 23:21:57 +04:00
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do {} while (0)
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2010-09-13 16:32:32 +04:00
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#endif
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2008-08-11 18:17:04 +04:00
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static void serial_receive1(void *opaque, const uint8_t *buf, int size);
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2008-02-10 16:40:52 +03:00
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2013-06-03 09:13:27 +04:00
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static inline void recv_fifo_put(SerialState *s, uint8_t chr)
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2004-03-14 15:20:30 +03:00
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{
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2010-02-11 00:35:54 +03:00
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/* Receive overruns do not overwrite FIFO contents. */
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2013-06-03 09:13:27 +04:00
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if (!fifo8_is_full(&s->recv_fifo)) {
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fifo8_push(&s->recv_fifo, chr);
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} else {
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2010-02-11 00:35:54 +03:00
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s->lsr |= UART_LSR_OE;
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2013-06-03 09:13:27 +04:00
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}
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2008-08-11 18:17:04 +04:00
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}
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2008-05-05 01:42:00 +04:00
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2008-08-11 18:17:04 +04:00
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static void serial_update_irq(SerialState *s)
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{
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uint8_t tmp_iir = UART_IIR_NO_INT;
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if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
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tmp_iir = UART_IIR_RLSI;
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2008-09-17 04:21:05 +04:00
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} else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
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2008-09-20 05:15:04 +04:00
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/* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
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* this is not in the specification but is observed on existing
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* hardware. */
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2008-08-11 18:17:04 +04:00
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tmp_iir = UART_IIR_CTI;
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2009-09-12 20:52:22 +04:00
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} else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
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(!(s->fcr & UART_FCR_FE) ||
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2013-06-03 09:13:27 +04:00
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s->recv_fifo.num >= s->recv_fifo_itl)) {
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2009-09-12 20:52:22 +04:00
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tmp_iir = UART_IIR_RDI;
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2008-08-11 18:17:04 +04:00
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} else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
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tmp_iir = UART_IIR_THRI;
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} else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
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tmp_iir = UART_IIR_MSI;
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}
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s->iir = tmp_iir | (s->iir & 0xF0);
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if (tmp_iir != UART_IIR_NO_INT) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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2008-05-05 01:42:00 +04:00
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}
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}
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2005-11-09 01:30:36 +03:00
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static void serial_update_parameters(SerialState *s)
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{
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2008-08-11 18:17:04 +04:00
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int speed, parity, data_bits, stop_bits, frame_size;
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2005-11-11 02:58:33 +03:00
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QEMUSerialSetParams ssp;
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2005-11-09 01:30:36 +03:00
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2008-08-11 18:17:04 +04:00
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if (s->divider == 0)
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return;
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2009-10-26 23:51:41 +03:00
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/* Start bit. */
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2008-08-11 18:17:04 +04:00
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frame_size = 1;
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2005-11-09 01:30:36 +03:00
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if (s->lcr & 0x08) {
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2009-10-26 23:51:41 +03:00
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/* Parity bit. */
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frame_size++;
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2005-11-09 01:30:36 +03:00
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if (s->lcr & 0x10)
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parity = 'E';
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else
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parity = 'O';
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} else {
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parity = 'N';
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}
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2007-09-17 01:08:06 +04:00
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if (s->lcr & 0x04)
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2005-11-09 01:30:36 +03:00
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stop_bits = 2;
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else
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stop_bits = 1;
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2008-08-11 18:17:04 +04:00
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2005-11-09 01:30:36 +03:00
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data_bits = (s->lcr & 0x03) + 5;
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2008-08-11 18:17:04 +04:00
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frame_size += data_bits + stop_bits;
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2008-05-05 01:42:11 +04:00
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speed = s->baudbase / s->divider;
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2005-11-11 02:58:33 +03:00
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ssp.speed = speed;
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ssp.parity = parity;
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ssp.data_bits = data_bits;
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ssp.stop_bits = stop_bits;
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2009-09-10 05:04:26 +04:00
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s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
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2011-08-15 20:17:34 +04:00
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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2010-09-13 16:32:32 +04:00
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DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
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2005-11-09 01:30:36 +03:00
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speed, parity, data_bits, stop_bits);
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}
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2008-08-11 18:17:04 +04:00
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static void serial_update_msl(SerialState *s)
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{
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uint8_t omsr;
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int flags;
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qemu_del_timer(s->modem_status_poll);
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2011-08-15 20:17:34 +04:00
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if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
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2008-08-11 18:17:04 +04:00
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s->poll_msl = -1;
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return;
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}
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omsr = s->msr;
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s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
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s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
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s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
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s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
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if (s->msr != omsr) {
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/* Set delta bits */
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s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
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/* UART_MSR_TERI only if change was from 1 -> 0 */
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if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
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s->msr &= ~UART_MSR_TERI;
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serial_update_irq(s);
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}
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/* The real 16550A apparently has a 250ns response latency to line status changes.
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We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
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if (s->poll_msl)
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2011-03-11 18:47:48 +03:00
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qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
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2008-08-11 18:17:04 +04:00
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}
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2013-03-05 21:51:33 +04:00
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static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
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2008-08-11 18:17:04 +04:00
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{
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SerialState *s = opaque;
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if (s->tsr_retry <= 0) {
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if (s->fcr & UART_FCR_FE) {
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2013-06-03 09:13:27 +04:00
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s->tsr = fifo8_is_full(&s->xmit_fifo) ?
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0 : fifo8_pop(&s->xmit_fifo);
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if (!s->xmit_fifo.num) {
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2008-08-11 18:17:04 +04:00
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s->lsr |= UART_LSR_THRE;
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2013-06-03 09:12:09 +04:00
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}
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2013-03-05 21:51:33 +04:00
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} else if ((s->lsr & UART_LSR_THRE)) {
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return FALSE;
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2008-08-11 18:17:04 +04:00
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} else {
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s->tsr = s->thr;
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s->lsr |= UART_LSR_THRE;
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2012-04-01 23:18:30 +04:00
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s->lsr &= ~UART_LSR_TEMT;
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2008-08-11 18:17:04 +04:00
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}
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}
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if (s->mcr & UART_MCR_LOOP) {
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/* in loopback mode, say that we just received a char */
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serial_receive1(s, &s->tsr, 1);
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2011-08-15 20:17:28 +04:00
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} else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) {
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2013-03-05 21:51:33 +04:00
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if (s->tsr_retry >= 0 && s->tsr_retry < MAX_XMIT_RETRY &&
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qemu_chr_fe_add_watch(s->chr, G_IO_OUT, serial_xmit, s) > 0) {
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2008-08-11 18:17:04 +04:00
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s->tsr_retry++;
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2013-03-05 21:51:33 +04:00
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return FALSE;
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2008-08-11 18:17:04 +04:00
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}
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2013-03-05 21:51:33 +04:00
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s->tsr_retry = 0;
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} else {
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2008-08-11 18:17:04 +04:00
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s->tsr_retry = 0;
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}
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2011-03-11 18:47:48 +03:00
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s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
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2008-08-11 18:17:04 +04:00
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if (s->lsr & UART_LSR_THRE) {
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s->lsr |= UART_LSR_TEMT;
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s->thr_ipending = 1;
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serial_update_irq(s);
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}
|
2013-03-05 21:51:33 +04:00
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return FALSE;
|
2008-08-11 18:17:04 +04:00
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}
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|
2012-10-08 15:40:29 +04:00
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static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
|
2004-03-14 15:20:30 +03:00
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{
|
2004-03-15 00:46:48 +03:00
|
|
|
SerialState *s = opaque;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-03-14 15:20:30 +03:00
|
|
|
addr &= 7;
|
2013-03-19 15:25:43 +04:00
|
|
|
DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val);
|
2004-03-14 15:20:30 +03:00
|
|
|
switch(addr) {
|
|
|
|
default:
|
|
|
|
case 0:
|
|
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
|
|
s->divider = (s->divider & 0xff00) | val;
|
2005-11-09 01:30:36 +03:00
|
|
|
serial_update_parameters(s);
|
2004-03-14 15:20:30 +03:00
|
|
|
} else {
|
2008-08-11 18:17:04 +04:00
|
|
|
s->thr = (uint8_t) val;
|
|
|
|
if(s->fcr & UART_FCR_FE) {
|
2013-06-03 09:13:27 +04:00
|
|
|
/* xmit overruns overwrite data, so make space if needed */
|
|
|
|
if (fifo8_is_full(&s->xmit_fifo)) {
|
|
|
|
fifo8_pop(&s->xmit_fifo);
|
|
|
|
}
|
|
|
|
fifo8_push(&s->xmit_fifo, s->thr);
|
2010-03-06 22:23:09 +03:00
|
|
|
s->lsr &= ~UART_LSR_TEMT;
|
2008-05-05 01:42:00 +04:00
|
|
|
}
|
2013-06-03 09:14:48 +04:00
|
|
|
s->thr_ipending = 0;
|
|
|
|
s->lsr &= ~UART_LSR_THRE;
|
|
|
|
serial_update_irq(s);
|
2013-03-05 21:51:33 +04:00
|
|
|
serial_xmit(NULL, G_IO_OUT, s);
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
|
|
s->divider = (s->divider & 0x00ff) | (val << 8);
|
2005-11-09 01:30:36 +03:00
|
|
|
serial_update_parameters(s);
|
2004-03-14 15:20:30 +03:00
|
|
|
} else {
|
2004-08-25 01:55:28 +04:00
|
|
|
s->ier = val & 0x0f;
|
2008-08-11 18:17:04 +04:00
|
|
|
/* If the backend device is a real serial port, turn polling of the modem
|
|
|
|
status lines on physical port on or off depending on UART_IER_MSI state */
|
|
|
|
if (s->poll_msl >= 0) {
|
|
|
|
if (s->ier & UART_IER_MSI) {
|
|
|
|
s->poll_msl = 1;
|
|
|
|
serial_update_msl(s);
|
|
|
|
} else {
|
|
|
|
qemu_del_timer(s->modem_status_poll);
|
|
|
|
s->poll_msl = 0;
|
|
|
|
}
|
|
|
|
}
|
2004-08-25 01:55:28 +04:00
|
|
|
if (s->lsr & UART_LSR_THRE) {
|
|
|
|
s->thr_ipending = 1;
|
2008-08-11 18:17:04 +04:00
|
|
|
serial_update_irq(s);
|
2004-08-25 01:55:28 +04:00
|
|
|
}
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2:
|
2008-08-11 18:17:04 +04:00
|
|
|
val = val & 0xFF;
|
|
|
|
|
|
|
|
if (s->fcr == val)
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
|
|
|
|
if ((val ^ s->fcr) & UART_FCR_FE)
|
|
|
|
val |= UART_FCR_XFR | UART_FCR_RFR;
|
|
|
|
|
|
|
|
/* FIFO clear */
|
|
|
|
|
|
|
|
if (val & UART_FCR_RFR) {
|
|
|
|
qemu_del_timer(s->fifo_timeout_timer);
|
|
|
|
s->timeout_ipending=0;
|
2013-06-03 09:13:27 +04:00
|
|
|
fifo8_reset(&s->recv_fifo);
|
2008-08-11 18:17:04 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (val & UART_FCR_XFR) {
|
2013-06-03 09:13:27 +04:00
|
|
|
fifo8_reset(&s->xmit_fifo);
|
2008-08-11 18:17:04 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (val & UART_FCR_FE) {
|
|
|
|
s->iir |= UART_IIR_FE;
|
2013-06-03 09:13:27 +04:00
|
|
|
/* Set recv_fifo trigger Level */
|
2008-08-11 18:17:04 +04:00
|
|
|
switch (val & 0xC0) {
|
|
|
|
case UART_FCR_ITL_1:
|
2013-06-03 09:13:27 +04:00
|
|
|
s->recv_fifo_itl = 1;
|
2008-08-11 18:17:04 +04:00
|
|
|
break;
|
|
|
|
case UART_FCR_ITL_2:
|
2013-06-03 09:13:27 +04:00
|
|
|
s->recv_fifo_itl = 4;
|
2008-08-11 18:17:04 +04:00
|
|
|
break;
|
|
|
|
case UART_FCR_ITL_3:
|
2013-06-03 09:13:27 +04:00
|
|
|
s->recv_fifo_itl = 8;
|
2008-08-11 18:17:04 +04:00
|
|
|
break;
|
|
|
|
case UART_FCR_ITL_4:
|
2013-06-03 09:13:27 +04:00
|
|
|
s->recv_fifo_itl = 14;
|
2008-08-11 18:17:04 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
s->iir &= ~UART_IIR_FE;
|
|
|
|
|
|
|
|
/* Set fcr - or at least the bits in it that are supposed to "stick" */
|
|
|
|
s->fcr = val & 0xC9;
|
|
|
|
serial_update_irq(s);
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
case 3:
|
2005-11-09 01:30:36 +03:00
|
|
|
{
|
|
|
|
int break_enable;
|
|
|
|
s->lcr = val;
|
|
|
|
serial_update_parameters(s);
|
|
|
|
break_enable = (val >> 6) & 1;
|
|
|
|
if (break_enable != s->last_break_enable) {
|
|
|
|
s->last_break_enable = break_enable;
|
2011-08-15 20:17:34 +04:00
|
|
|
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
|
2005-11-11 02:58:33 +03:00
|
|
|
&break_enable);
|
2005-11-09 01:30:36 +03:00
|
|
|
}
|
|
|
|
}
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-08-11 18:17:04 +04:00
|
|
|
{
|
|
|
|
int flags;
|
|
|
|
int old_mcr = s->mcr;
|
|
|
|
s->mcr = val & 0x1f;
|
|
|
|
if (val & UART_MCR_LOOP)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (s->poll_msl >= 0 && old_mcr != s->mcr) {
|
|
|
|
|
2011-08-15 20:17:34 +04:00
|
|
|
qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
|
2008-08-11 18:17:04 +04:00
|
|
|
|
|
|
|
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
|
|
|
|
|
|
|
|
if (val & UART_MCR_RTS)
|
|
|
|
flags |= CHR_TIOCM_RTS;
|
|
|
|
if (val & UART_MCR_DTR)
|
|
|
|
flags |= CHR_TIOCM_DTR;
|
|
|
|
|
2011-08-15 20:17:34 +04:00
|
|
|
qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
|
2008-08-11 18:17:04 +04:00
|
|
|
/* Update the modem status after a one-character-send wait-time, since there may be a response
|
|
|
|
from the device/computer at the other end of the serial line */
|
2011-03-11 18:47:48 +03:00
|
|
|
qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
|
2008-08-11 18:17:04 +04:00
|
|
|
}
|
|
|
|
}
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
s->scr = val;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-08 15:40:29 +04:00
|
|
|
static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
|
2004-03-14 15:20:30 +03:00
|
|
|
{
|
2004-03-15 00:46:48 +03:00
|
|
|
SerialState *s = opaque;
|
2004-03-14 15:20:30 +03:00
|
|
|
uint32_t ret;
|
|
|
|
|
|
|
|
addr &= 7;
|
|
|
|
switch(addr) {
|
|
|
|
default:
|
|
|
|
case 0:
|
|
|
|
if (s->lcr & UART_LCR_DLAB) {
|
2007-09-17 01:08:06 +04:00
|
|
|
ret = s->divider & 0xff;
|
2004-03-14 15:20:30 +03:00
|
|
|
} else {
|
2008-08-11 18:17:04 +04:00
|
|
|
if(s->fcr & UART_FCR_FE) {
|
2013-06-17 04:30:52 +04:00
|
|
|
ret = fifo8_is_empty(&s->recv_fifo) ?
|
2013-06-03 09:13:27 +04:00
|
|
|
0 : fifo8_pop(&s->recv_fifo);
|
|
|
|
if (s->recv_fifo.num == 0) {
|
2008-08-11 18:17:04 +04:00
|
|
|
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
|
2013-06-03 09:12:09 +04:00
|
|
|
} else {
|
2011-03-11 18:47:48 +03:00
|
|
|
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
|
2013-06-03 09:12:09 +04:00
|
|
|
}
|
2008-08-11 18:17:04 +04:00
|
|
|
s->timeout_ipending = 0;
|
|
|
|
} else {
|
|
|
|
ret = s->rbr;
|
|
|
|
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
|
|
|
|
}
|
2004-03-15 00:46:48 +03:00
|
|
|
serial_update_irq(s);
|
2008-02-10 16:40:52 +03:00
|
|
|
if (!(s->mcr & UART_MCR_LOOP)) {
|
|
|
|
/* in loopback mode, don't receive any data */
|
|
|
|
qemu_chr_accept_input(s->chr);
|
|
|
|
}
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
|
|
ret = (s->divider >> 8) & 0xff;
|
|
|
|
} else {
|
|
|
|
ret = s->ier;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
ret = s->iir;
|
2010-03-07 00:19:53 +03:00
|
|
|
if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
|
2004-03-14 15:20:30 +03:00
|
|
|
s->thr_ipending = 0;
|
2010-02-11 00:35:54 +03:00
|
|
|
serial_update_irq(s);
|
|
|
|
}
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
ret = s->lcr;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
ret = s->mcr;
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
ret = s->lsr;
|
2010-02-11 00:35:54 +03:00
|
|
|
/* Clear break and overrun interrupts */
|
|
|
|
if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
|
|
|
|
s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
|
2008-08-11 18:17:04 +04:00
|
|
|
serial_update_irq(s);
|
|
|
|
}
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
if (s->mcr & UART_MCR_LOOP) {
|
|
|
|
/* in loopback, the modem output pins are connected to the
|
|
|
|
inputs */
|
|
|
|
ret = (s->mcr & 0x0c) << 4;
|
|
|
|
ret |= (s->mcr & 0x02) << 3;
|
|
|
|
ret |= (s->mcr & 0x01) << 5;
|
|
|
|
} else {
|
2008-08-11 18:17:04 +04:00
|
|
|
if (s->poll_msl >= 0)
|
|
|
|
serial_update_msl(s);
|
2004-03-14 15:20:30 +03:00
|
|
|
ret = s->msr;
|
2008-08-11 18:17:04 +04:00
|
|
|
/* Clear delta bits & msr int after read, if they were set */
|
|
|
|
if (s->msr & UART_MSR_ANY_DELTA) {
|
|
|
|
s->msr &= 0xF0;
|
|
|
|
serial_update_irq(s);
|
|
|
|
}
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
ret = s->scr;
|
|
|
|
break;
|
|
|
|
}
|
2013-03-19 15:25:43 +04:00
|
|
|
DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret);
|
2004-03-14 15:20:30 +03:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-07-14 21:28:13 +04:00
|
|
|
static int serial_can_receive(SerialState *s)
|
2004-03-14 15:20:30 +03:00
|
|
|
{
|
2008-08-11 18:17:04 +04:00
|
|
|
if(s->fcr & UART_FCR_FE) {
|
2013-06-03 09:13:27 +04:00
|
|
|
if (s->recv_fifo.num < UART_FIFO_LENGTH) {
|
2013-06-03 09:12:09 +04:00
|
|
|
/*
|
|
|
|
* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
|
|
|
|
* if above. If UART_FIFO_LENGTH - fifo.count is advertised the
|
|
|
|
* effect will be to almost always fill the fifo completely before
|
|
|
|
* the guest has a chance to respond, effectively overriding the ITL
|
|
|
|
* that the guest has set.
|
|
|
|
*/
|
2013-06-03 09:13:27 +04:00
|
|
|
return (s->recv_fifo.num <= s->recv_fifo_itl) ?
|
|
|
|
s->recv_fifo_itl - s->recv_fifo.num : 1;
|
2013-06-03 09:12:09 +04:00
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
2008-08-11 18:17:04 +04:00
|
|
|
} else {
|
2013-06-03 09:12:09 +04:00
|
|
|
return !(s->lsr & UART_LSR_DR);
|
2008-08-11 18:17:04 +04:00
|
|
|
}
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
|
|
|
|
2004-07-14 21:28:13 +04:00
|
|
|
static void serial_receive_break(SerialState *s)
|
2004-03-14 15:20:30 +03:00
|
|
|
{
|
|
|
|
s->rbr = 0;
|
2009-05-18 19:00:27 +04:00
|
|
|
/* When the LSR_DR is set a null byte is pushed into the fifo */
|
2013-06-03 09:13:27 +04:00
|
|
|
recv_fifo_put(s, '\0');
|
2004-03-14 15:20:30 +03:00
|
|
|
s->lsr |= UART_LSR_BI | UART_LSR_DR;
|
2004-03-15 00:46:48 +03:00
|
|
|
serial_update_irq(s);
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
|
|
|
|
2008-08-11 18:17:04 +04:00
|
|
|
/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
|
|
|
|
static void fifo_timeout_int (void *opaque) {
|
|
|
|
SerialState *s = opaque;
|
2013-06-03 09:13:27 +04:00
|
|
|
if (s->recv_fifo.num) {
|
2008-08-11 18:17:04 +04:00
|
|
|
s->timeout_ipending = 1;
|
|
|
|
serial_update_irq(s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-03-15 00:46:48 +03:00
|
|
|
static int serial_can_receive1(void *opaque)
|
2004-03-14 15:20:30 +03:00
|
|
|
{
|
2004-03-15 00:46:48 +03:00
|
|
|
SerialState *s = opaque;
|
|
|
|
return serial_can_receive(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_receive1(void *opaque, const uint8_t *buf, int size)
|
|
|
|
{
|
|
|
|
SerialState *s = opaque;
|
2012-02-23 16:45:23 +04:00
|
|
|
|
|
|
|
if (s->wakeup) {
|
|
|
|
qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
|
|
|
|
}
|
2008-08-11 18:17:04 +04:00
|
|
|
if(s->fcr & UART_FCR_FE) {
|
|
|
|
int i;
|
|
|
|
for (i = 0; i < size; i++) {
|
2013-06-03 09:13:27 +04:00
|
|
|
recv_fifo_put(s, buf[i]);
|
2008-08-11 18:17:04 +04:00
|
|
|
}
|
|
|
|
s->lsr |= UART_LSR_DR;
|
|
|
|
/* call the timeout receive callback in 4 char transmit time */
|
2011-03-11 18:47:48 +03:00
|
|
|
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
|
2008-08-11 18:17:04 +04:00
|
|
|
} else {
|
2010-02-11 00:35:54 +03:00
|
|
|
if (s->lsr & UART_LSR_DR)
|
|
|
|
s->lsr |= UART_LSR_OE;
|
2008-08-11 18:17:04 +04:00
|
|
|
s->rbr = buf[0];
|
|
|
|
s->lsr |= UART_LSR_DR;
|
|
|
|
}
|
|
|
|
serial_update_irq(s);
|
2004-03-15 00:46:48 +03:00
|
|
|
}
|
2004-03-14 15:20:30 +03:00
|
|
|
|
2004-07-14 21:28:13 +04:00
|
|
|
static void serial_event(void *opaque, int event)
|
|
|
|
{
|
|
|
|
SerialState *s = opaque;
|
2010-09-13 16:32:32 +04:00
|
|
|
DPRINTF("event %x\n", event);
|
2004-07-14 21:28:13 +04:00
|
|
|
if (event == CHR_EVENT_BREAK)
|
|
|
|
serial_receive_break(s);
|
|
|
|
}
|
|
|
|
|
2009-09-30 00:48:22 +04:00
|
|
|
static void serial_pre_save(void *opaque)
|
2005-11-06 18:48:04 +03:00
|
|
|
{
|
2009-09-30 00:48:22 +04:00
|
|
|
SerialState *s = opaque;
|
2009-09-10 05:04:46 +04:00
|
|
|
s->fcr_vmstate = s->fcr;
|
2005-11-06 18:48:04 +03:00
|
|
|
}
|
|
|
|
|
2009-09-30 00:48:21 +04:00
|
|
|
static int serial_post_load(void *opaque, int version_id)
|
2009-09-10 05:04:46 +04:00
|
|
|
{
|
|
|
|
SerialState *s = opaque;
|
2008-08-11 18:17:04 +04:00
|
|
|
|
2009-10-16 17:39:58 +04:00
|
|
|
if (version_id < 3) {
|
|
|
|
s->fcr_vmstate = 0;
|
|
|
|
}
|
2008-08-11 18:17:04 +04:00
|
|
|
/* Initialize fcr via setter to perform essential side-effects */
|
2012-10-08 15:40:29 +04:00
|
|
|
serial_ioport_write(s, 0x02, s->fcr_vmstate, 1);
|
2010-09-15 17:35:53 +04:00
|
|
|
serial_update_parameters(s);
|
2005-11-06 18:48:04 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-17 11:54:19 +04:00
|
|
|
const VMStateDescription vmstate_serial = {
|
2009-09-10 05:04:46 +04:00
|
|
|
.name = "serial",
|
|
|
|
.version_id = 3,
|
|
|
|
.minimum_version_id = 2,
|
|
|
|
.pre_save = serial_pre_save,
|
|
|
|
.post_load = serial_post_load,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_UINT16_V(divider, SerialState, 2),
|
|
|
|
VMSTATE_UINT8(rbr, SerialState),
|
|
|
|
VMSTATE_UINT8(ier, SerialState),
|
|
|
|
VMSTATE_UINT8(iir, SerialState),
|
|
|
|
VMSTATE_UINT8(lcr, SerialState),
|
|
|
|
VMSTATE_UINT8(mcr, SerialState),
|
|
|
|
VMSTATE_UINT8(lsr, SerialState),
|
|
|
|
VMSTATE_UINT8(msr, SerialState),
|
|
|
|
VMSTATE_UINT8(scr, SerialState),
|
|
|
|
VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2008-02-10 16:40:52 +03:00
|
|
|
static void serial_reset(void *opaque)
|
|
|
|
{
|
|
|
|
SerialState *s = opaque;
|
|
|
|
|
|
|
|
s->rbr = 0;
|
|
|
|
s->ier = 0;
|
|
|
|
s->iir = UART_IIR_NO_INT;
|
|
|
|
s->lcr = 0;
|
|
|
|
s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
|
|
|
|
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
|
2009-10-26 23:51:41 +03:00
|
|
|
/* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
|
2008-08-11 18:17:04 +04:00
|
|
|
s->divider = 0x0C;
|
|
|
|
s->mcr = UART_MCR_OUT2;
|
2008-02-10 16:40:52 +03:00
|
|
|
s->scr = 0;
|
2008-08-11 18:17:04 +04:00
|
|
|
s->tsr_retry = 0;
|
2009-10-26 23:51:41 +03:00
|
|
|
s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
|
2008-08-11 18:17:04 +04:00
|
|
|
s->poll_msl = 0;
|
|
|
|
|
2013-06-03 09:13:27 +04:00
|
|
|
fifo8_reset(&s->recv_fifo);
|
|
|
|
fifo8_reset(&s->xmit_fifo);
|
2008-08-11 18:17:04 +04:00
|
|
|
|
2011-03-11 18:47:48 +03:00
|
|
|
s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
|
2008-02-10 16:40:52 +03:00
|
|
|
|
|
|
|
s->thr_ipending = 0;
|
|
|
|
s->last_break_enable = 0;
|
|
|
|
qemu_irq_lower(s->irq);
|
|
|
|
}
|
|
|
|
|
2012-11-25 05:37:14 +04:00
|
|
|
void serial_realize_core(SerialState *s, Error **errp)
|
2008-08-11 18:17:04 +04:00
|
|
|
{
|
2009-09-22 15:53:21 +04:00
|
|
|
if (!s->chr) {
|
2012-11-25 05:37:14 +04:00
|
|
|
error_setg(errp, "Can't create serial device, empty char device");
|
|
|
|
return;
|
2009-09-15 03:16:28 +04:00
|
|
|
}
|
|
|
|
|
2011-03-11 18:47:48 +03:00
|
|
|
s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
|
2008-08-11 18:17:04 +04:00
|
|
|
|
2011-03-11 18:47:48 +03:00
|
|
|
s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
|
2009-06-27 11:25:07 +04:00
|
|
|
qemu_register_reset(serial_reset, s);
|
2008-08-11 18:17:04 +04:00
|
|
|
|
2009-01-18 17:28:10 +03:00
|
|
|
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
|
|
|
|
serial_event, s);
|
2013-06-03 09:13:27 +04:00
|
|
|
fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
|
|
|
|
fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
|
2008-08-11 18:17:04 +04:00
|
|
|
}
|
|
|
|
|
2012-10-17 11:54:20 +04:00
|
|
|
void serial_exit_core(SerialState *s)
|
|
|
|
{
|
|
|
|
qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL);
|
|
|
|
qemu_unregister_reset(serial_reset, s);
|
|
|
|
}
|
|
|
|
|
2009-10-31 13:28:11 +03:00
|
|
|
/* Change the main reference oscillator frequency. */
|
|
|
|
void serial_set_frequency(SerialState *s, uint32_t frequency)
|
|
|
|
{
|
|
|
|
s->baudbase = frequency;
|
|
|
|
serial_update_parameters(s);
|
|
|
|
}
|
|
|
|
|
2012-10-17 11:54:19 +04:00
|
|
|
const MemoryRegionOps serial_io_ops = {
|
2012-10-08 15:40:29 +04:00
|
|
|
.read = serial_ioport_read,
|
|
|
|
.write = serial_ioport_write,
|
|
|
|
.impl = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 1,
|
|
|
|
},
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
2011-08-11 02:28:18 +04:00
|
|
|
};
|
|
|
|
|
2008-05-05 01:42:11 +04:00
|
|
|
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
|
2012-09-19 15:50:07 +04:00
|
|
|
CharDriverState *chr, MemoryRegion *system_io)
|
2004-03-15 00:46:48 +03:00
|
|
|
{
|
|
|
|
SerialState *s;
|
2012-11-25 05:37:14 +04:00
|
|
|
Error *err = NULL;
|
2004-03-15 00:46:48 +03:00
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
s = g_malloc0(sizeof(SerialState));
|
2008-05-05 01:42:00 +04:00
|
|
|
|
2009-09-22 15:53:21 +04:00
|
|
|
s->irq = irq;
|
|
|
|
s->baudbase = baudbase;
|
|
|
|
s->chr = chr;
|
2012-11-25 05:37:14 +04:00
|
|
|
serial_realize_core(s, &err);
|
|
|
|
if (err != NULL) {
|
|
|
|
fprintf(stderr, "%s\n", error_get_pretty(err));
|
|
|
|
error_free(err);
|
|
|
|
exit(1);
|
|
|
|
}
|
2004-03-15 00:46:48 +03:00
|
|
|
|
2010-06-25 21:09:07 +04:00
|
|
|
vmstate_register(NULL, base, &vmstate_serial, s);
|
2005-11-06 18:48:04 +03:00
|
|
|
|
2013-06-06 13:41:28 +04:00
|
|
|
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
|
2012-09-19 15:50:07 +04:00
|
|
|
memory_region_add_subregion(system_io, base, &s->io);
|
2012-10-08 15:40:29 +04:00
|
|
|
|
2004-03-15 00:46:48 +03:00
|
|
|
return s;
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
2005-11-24 00:11:49 +03:00
|
|
|
|
|
|
|
/* Memory mapped interface */
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint64_t serial_mm_read(void *opaque, hwaddr addr,
|
2011-08-12 03:18:59 +04:00
|
|
|
unsigned size)
|
2005-11-24 00:11:49 +03:00
|
|
|
{
|
|
|
|
SerialState *s = opaque;
|
2012-10-08 15:40:29 +04:00
|
|
|
return serial_ioport_read(s, addr >> s->it_shift, 1);
|
2005-11-24 00:11:49 +03:00
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static void serial_mm_write(void *opaque, hwaddr addr,
|
2011-08-12 03:18:59 +04:00
|
|
|
uint64_t value, unsigned size)
|
2010-03-21 22:47:11 +03:00
|
|
|
{
|
|
|
|
SerialState *s = opaque;
|
2011-08-12 03:18:59 +04:00
|
|
|
value &= ~0u >> (32 - (size * 8));
|
2012-10-08 15:40:29 +04:00
|
|
|
serial_ioport_write(s, addr >> s->it_shift, value, 1);
|
2010-03-21 22:47:11 +03:00
|
|
|
}
|
|
|
|
|
2011-08-12 03:18:59 +04:00
|
|
|
static const MemoryRegionOps serial_mm_ops[3] = {
|
|
|
|
[DEVICE_NATIVE_ENDIAN] = {
|
|
|
|
.read = serial_mm_read,
|
|
|
|
.write = serial_mm_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
},
|
|
|
|
[DEVICE_LITTLE_ENDIAN] = {
|
|
|
|
.read = serial_mm_read,
|
|
|
|
.write = serial_mm_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
},
|
|
|
|
[DEVICE_BIG_ENDIAN] = {
|
|
|
|
.read = serial_mm_read,
|
|
|
|
.write = serial_mm_write,
|
|
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
|
|
},
|
2005-11-24 00:11:49 +03:00
|
|
|
};
|
|
|
|
|
2011-08-12 03:07:16 +04:00
|
|
|
SerialState *serial_mm_init(MemoryRegion *address_space,
|
2012-10-23 14:30:10 +04:00
|
|
|
hwaddr base, int it_shift,
|
2011-08-12 03:07:16 +04:00
|
|
|
qemu_irq irq, int baudbase,
|
|
|
|
CharDriverState *chr, enum device_endian end)
|
2005-11-24 00:11:49 +03:00
|
|
|
{
|
|
|
|
SerialState *s;
|
2012-11-25 05:37:14 +04:00
|
|
|
Error *err = NULL;
|
2005-11-24 00:11:49 +03:00
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
s = g_malloc0(sizeof(SerialState));
|
2008-08-11 18:17:04 +04:00
|
|
|
|
2005-11-24 00:11:49 +03:00
|
|
|
s->it_shift = it_shift;
|
2009-09-22 15:53:21 +04:00
|
|
|
s->irq = irq;
|
|
|
|
s->baudbase = baudbase;
|
|
|
|
s->chr = chr;
|
2005-11-24 00:11:49 +03:00
|
|
|
|
2012-11-25 05:37:14 +04:00
|
|
|
serial_realize_core(s, &err);
|
|
|
|
if (err != NULL) {
|
|
|
|
fprintf(stderr, "%s\n", error_get_pretty(err));
|
|
|
|
error_free(err);
|
|
|
|
exit(1);
|
|
|
|
}
|
2010-06-25 21:09:07 +04:00
|
|
|
vmstate_register(NULL, base, &vmstate_serial, s);
|
2005-11-24 00:11:49 +03:00
|
|
|
|
2013-06-06 13:41:28 +04:00
|
|
|
memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
|
2011-08-12 03:18:59 +04:00
|
|
|
"serial", 8 << it_shift);
|
2011-08-12 03:07:16 +04:00
|
|
|
memory_region_add_subregion(address_space, base, &s->io);
|
2011-08-12 03:07:15 +04:00
|
|
|
|
2008-08-11 18:17:04 +04:00
|
|
|
serial_update_msl(s);
|
2005-11-24 00:11:49 +03:00
|
|
|
return s;
|
|
|
|
}
|