2007-09-17 01:08:06 +04:00
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/*
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2006-07-17 22:45:34 +04:00
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* Arm PrimeCell PL050 Keyboard / Mouse Interface
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2006-04-09 05:32:52 +04:00
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*
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2007-04-30 06:39:55 +04:00
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* Copyright (c) 2006-2007 CodeSourcery.
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2006-04-09 05:32:52 +04:00
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* Written by Paul Brook
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*
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2011-06-26 06:21:35 +04:00
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* This code is licensed under the GPL.
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2006-04-09 05:32:52 +04:00
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*/
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2022-06-24 16:40:52 +03:00
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/*
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* QEMU interface:
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* + sysbus MMIO region 0: MemoryRegion defining the PL050 registers
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* + Named GPIO input "ps2-input-irq": set to 1 if the downstream PS2 device
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* has asserted its irq
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* + sysbus IRQ 0: PL050 output irq
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*/
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2016-01-26 21:17:05 +03:00
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#include "qemu/osdep.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/sysbus.h"
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2019-08-12 08:23:45 +03:00
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#include "migration/vmstate.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/input/ps2.h"
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2022-07-13 00:52:12 +03:00
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#include "hw/input/pl050.h"
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2019-08-12 08:23:42 +03:00
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#include "hw/irq.h"
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2015-12-15 15:16:16 +03:00
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#include "qemu/log.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2020-09-03 23:43:22 +03:00
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#include "qom/object.h"
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2006-04-09 05:32:52 +04:00
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2010-12-23 20:19:54 +03:00
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static const VMStateDescription vmstate_pl050 = {
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.name = "pl050",
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2013-04-05 19:17:58 +04:00
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.version_id = 2,
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.minimum_version_id = 2,
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2023-12-21 06:16:14 +03:00
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.fields = (const VMStateField[]) {
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2013-07-26 20:40:25 +04:00
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VMSTATE_UINT32(cr, PL050State),
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VMSTATE_UINT32(clk, PL050State),
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VMSTATE_UINT32(last, PL050State),
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VMSTATE_INT32(pending, PL050State),
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2010-12-23 20:19:54 +03:00
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VMSTATE_END_OF_LIST()
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}
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};
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2007-04-30 06:39:55 +04:00
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#define PL050_TXEMPTY (1 << 6)
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#define PL050_TXBUSY (1 << 5)
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#define PL050_RXFULL (1 << 4)
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#define PL050_RXBUSY (1 << 3)
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#define PL050_RXPARITY (1 << 2)
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#define PL050_KMIC (1 << 1)
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#define PL050_KMID (1 << 0)
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2022-06-24 16:40:29 +03:00
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static const unsigned char pl050_id[] = {
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0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
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};
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2006-04-09 05:32:52 +04:00
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2022-06-24 16:40:30 +03:00
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static void pl050_update_irq(PL050State *s)
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{
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int level = (s->pending && (s->cr & 0x10) != 0)
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|| (s->cr & 0x08) != 0;
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qemu_set_irq(s->irq, level);
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}
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2022-06-24 16:40:51 +03:00
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static void pl050_set_irq(void *opaque, int n, int level)
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2006-04-09 05:32:52 +04:00
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{
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2013-07-26 20:40:25 +04:00
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PL050State *s = (PL050State *)opaque;
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2006-04-09 05:32:52 +04:00
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s->pending = level;
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2022-06-24 16:40:30 +03:00
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pl050_update_irq(s);
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2006-04-09 05:32:52 +04:00
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}
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2012-10-23 14:30:10 +04:00
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static uint64_t pl050_read(void *opaque, hwaddr offset,
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2011-10-10 19:18:44 +04:00
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unsigned size)
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2006-04-09 05:32:52 +04:00
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{
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2013-07-26 20:40:25 +04:00
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PL050State *s = (PL050State *)opaque;
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2022-06-24 16:40:29 +03:00
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if (offset >= 0xfe0 && offset < 0x1000) {
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2006-04-09 05:32:52 +04:00
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return pl050_id[(offset - 0xfe0) >> 2];
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2022-06-24 16:40:29 +03:00
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}
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2006-04-09 05:32:52 +04:00
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switch (offset >> 2) {
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case 0: /* KMICR */
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return s->cr;
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case 1: /* KMISTAT */
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2007-04-30 06:39:55 +04:00
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{
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uint8_t val;
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uint32_t stat;
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val = s->last;
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val = val ^ (val >> 4);
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val = val ^ (val >> 2);
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val = (val ^ (val >> 1)) & 1;
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stat = PL050_TXEMPTY;
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2022-06-24 16:40:29 +03:00
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if (val) {
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2007-04-30 06:39:55 +04:00
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stat |= PL050_RXPARITY;
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2022-06-24 16:40:29 +03:00
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}
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if (s->pending) {
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2007-04-30 06:39:55 +04:00
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stat |= PL050_RXFULL;
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2022-06-24 16:40:29 +03:00
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}
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2007-04-30 06:39:55 +04:00
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return stat;
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2006-04-09 05:32:52 +04:00
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}
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case 2: /* KMIDATA */
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2022-06-24 16:40:29 +03:00
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if (s->pending) {
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2022-07-13 00:52:14 +03:00
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s->last = ps2_read_data(s->ps2dev);
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2022-06-24 16:40:29 +03:00
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}
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2006-04-09 05:32:52 +04:00
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return s->last;
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case 3: /* KMICLKDIV */
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return s->clk;
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case 4: /* KMIIR */
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return s->pending | 2;
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default:
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2012-10-30 11:45:08 +04:00
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl050_read: Bad offset %x\n", (int)offset);
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2006-04-09 05:32:52 +04:00
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return 0;
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}
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}
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2012-10-23 14:30:10 +04:00
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static void pl050_write(void *opaque, hwaddr offset,
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2011-10-10 19:18:44 +04:00
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uint64_t value, unsigned size)
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2006-04-09 05:32:52 +04:00
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{
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2013-07-26 20:40:25 +04:00
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PL050State *s = (PL050State *)opaque;
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2022-06-24 16:40:29 +03:00
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2006-04-09 05:32:52 +04:00
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switch (offset >> 2) {
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case 0: /* KMICR */
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s->cr = value;
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2022-06-24 16:40:30 +03:00
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pl050_update_irq(s);
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2006-04-09 05:32:52 +04:00
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/* ??? Need to implement the enable/disable bit. */
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break;
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case 2: /* KMIDATA */
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/* ??? This should toggle the TX interrupt line. */
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/* ??? This means kbd/mouse can block each other. */
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if (s->is_mouse) {
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2022-07-13 00:52:14 +03:00
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ps2_write_mouse(PS2_MOUSE_DEVICE(s->ps2dev), value);
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2006-04-09 05:32:52 +04:00
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} else {
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2022-07-13 00:52:14 +03:00
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ps2_write_keyboard(PS2_KBD_DEVICE(s->ps2dev), value);
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2006-04-09 05:32:52 +04:00
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}
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break;
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case 3: /* KMICLKDIV */
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s->clk = value;
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return;
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default:
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2012-10-30 11:45:08 +04:00
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl050_write: Bad offset %x\n", (int)offset);
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2006-04-09 05:32:52 +04:00
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}
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}
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2011-10-10 19:18:44 +04:00
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static const MemoryRegionOps pl050_ops = {
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.read = pl050_read,
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.write = pl050_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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2006-04-09 05:32:52 +04:00
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};
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2018-12-13 16:47:59 +03:00
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static void pl050_realize(DeviceState *dev, Error **errp)
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2006-04-09 05:32:52 +04:00
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{
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2013-07-26 20:49:24 +04:00
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PL050State *s = PL050(dev);
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2006-04-09 05:32:52 +04:00
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2022-07-13 00:52:14 +03:00
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qdev_connect_gpio_out(DEVICE(s->ps2dev), PS2_DEVICE_IRQ,
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2022-06-24 16:40:51 +03:00
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qdev_get_gpio_in_named(dev, "ps2-input-irq", 0));
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2006-04-09 05:32:52 +04:00
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}
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2009-05-15 01:35:07 +04:00
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2022-07-13 00:52:19 +03:00
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static void pl050_kbd_realize(DeviceState *dev, Error **errp)
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{
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PL050DeviceClass *pdc = PL050_GET_CLASS(dev);
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2022-07-13 00:52:21 +03:00
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PL050KbdState *s = PL050_KBD_DEVICE(dev);
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2022-07-13 00:52:19 +03:00
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PL050State *ps = PL050(dev);
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2022-07-13 00:52:21 +03:00
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->kbd), errp)) {
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return;
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}
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ps->ps2dev = PS2_DEVICE(&s->kbd);
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2022-07-13 00:52:19 +03:00
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pdc->parent_realize(dev, errp);
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}
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2022-07-13 00:52:13 +03:00
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static void pl050_kbd_init(Object *obj)
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2009-05-15 01:35:07 +04:00
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{
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2022-07-13 00:52:21 +03:00
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PL050KbdState *s = PL050_KBD_DEVICE(obj);
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PL050State *ps = PL050(obj);
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2009-05-15 01:35:07 +04:00
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2022-07-13 00:52:21 +03:00
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ps->is_mouse = false;
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object_initialize_child(obj, "kbd", &s->kbd, TYPE_PS2_KBD_DEVICE);
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2009-05-15 01:35:07 +04:00
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}
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2022-07-13 00:52:20 +03:00
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static void pl050_mouse_realize(DeviceState *dev, Error **errp)
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{
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PL050DeviceClass *pdc = PL050_GET_CLASS(dev);
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2022-07-13 00:52:22 +03:00
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PL050MouseState *s = PL050_MOUSE_DEVICE(dev);
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2022-07-13 00:52:20 +03:00
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PL050State *ps = PL050(dev);
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2022-07-13 00:52:22 +03:00
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->mouse), errp)) {
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return;
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}
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ps->ps2dev = PS2_DEVICE(&s->mouse);
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2022-07-13 00:52:20 +03:00
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pdc->parent_realize(dev, errp);
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}
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2013-07-26 20:49:24 +04:00
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static void pl050_mouse_init(Object *obj)
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2012-01-24 23:12:29 +04:00
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{
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2022-07-13 00:52:22 +03:00
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PL050MouseState *s = PL050_MOUSE_DEVICE(obj);
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PL050State *ps = PL050(obj);
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2012-01-24 23:12:29 +04:00
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2022-07-13 00:52:22 +03:00
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ps->is_mouse = true;
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object_initialize_child(obj, "mouse", &s->mouse, TYPE_PS2_MOUSE_DEVICE);
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2012-01-24 23:12:29 +04:00
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}
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2022-07-13 00:52:19 +03:00
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static void pl050_kbd_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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PL050DeviceClass *pdc = PL050_CLASS(oc);
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device_class_set_parent_realize(dc, pl050_kbd_realize,
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&pdc->parent_realize);
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}
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2013-01-10 19:19:07 +04:00
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static const TypeInfo pl050_kbd_info = {
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2022-07-13 00:52:15 +03:00
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.name = TYPE_PL050_KBD_DEVICE,
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2013-07-26 20:49:24 +04:00
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.parent = TYPE_PL050,
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2022-07-13 00:52:13 +03:00
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.instance_init = pl050_kbd_init,
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2022-07-13 00:52:15 +03:00
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.instance_size = sizeof(PL050KbdState),
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2022-07-13 00:52:19 +03:00
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.class_init = pl050_kbd_class_init,
|
2010-12-23 20:19:54 +03:00
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};
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2022-07-13 00:52:20 +03:00
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static void pl050_mouse_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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PL050DeviceClass *pdc = PL050_CLASS(oc);
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device_class_set_parent_realize(dc, pl050_mouse_realize,
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&pdc->parent_realize);
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}
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2013-07-26 20:49:24 +04:00
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static const TypeInfo pl050_mouse_info = {
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2022-07-13 00:52:16 +03:00
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.name = TYPE_PL050_MOUSE_DEVICE,
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2013-07-26 20:49:24 +04:00
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.parent = TYPE_PL050,
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.instance_init = pl050_mouse_init,
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2022-07-13 00:52:16 +03:00
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.instance_size = sizeof(PL050MouseState),
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2022-07-13 00:52:20 +03:00
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.class_init = pl050_mouse_class_init,
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2013-07-26 20:49:24 +04:00
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};
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2022-06-24 16:40:51 +03:00
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static void pl050_init(Object *obj)
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{
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2022-07-13 00:52:17 +03:00
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PL050State *s = PL050(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &pl050_ops, s, "pl050", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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2022-06-24 16:40:51 +03:00
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qdev_init_gpio_in_named(DEVICE(obj), pl050_set_irq, "ps2-input-irq", 1);
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}
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2013-07-26 20:49:24 +04:00
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static void pl050_class_init(ObjectClass *oc, void *data)
|
2012-01-24 23:12:29 +04:00
|
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{
|
2013-07-26 20:49:24 +04:00
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DeviceClass *dc = DEVICE_CLASS(oc);
|
2012-01-24 23:12:29 +04:00
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|
2018-12-13 16:47:59 +03:00
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dc->realize = pl050_realize;
|
2011-12-08 07:34:16 +04:00
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dc->vmsd = &vmstate_pl050;
|
2012-01-24 23:12:29 +04:00
|
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}
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|
2013-07-26 20:49:24 +04:00
|
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static const TypeInfo pl050_type_info = {
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.name = TYPE_PL050,
|
2011-12-08 07:34:16 +04:00
|
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|
.parent = TYPE_SYS_BUS_DEVICE,
|
2022-06-24 16:40:51 +03:00
|
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|
.instance_init = pl050_init,
|
2013-07-26 20:40:25 +04:00
|
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|
.instance_size = sizeof(PL050State),
|
2022-07-13 00:52:18 +03:00
|
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|
.class_init = pl050_class_init,
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|
|
.class_size = sizeof(PL050DeviceClass),
|
2013-07-26 20:49:24 +04:00
|
|
|
.abstract = true,
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|
.class_init = pl050_class_init,
|
2010-12-23 20:19:54 +03:00
|
|
|
};
|
|
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|
|
2012-02-09 18:20:55 +04:00
|
|
|
static void pl050_register_types(void)
|
2009-05-15 01:35:07 +04:00
|
|
|
{
|
2013-07-26 20:49:24 +04:00
|
|
|
type_register_static(&pl050_type_info);
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&pl050_kbd_info);
|
|
|
|
type_register_static(&pl050_mouse_info);
|
2009-05-15 01:35:07 +04:00
|
|
|
}
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
type_init(pl050_register_types)
|