2009-10-07 18:56:24 +04:00
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/*
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* QEMU IDE Emulation: PCI PIIX3/4 support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2012-05-11 19:22:19 +04:00
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2016-01-26 21:17:09 +03:00
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#include "qemu/osdep.h"
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2016-06-22 20:11:19 +03:00
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#include "hw/hw.h"
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#include "hw/i386/pc.h"
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#include "hw/pci/pci.h"
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#include "hw/isa/isa.h"
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2014-10-07 15:59:09 +04:00
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#include "sysemu/block-backend.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/sysemu.h"
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#include "sysemu/dma.h"
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2009-10-07 18:56:24 +04:00
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2016-06-22 20:11:19 +03:00
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#include "hw/ide/pci.h"
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2009-10-07 18:56:24 +04:00
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2012-10-23 14:30:10 +04:00
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static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
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2009-10-07 18:56:24 +04:00
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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2011-08-08 17:09:11 +04:00
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if (size != 1) {
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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2009-10-07 18:56:24 +04:00
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switch(addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 2:
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val = bm->status;
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break;
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default:
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val = 0xff;
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break;
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}
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#ifdef DEBUG_IDE
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2012-02-07 01:19:42 +04:00
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printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val);
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2009-10-07 18:56:24 +04:00
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#endif
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return val;
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}
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2012-10-23 14:30:10 +04:00
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static void bmdma_write(void *opaque, hwaddr addr,
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2011-08-08 17:09:11 +04:00
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uint64_t val, unsigned size)
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2009-10-07 18:56:24 +04:00
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{
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BMDMAState *bm = opaque;
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2011-08-08 17:09:11 +04:00
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if (size != 1) {
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return;
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}
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2009-10-07 18:56:24 +04:00
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#ifdef DEBUG_IDE
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2012-02-07 01:19:42 +04:00
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printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val);
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2009-10-07 18:56:24 +04:00
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#endif
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switch(addr & 3) {
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2011-08-08 17:09:11 +04:00
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case 0:
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2012-07-08 10:56:53 +04:00
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bmdma_cmd_writeb(bm, val);
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break;
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2009-10-07 18:56:24 +04:00
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case 2:
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
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break;
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}
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}
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2012-02-05 14:19:07 +04:00
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static const MemoryRegionOps piix_bmdma_ops = {
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2011-08-08 17:09:11 +04:00
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.read = bmdma_read,
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.write = bmdma_write,
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};
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static void bmdma_setup_bar(PCIIDEState *d)
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2009-10-07 18:56:24 +04:00
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{
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int i;
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2013-06-07 05:25:08 +04:00
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memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
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2009-10-07 18:56:24 +04:00
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for(i = 0;i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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2013-06-07 05:25:08 +04:00
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memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
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2011-08-08 17:09:11 +04:00
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"piix-bmdma", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
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2013-06-07 05:25:08 +04:00
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memory_region_init_io(&bm->addr_ioport, OBJECT(d),
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&bmdma_addr_ioport_ops, bm, "bmdma", 4);
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2011-08-08 17:09:11 +04:00
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memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
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2009-10-07 18:56:24 +04:00
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}
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}
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static void piix3_reset(void *opaque)
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{
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PCIIDEState *d = opaque;
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2013-07-17 20:44:48 +04:00
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PCIDevice *pd = PCI_DEVICE(d);
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uint8_t *pci_conf = pd->config;
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2009-10-07 18:56:24 +04:00
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int i;
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2009-11-07 17:13:05 +03:00
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for (i = 0; i < 2; i++) {
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ide_bus_reset(&d->bus[i]);
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}
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2009-10-07 18:56:24 +04:00
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2009-12-10 19:18:19 +03:00
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/* TODO: this is the default. do not override. */
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pci_conf[PCI_COMMAND] = 0x00;
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/* TODO: this is the default. do not override. */
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pci_conf[PCI_COMMAND + 1] = 0x00;
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/* TODO: use pci_set_word */
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pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
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pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
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2009-10-07 18:56:24 +04:00
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pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
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}
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2010-12-16 18:54:06 +03:00
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static void pci_piix_init_ports(PCIIDEState *d) {
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2011-08-16 19:59:00 +04:00
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static const struct {
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2010-12-16 18:54:06 +03:00
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int iobase;
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int iobase2;
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int isairq;
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} port_info[] = {
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{0x1f0, 0x3f6, 14},
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{0x170, 0x376, 15},
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};
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2011-08-16 19:59:00 +04:00
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int i;
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2010-12-16 18:54:06 +03:00
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for (i = 0; i < 2; i++) {
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2013-08-23 22:18:50 +04:00
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ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
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2011-08-16 19:59:00 +04:00
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ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
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port_info[i].iobase2);
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2011-12-16 01:09:51 +04:00
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ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
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2010-12-16 18:54:06 +03:00
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2011-08-08 17:09:11 +04:00
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bmdma_init(&d->bus[i], &d->bmdma[i], d);
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2010-12-16 18:54:06 +03:00
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d->bmdma[i].bus = &d->bus[i];
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2015-02-23 19:17:52 +03:00
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ide_register_restart_cb(&d->bus[i]);
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2010-12-16 18:54:06 +03:00
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}
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}
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2015-01-19 17:52:30 +03:00
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static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
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2009-10-07 18:56:24 +04:00
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{
|
2013-07-17 20:44:48 +04:00
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PCIIDEState *d = PCI_IDE(dev);
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uint8_t *pci_conf = dev->config;
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2009-10-07 18:56:24 +04:00
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2009-12-10 19:18:19 +03:00
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pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
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2009-10-07 18:56:24 +04:00
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qemu_register_reset(piix3_reset, d);
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2011-08-08 17:09:11 +04:00
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bmdma_setup_bar(d);
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2013-07-17 20:44:48 +04:00
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pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
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2009-10-07 18:56:24 +04:00
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2013-06-24 10:56:30 +04:00
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vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
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2009-10-07 18:56:24 +04:00
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2010-12-16 18:54:06 +03:00
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pci_piix_init_ports(d);
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2009-10-07 18:56:24 +04:00
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}
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2014-02-20 21:28:08 +04:00
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int pci_piix3_xen_ide_unplug(DeviceState *dev)
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2011-07-18 10:07:02 +04:00
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{
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PCIIDEState *pci_ide;
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DriveInfo *di;
|
2014-10-30 13:08:28 +03:00
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int i;
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2015-08-03 16:56:57 +03:00
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IDEDevice *idedev;
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2011-07-18 10:07:02 +04:00
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|
2013-07-17 20:44:48 +04:00
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pci_ide = PCI_IDE(dev);
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2011-07-18 10:07:02 +04:00
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2014-10-30 13:08:28 +03:00
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for (i = 0; i < 4; i++) {
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2011-07-18 10:07:02 +04:00
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di = drive_get_by_index(IF_IDE, i);
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2011-08-03 17:08:12 +04:00
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if (di != NULL && !di->media_cd) {
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2014-10-07 15:59:09 +04:00
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BlockBackend *blk = blk_by_legacy_dinfo(di);
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2014-10-07 15:59:18 +04:00
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DeviceState *ds = blk_get_attached_dev(blk);
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2016-09-23 04:45:52 +03:00
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blk_drain(blk);
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blk_flush(blk);
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2011-07-18 10:07:02 +04:00
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if (ds) {
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2014-10-07 15:59:18 +04:00
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blk_detach_dev(blk, ds);
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2011-07-18 10:07:02 +04:00
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}
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2014-10-07 15:59:18 +04:00
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pci_ide->bus[di->bus].ifs[di->unit].blk = NULL;
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2015-08-03 16:56:57 +03:00
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if (!(i % 2)) {
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idedev = pci_ide->bus[di->bus].master;
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} else {
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idedev = pci_ide->bus[di->bus].slave;
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}
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idedev->conf.blk = NULL;
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2016-04-12 23:47:52 +03:00
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monitor_remove_blk(blk);
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2014-10-07 15:59:09 +04:00
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blk_unref(blk);
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2011-07-18 10:07:02 +04:00
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}
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}
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2013-06-24 10:56:30 +04:00
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qdev_reset_all(DEVICE(dev));
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2011-07-18 10:07:02 +04:00
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return 0;
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}
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PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
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pci_ide_create_devs(dev, hd_table);
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return dev;
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}
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2012-07-04 08:39:27 +04:00
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static void pci_piix_ide_exitfn(PCIDevice *dev)
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2011-08-08 17:09:11 +04:00
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{
|
2013-07-17 20:44:48 +04:00
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PCIIDEState *d = PCI_IDE(dev);
|
2011-08-08 17:09:11 +04:00
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unsigned i;
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for (i = 0; i < 2; ++i) {
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
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}
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}
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2009-10-07 18:56:24 +04:00
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/* hd_table must contain 4 block drivers */
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/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
|
2010-06-24 21:59:29 +04:00
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PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
|
2009-10-07 18:56:24 +04:00
|
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{
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PCIDevice *dev;
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|
2009-12-09 19:07:53 +03:00
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dev = pci_create_simple(bus, devfn, "piix3-ide");
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2009-10-07 18:56:24 +04:00
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pci_ide_create_devs(dev, hd_table);
|
2010-06-24 21:59:29 +04:00
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return dev;
|
2009-10-07 18:56:24 +04:00
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}
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/* hd_table must contain 4 block drivers */
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/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
|
2010-06-24 21:59:29 +04:00
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PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
|
2009-10-07 18:56:24 +04:00
|
|
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{
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PCIDevice *dev;
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|
2009-12-09 19:07:53 +03:00
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dev = pci_create_simple(bus, devfn, "piix4-ide");
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2009-10-07 18:56:24 +04:00
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pci_ide_create_devs(dev, hd_table);
|
2010-06-24 21:59:29 +04:00
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return dev;
|
2009-10-07 18:56:24 +04:00
|
|
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}
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|
2011-12-04 22:22:06 +04:00
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|
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static void piix3_ide_class_init(ObjectClass *klass, void *data)
|
|
|
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{
|
2011-12-08 07:34:16 +04:00
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|
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DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 22:22:06 +04:00
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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|
2015-01-19 17:52:30 +03:00
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k->realize = pci_piix_ide_realize;
|
2011-12-04 22:22:06 +04:00
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k->exit = pci_piix_ide_exitfn;
|
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|
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k->vendor_id = PCI_VENDOR_ID_INTEL;
|
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|
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k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
|
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|
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k->class_id = PCI_CLASS_STORAGE_IDE;
|
2013-07-29 18:17:45 +04:00
|
|
|
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
2014-02-05 19:36:48 +04:00
|
|
|
dc->hotpluggable = false;
|
2011-12-04 22:22:06 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo piix3_ide_info = {
|
2011-12-08 07:34:16 +04:00
|
|
|
.name = "piix3-ide",
|
2013-07-17 20:44:48 +04:00
|
|
|
.parent = TYPE_PCI_IDE,
|
2011-12-08 07:34:16 +04:00
|
|
|
.class_init = piix3_ide_class_init,
|
2011-12-07 05:32:44 +04:00
|
|
|
};
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo piix3_ide_xen_info = {
|
2011-12-08 07:34:16 +04:00
|
|
|
.name = "piix3-ide-xen",
|
2013-07-17 20:44:48 +04:00
|
|
|
.parent = TYPE_PCI_IDE,
|
2016-03-06 21:44:30 +03:00
|
|
|
.class_init = piix3_ide_class_init,
|
2011-12-07 05:32:44 +04:00
|
|
|
};
|
|
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2011-12-04 22:22:06 +04:00
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static void piix4_ide_class_init(ObjectClass *klass, void *data)
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{
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2011-12-08 07:34:16 +04:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2011-12-04 22:22:06 +04:00
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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2015-01-19 17:52:30 +03:00
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k->realize = pci_piix_ide_realize;
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2011-12-04 22:22:06 +04:00
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k->exit = pci_piix_ide_exitfn;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
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k->class_id = PCI_CLASS_STORAGE_IDE;
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2013-07-29 18:17:45 +04:00
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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2014-02-05 19:36:48 +04:00
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dc->hotpluggable = false;
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2011-12-04 22:22:06 +04:00
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}
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2013-01-10 19:19:07 +04:00
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static const TypeInfo piix4_ide_info = {
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2011-12-08 07:34:16 +04:00
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.name = "piix4-ide",
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2013-07-17 20:44:48 +04:00
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.parent = TYPE_PCI_IDE,
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2011-12-08 07:34:16 +04:00
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.class_init = piix4_ide_class_init,
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2009-10-07 18:56:24 +04:00
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};
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2012-02-09 18:20:55 +04:00
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static void piix_ide_register_types(void)
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2009-10-07 18:56:24 +04:00
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{
|
2011-12-08 07:34:16 +04:00
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type_register_static(&piix3_ide_info);
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type_register_static(&piix3_ide_xen_info);
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|
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type_register_static(&piix4_ide_info);
|
2009-10-07 18:56:24 +04:00
|
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}
|
2012-02-09 18:20:55 +04:00
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type_init(piix_ide_register_types)
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