ide: convert to memory API
Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity
Anthony Liguori
parent
e1a99dbd9c
commit
a9deb8c69a
206
hw/ide/cmd646.c
206
hw/ide/cmd646.c
@ -44,35 +44,95 @@
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static void cmd646_update_irq(PCIIDEState *d);
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static void ide_map(PCIDevice *pci_dev, int region_num,
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pcibus_t addr, pcibus_t size, int type)
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static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
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IDEBus *bus;
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CMD646BAR *cmd646bar = opaque;
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if (region_num <= 3) {
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bus = &d->bus[(region_num >> 1)];
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if (region_num & 1) {
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register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
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register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
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if (addr != 2 || size != 1) {
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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return ide_status_read(cmd646bar->bus, addr + 2);
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}
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static void cmd646_cmd_write(void *opaque, target_phys_addr_t addr,
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uint64_t data, unsigned size)
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{
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CMD646BAR *cmd646bar = opaque;
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if (addr != 2 || size != 1) {
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return;
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}
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ide_cmd_write(cmd646bar->bus, addr + 2, data);
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}
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static MemoryRegionOps cmd646_cmd_ops = {
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.read = cmd646_cmd_read,
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.write = cmd646_cmd_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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CMD646BAR *cmd646bar = opaque;
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if (size == 1) {
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return ide_ioport_read(cmd646bar->bus, addr);
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} else if (addr == 0) {
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if (size == 2) {
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return ide_data_readw(cmd646bar->bus, addr);
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} else {
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register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
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register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
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return ide_data_readl(cmd646bar->bus, addr);
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}
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}
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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/* data ports */
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register_ioport_write(addr, 2, 2, ide_data_writew, bus);
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register_ioport_read(addr, 2, 2, ide_data_readw, bus);
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register_ioport_write(addr, 4, 4, ide_data_writel, bus);
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register_ioport_read(addr, 4, 4, ide_data_readl, bus);
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static void cmd646_data_write(void *opaque, target_phys_addr_t addr,
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uint64_t data, unsigned size)
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{
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CMD646BAR *cmd646bar = opaque;
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if (size == 1) {
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return ide_ioport_write(cmd646bar->bus, addr, data);
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} else if (addr == 0) {
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if (size == 2) {
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return ide_data_writew(cmd646bar->bus, addr, data);
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} else {
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return ide_data_writel(cmd646bar->bus, addr, data);
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}
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}
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}
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static uint32_t bmdma_readb_common(PCIIDEState *pci_dev, BMDMAState *bm,
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uint32_t addr)
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static MemoryRegionOps cmd646_data_ops = {
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.read = cmd646_data_read,
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.write = cmd646_data_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
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{
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IDEBus *bus = &d->bus[bus_num];
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CMD646BAR *bar = &d->cmd646_bar[bus_num];
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bar->bus = bus;
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bar->pci_dev = d;
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memory_region_init_io(&bar->cmd, &cmd646_cmd_ops, bar, "cmd646-cmd", 4);
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memory_region_init_io(&bar->data, &cmd646_data_ops, bar, "cmd646-data", 8);
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}
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static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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BMDMAState *bm = opaque;
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PCIIDEState *pci_dev = bm->pci_dev;
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uint32_t val;
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if (size != 1) {
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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switch(addr & 3) {
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case 0:
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val = bm->cmd;
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@ -100,31 +160,22 @@ static uint32_t bmdma_readb_common(PCIIDEState *pci_dev, BMDMAState *bm,
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return val;
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}
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static uint32_t bmdma_readb_0(void *opaque, uint32_t addr)
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static void bmdma_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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PCIIDEState *pci_dev = opaque;
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BMDMAState *bm = &pci_dev->bmdma[0];
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BMDMAState *bm = opaque;
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PCIIDEState *pci_dev = bm->pci_dev;
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return bmdma_readb_common(pci_dev, bm, addr);
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}
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if (size != 1) {
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return;
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}
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static uint32_t bmdma_readb_1(void *opaque, uint32_t addr)
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{
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PCIIDEState *pci_dev = opaque;
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BMDMAState *bm = &pci_dev->bmdma[1];
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return bmdma_readb_common(pci_dev, bm, addr);
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}
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static void bmdma_writeb_common(PCIIDEState *pci_dev, BMDMAState *bm,
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uint32_t addr, uint32_t val)
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{
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#ifdef DEBUG_IDE
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printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
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#endif
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switch(addr & 3) {
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case 0:
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bmdma_cmd_writeb(bm, addr, val);
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bmdma_cmd_writeb(bm, val);
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break;
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case 1:
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pci_dev->dev.config[MRDMODE] =
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@ -143,42 +194,25 @@ static void bmdma_writeb_common(PCIIDEState *pci_dev, BMDMAState *bm,
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}
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}
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static void bmdma_writeb_0(void *opaque, uint32_t addr, uint32_t val)
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static MemoryRegionOps cmd646_bmdma_ops = {
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.read = bmdma_read,
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.write = bmdma_write,
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};
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static void bmdma_setup_bar(PCIIDEState *d)
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{
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PCIIDEState *pci_dev = opaque;
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BMDMAState *bm = &pci_dev->bmdma[0];
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bmdma_writeb_common(pci_dev, bm, addr, val);
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}
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static void bmdma_writeb_1(void *opaque, uint32_t addr, uint32_t val)
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{
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PCIIDEState *pci_dev = opaque;
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BMDMAState *bm = &pci_dev->bmdma[1];
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bmdma_writeb_common(pci_dev, bm, addr, val);
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}
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static void bmdma_map(PCIDevice *pci_dev, int region_num,
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pcibus_t addr, pcibus_t size, int type)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
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BMDMAState *bm;
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int i;
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memory_region_init(&d->bmdma_bar, "cmd646-bmdma", 16);
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for(i = 0;i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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if (i == 0) {
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register_ioport_write(addr, 4, 1, bmdma_writeb_0, d);
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register_ioport_read(addr, 4, 1, bmdma_readb_0, d);
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} else {
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register_ioport_write(addr, 4, 1, bmdma_writeb_1, d);
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register_ioport_read(addr, 4, 1, bmdma_readb_1, d);
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}
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iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4);
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ioport_register(&bm->addr_ioport);
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addr += 8;
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bm = &d->bmdma[i];
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memory_region_init_io(&bm->extra_io, &cmd646_bmdma_ops, bm,
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"cmd646-bmdma-bus", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
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memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
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"cmd646-bmdma-ioport", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
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}
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}
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@ -234,11 +268,18 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
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pci_conf[0x51] |= 0x08; /* enable IDE1 */
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}
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pci_register_bar(dev, 0, 0x8, PCI_BASE_ADDRESS_SPACE_IO, ide_map);
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pci_register_bar(dev, 1, 0x4, PCI_BASE_ADDRESS_SPACE_IO, ide_map);
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pci_register_bar(dev, 2, 0x8, PCI_BASE_ADDRESS_SPACE_IO, ide_map);
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pci_register_bar(dev, 3, 0x4, PCI_BASE_ADDRESS_SPACE_IO, ide_map);
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pci_register_bar(dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
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setup_cmd646_bar(d, 0);
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setup_cmd646_bar(d, 1);
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pci_register_bar_region(dev, 0, PCI_BASE_ADDRESS_SPACE_IO,
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&d->cmd646_bar[0].data);
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pci_register_bar_region(dev, 1, PCI_BASE_ADDRESS_SPACE_IO,
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&d->cmd646_bar[0].cmd);
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pci_register_bar_region(dev, 2, PCI_BASE_ADDRESS_SPACE_IO,
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&d->cmd646_bar[1].data);
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pci_register_bar_region(dev, 3, PCI_BASE_ADDRESS_SPACE_IO,
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&d->cmd646_bar[1].cmd);
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bmdma_setup_bar(d);
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pci_register_bar_region(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
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/* TODO: RST# value should be 0 */
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pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
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@ -248,7 +289,7 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
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ide_bus_new(&d->bus[i], &d->dev.qdev, i);
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ide_init2(&d->bus[i], irq[i]);
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bmdma_init(&d->bus[i], &d->bmdma[i]);
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bmdma_init(&d->bus[i], &d->bmdma[i], d);
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d->bmdma[i].bus = &d->bus[i];
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qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
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&d->bmdma[i].dma);
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@ -259,6 +300,24 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
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return 0;
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}
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static int pci_cmd646_ide_exitfn(PCIDevice *dev)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
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unsigned i;
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for (i = 0; i < 2; ++i) {
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
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memory_region_destroy(&d->bmdma[i].extra_io);
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
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memory_region_destroy(&d->bmdma[i].addr_ioport);
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memory_region_destroy(&d->cmd646_bar[i].cmd);
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memory_region_destroy(&d->cmd646_bar[i].data);
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}
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memory_region_destroy(&d->bmdma_bar);
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return 0;
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}
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void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
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int secondary_ide_enabled)
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{
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@ -276,6 +335,7 @@ static PCIDeviceInfo cmd646_ide_info[] = {
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.qdev.name = "cmd646-ide",
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.qdev.size = sizeof(PCIIDEState),
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.init = pci_cmd646_ide_initfn,
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.exit = pci_cmd646_ide_exitfn,
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.vendor_id = PCI_VENDOR_ID_CMD,
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.device_id = PCI_DEVICE_ID_CMD_646,
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.revision = 0x07, // IDE controller revision
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25
hw/ide/pci.c
25
hw/ide/pci.c
@ -287,9 +287,8 @@ static void bmdma_irq(void *opaque, int n, int level)
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qemu_set_irq(bm->irq, level);
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}
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void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
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void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
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{
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BMDMAState *bm = opaque;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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@ -328,22 +327,24 @@ void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
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bm->cmd = val & 0x09;
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}
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static void bmdma_addr_read(IORange *ioport, uint64_t addr,
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unsigned width, uint64_t *data)
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static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
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unsigned width)
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{
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BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport);
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BMDMAState *bm = opaque;
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uint32_t mask = (1ULL << (width * 8)) - 1;
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uint64_t data;
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*data = (bm->addr >> (addr * 8)) & mask;
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data = (bm->addr >> (addr * 8)) & mask;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, (unsigned)*data);
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#endif
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return data;
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}
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static void bmdma_addr_write(IORange *ioport, uint64_t addr,
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unsigned width, uint64_t data)
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static void bmdma_addr_write(void *opaque, target_phys_addr_t addr,
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uint64_t data, unsigned width)
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{
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BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport);
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BMDMAState *bm = opaque;
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int shift = addr * 8;
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uint32_t mask = (1ULL << (width * 8)) - 1;
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@ -354,9 +355,10 @@ static void bmdma_addr_write(IORange *ioport, uint64_t addr,
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bm->addr |= ((data & mask) << shift) & ~3;
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}
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const IORangeOps bmdma_addr_ioport_ops = {
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MemoryRegionOps bmdma_addr_ioport_ops = {
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.read = bmdma_addr_read,
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.write = bmdma_addr_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static bool ide_bmdma_current_needed(void *opaque)
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@ -514,7 +516,7 @@ static const struct IDEDMAOps bmdma_ops = {
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.reset = bmdma_reset,
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};
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void bmdma_init(IDEBus *bus, BMDMAState *bm)
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void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
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{
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qemu_irq *irq;
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@ -527,4 +529,5 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm)
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bm->irq = bus->irq;
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irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
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bus->irq = *irq;
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bm->pci_dev = d;
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}
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19
hw/ide/pci.h
19
hw/ide/pci.h
@ -19,20 +19,31 @@ typedef struct BMDMAState {
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BlockDriverCompletionFunc *dma_cb;
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int64_t sector_num;
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uint32_t nsector;
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IORange addr_ioport;
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MemoryRegion addr_ioport;
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MemoryRegion extra_io;
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QEMUBH *bh;
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qemu_irq irq;
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/* Bit 0-2 and 7: BM status register
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* Bit 3-6: bus->error_status */
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uint8_t migration_compat_status;
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struct PCIIDEState *pci_dev;
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} BMDMAState;
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typedef struct CMD646BAR {
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MemoryRegion cmd;
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MemoryRegion data;
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IDEBus *bus;
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struct PCIIDEState *pci_dev;
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} CMD646BAR;
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typedef struct PCIIDEState {
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PCIDevice dev;
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IDEBus bus[2];
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BMDMAState bmdma[2];
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uint32_t secondary; /* used only for cmd646 */
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MemoryRegion bmdma_bar;
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CMD646BAR cmd646_bar[2]; /* used only for cmd646 */
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} PCIIDEState;
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@ -43,9 +54,9 @@ static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
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}
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void bmdma_init(IDEBus *bus, BMDMAState *bm);
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void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val);
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extern const IORangeOps bmdma_addr_ioport_ops;
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void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d);
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void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val);
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extern MemoryRegionOps bmdma_addr_ioport_ops;
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void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table);
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extern const VMStateDescription vmstate_ide_pci;
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@ -33,11 +33,15 @@
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#include <hw/ide/pci.h>
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static uint32_t bmdma_readb(void *opaque, uint32_t addr)
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static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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if (size != 1) {
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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switch(addr & 3) {
|
||||
case 0:
|
||||
val = bm->cmd;
|
||||
@ -55,36 +59,46 @@ static uint32_t bmdma_readb(void *opaque, uint32_t addr)
|
||||
return val;
|
||||
}
|
||||
|
||||
static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
|
||||
static void bmdma_write(void *opaque, target_phys_addr_t addr,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
BMDMAState *bm = opaque;
|
||||
|
||||
if (size != 1) {
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_IDE
|
||||
printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
|
||||
#endif
|
||||
switch(addr & 3) {
|
||||
case 0:
|
||||
return bmdma_cmd_writeb(bm, val);
|
||||
case 2:
|
||||
bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void bmdma_map(PCIDevice *pci_dev, int region_num,
|
||||
pcibus_t addr, pcibus_t size, int type)
|
||||
static MemoryRegionOps piix_bmdma_ops = {
|
||||
.read = bmdma_read,
|
||||
.write = bmdma_write,
|
||||
};
|
||||
|
||||
static void bmdma_setup_bar(PCIIDEState *d)
|
||||
{
|
||||
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
|
||||
int i;
|
||||
|
||||
memory_region_init(&d->bmdma_bar, "piix-bmdma-container", 16);
|
||||
for(i = 0;i < 2; i++) {
|
||||
BMDMAState *bm = &d->bmdma[i];
|
||||
|
||||
register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
|
||||
|
||||
register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
|
||||
register_ioport_read(addr, 4, 1, bmdma_readb, bm);
|
||||
|
||||
iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4);
|
||||
ioport_register(&bm->addr_ioport);
|
||||
addr += 8;
|
||||
memory_region_init_io(&bm->extra_io, &piix_bmdma_ops, bm,
|
||||
"piix-bmdma", 4);
|
||||
memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
|
||||
memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
|
||||
"bmdma", 4);
|
||||
memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
|
||||
}
|
||||
}
|
||||
|
||||
@ -124,7 +138,7 @@ static void pci_piix_init_ports(PCIIDEState *d) {
|
||||
ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
|
||||
ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));
|
||||
|
||||
bmdma_init(&d->bus[i], &d->bmdma[i]);
|
||||
bmdma_init(&d->bus[i], &d->bmdma[i], d);
|
||||
d->bmdma[i].bus = &d->bus[i];
|
||||
qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
|
||||
&d->bmdma[i].dma);
|
||||
@ -140,7 +154,9 @@ static int pci_piix_ide_initfn(PCIDevice *dev)
|
||||
|
||||
qemu_register_reset(piix3_reset, d);
|
||||
|
||||
pci_register_bar(&d->dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
|
||||
bmdma_setup_bar(d);
|
||||
pci_register_bar_region(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO,
|
||||
&d->bmdma_bar);
|
||||
|
||||
vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
|
||||
|
||||
@ -185,6 +201,22 @@ PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
|
||||
return dev;
|
||||
}
|
||||
|
||||
static int pci_piix_ide_exitfn(PCIDevice *dev)
|
||||
{
|
||||
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 2; ++i) {
|
||||
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
|
||||
memory_region_destroy(&d->bmdma[i].extra_io);
|
||||
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
|
||||
memory_region_destroy(&d->bmdma[i].addr_ioport);
|
||||
}
|
||||
memory_region_destroy(&d->bmdma_bar);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* hd_table must contain 4 block drivers */
|
||||
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
|
||||
PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
|
||||
@ -214,6 +246,7 @@ static PCIDeviceInfo piix_ide_info[] = {
|
||||
.qdev.no_user = 1,
|
||||
.no_hotplug = 1,
|
||||
.init = pci_piix_ide_initfn,
|
||||
.exit = pci_piix_ide_exitfn,
|
||||
.vendor_id = PCI_VENDOR_ID_INTEL,
|
||||
.device_id = PCI_DEVICE_ID_INTEL_82371SB_1,
|
||||
.class_id = PCI_CLASS_STORAGE_IDE,
|
||||
@ -231,6 +264,7 @@ static PCIDeviceInfo piix_ide_info[] = {
|
||||
.qdev.no_user = 1,
|
||||
.no_hotplug = 1,
|
||||
.init = pci_piix_ide_initfn,
|
||||
.exit = pci_piix_ide_exitfn,
|
||||
.vendor_id = PCI_VENDOR_ID_INTEL,
|
||||
.device_id = PCI_DEVICE_ID_INTEL_82371AB,
|
||||
.class_id = PCI_CLASS_STORAGE_IDE,
|
||||
|
||||
65
hw/ide/via.c
65
hw/ide/via.c
@ -34,11 +34,16 @@
|
||||
|
||||
#include <hw/ide/pci.h>
|
||||
|
||||
static uint32_t bmdma_readb(void *opaque, uint32_t addr)
|
||||
static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
|
||||
unsigned size)
|
||||
{
|
||||
BMDMAState *bm = opaque;
|
||||
uint32_t val;
|
||||
|
||||
if (size != 1) {
|
||||
return ((uint64_t)1 << (size * 8)) - 1;
|
||||
}
|
||||
|
||||
switch (addr & 3) {
|
||||
case 0:
|
||||
val = bm->cmd;
|
||||
@ -56,13 +61,21 @@ static uint32_t bmdma_readb(void *opaque, uint32_t addr)
|
||||
return val;
|
||||
}
|
||||
|
||||
static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
|
||||
static void bmdma_write(void *opaque, target_phys_addr_t addr,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
BMDMAState *bm = opaque;
|
||||
|
||||
if (size != 1) {
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_IDE
|
||||
printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
|
||||
#endif
|
||||
switch (addr & 3) {
|
||||
case 0:
|
||||
return bmdma_cmd_writeb(bm, val);
|
||||
case 2:
|
||||
bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
|
||||
break;
|
||||
@ -70,23 +83,25 @@ static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
|
||||
}
|
||||
}
|
||||
|
||||
static void bmdma_map(PCIDevice *pci_dev, int region_num,
|
||||
pcibus_t addr, pcibus_t size, int type)
|
||||
static MemoryRegionOps via_bmdma_ops = {
|
||||
.read = bmdma_read,
|
||||
.write = bmdma_write,
|
||||
};
|
||||
|
||||
static void bmdma_setup_bar(PCIIDEState *d)
|
||||
{
|
||||
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
|
||||
int i;
|
||||
|
||||
memory_region_init(&d->bmdma_bar, "via-bmdma-container", 16);
|
||||
for(i = 0;i < 2; i++) {
|
||||
BMDMAState *bm = &d->bmdma[i];
|
||||
|
||||
register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
|
||||
|
||||
register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
|
||||
register_ioport_read(addr, 4, 1, bmdma_readb, bm);
|
||||
|
||||
iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4);
|
||||
ioport_register(&bm->addr_ioport);
|
||||
addr += 8;
|
||||
memory_region_init_io(&bm->extra_io, &via_bmdma_ops, bm,
|
||||
"via-bmdma", 4);
|
||||
memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
|
||||
memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
|
||||
"bmdma", 4);
|
||||
memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
|
||||
}
|
||||
}
|
||||
|
||||
@ -147,7 +162,7 @@ static void vt82c686b_init_ports(PCIIDEState *d) {
|
||||
ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
|
||||
ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));
|
||||
|
||||
bmdma_init(&d->bus[i], &d->bmdma[i]);
|
||||
bmdma_init(&d->bus[i], &d->bmdma[i], d);
|
||||
d->bmdma[i].bus = &d->bus[i];
|
||||
qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
|
||||
&d->bmdma[i].dma);
|
||||
@ -164,8 +179,9 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
|
||||
pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
|
||||
|
||||
qemu_register_reset(via_reset, d);
|
||||
pci_register_bar(&d->dev, 4, 0x10,
|
||||
PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
|
||||
bmdma_setup_bar(d);
|
||||
pci_register_bar_region(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO,
|
||||
&d->bmdma_bar);
|
||||
|
||||
vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
|
||||
|
||||
@ -174,6 +190,22 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vt82c686b_ide_exitfn(PCIDevice *dev)
|
||||
{
|
||||
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 2; ++i) {
|
||||
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
|
||||
memory_region_destroy(&d->bmdma[i].extra_io);
|
||||
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
|
||||
memory_region_destroy(&d->bmdma[i].addr_ioport);
|
||||
}
|
||||
memory_region_destroy(&d->bmdma_bar);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
|
||||
{
|
||||
PCIDevice *dev;
|
||||
@ -187,6 +219,7 @@ static PCIDeviceInfo via_ide_info = {
|
||||
.qdev.size = sizeof(PCIIDEState),
|
||||
.qdev.no_user = 1,
|
||||
.init = vt82c686b_ide_initfn,
|
||||
.exit = vt82c686b_ide_exitfn,
|
||||
.vendor_id = PCI_VENDOR_ID_VIA,
|
||||
.device_id = PCI_DEVICE_ID_VIA_IDE,
|
||||
.revision = 0x06,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user