2018-03-02 15:31:13 +03:00
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/*
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* SiFive PLIC (Platform Level Interrupt Controller)
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This provides a parameterizable interrupt controller based on SiFive's PLIC.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:31:58 +03:00
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#include "qapi/error.h"
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2018-03-02 15:31:13 +03:00
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#include "qemu/log.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2018-03-02 15:31:13 +03:00
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#include "qemu/error-report.h"
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#include "hw/sysbus.h"
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2019-03-15 23:05:36 +03:00
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#include "hw/pci/msi.h"
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2019-08-12 08:23:51 +03:00
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#include "hw/qdev-properties.h"
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2020-09-03 13:40:17 +03:00
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#include "hw/intc/sifive_plic.h"
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2018-03-02 15:31:13 +03:00
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#include "target/riscv/cpu.h"
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2020-10-26 14:55:30 +03:00
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#include "migration/vmstate.h"
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2018-03-02 15:31:13 +03:00
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#define RISCV_DEBUG_PLIC 0
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static PLICMode char_to_mode(char c)
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{
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switch (c) {
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case 'U': return PLICMode_U;
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case 'S': return PLICMode_S;
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case 'H': return PLICMode_H;
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case 'M': return PLICMode_M;
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default:
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error_report("plic: invalid mode '%c'", c);
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exit(1);
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}
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}
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static char mode_to_char(PLICMode m)
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{
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switch (m) {
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case PLICMode_U: return 'U';
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case PLICMode_S: return 'S';
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case PLICMode_H: return 'H';
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case PLICMode_M: return 'M';
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default: return '?';
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}
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}
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static void sifive_plic_print_state(SiFivePLICState *plic)
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{
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int i;
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int addrid;
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/* pending */
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qemu_log("pending : ");
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for (i = plic->bitfield_words - 1; i >= 0; i--) {
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qemu_log("%08x", plic->pending[i]);
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}
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qemu_log("\n");
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/* pending */
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qemu_log("claimed : ");
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for (i = plic->bitfield_words - 1; i >= 0; i--) {
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qemu_log("%08x", plic->claimed[i]);
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}
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qemu_log("\n");
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for (addrid = 0; addrid < plic->num_addrs; addrid++) {
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qemu_log("hart%d-%c enable: ",
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plic->addr_config[addrid].hartid,
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mode_to_char(plic->addr_config[addrid].mode));
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for (i = plic->bitfield_words - 1; i >= 0; i--) {
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qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
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}
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qemu_log("\n");
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}
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}
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2018-04-10 11:02:46 +03:00
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static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
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2018-03-02 15:31:13 +03:00
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{
|
2020-09-23 13:56:46 +03:00
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uint32_t old, new, cmp = qatomic_read(a);
|
2018-04-10 11:02:46 +03:00
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do {
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old = cmp;
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new = (old & ~mask) | (value & mask);
|
2020-09-23 13:56:46 +03:00
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cmp = qatomic_cmpxchg(a, old, new);
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2018-04-10 11:02:46 +03:00
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} while (old != cmp);
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return old;
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2018-03-02 15:31:13 +03:00
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}
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2018-04-10 11:02:46 +03:00
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static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
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2018-03-02 15:31:13 +03:00
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{
|
2018-04-10 11:02:46 +03:00
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atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
|
2018-03-02 15:31:13 +03:00
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}
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2018-04-10 11:02:46 +03:00
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static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
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2018-03-02 15:31:13 +03:00
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{
|
2018-04-10 11:02:46 +03:00
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atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
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}
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static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
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{
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int i, j;
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2018-03-02 15:31:13 +03:00
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for (i = 0; i < plic->bitfield_words; i++) {
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uint32_t pending_enabled_not_claimed =
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(plic->pending[i] & ~plic->claimed[i]) &
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plic->enable[addrid * plic->bitfield_words + i];
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if (!pending_enabled_not_claimed) {
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continue;
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}
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for (j = 0; j < 32; j++) {
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int irq = (i << 5) + j;
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uint32_t prio = plic->source_priority[irq];
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int enabled = pending_enabled_not_claimed & (1 << j);
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if (enabled && prio > plic->target_priority[addrid]) {
|
2018-04-10 11:02:46 +03:00
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return 1;
|
2018-03-02 15:31:13 +03:00
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}
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}
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}
|
2018-04-10 11:02:46 +03:00
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return 0;
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2018-03-02 15:31:13 +03:00
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}
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static void sifive_plic_update(SiFivePLICState *plic)
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{
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int addrid;
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/* raise irq on harts where this irq is enabled */
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for (addrid = 0; addrid < plic->num_addrs; addrid++) {
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uint32_t hartid = plic->addr_config[addrid].hartid;
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PLICMode mode = plic->addr_config[addrid].mode;
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CPUState *cpu = qemu_get_cpu(hartid);
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CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
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if (!env) {
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continue;
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}
|
2018-04-10 11:02:46 +03:00
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int level = sifive_plic_irqs_pending(plic, addrid);
|
2018-03-02 15:31:13 +03:00
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switch (mode) {
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case PLICMode_M:
|
2018-04-09 00:25:25 +03:00
|
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riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
|
2018-03-02 15:31:13 +03:00
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break;
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case PLICMode_S:
|
2018-04-09 00:25:25 +03:00
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riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
|
2018-03-02 15:31:13 +03:00
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break;
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default:
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|
break;
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}
|
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}
|
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|
if (RISCV_DEBUG_PLIC) {
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|
|
sifive_plic_print_state(plic);
|
|
|
|
}
|
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|
}
|
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static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
|
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|
|
{
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int i, j;
|
2020-06-18 23:23:43 +03:00
|
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|
uint32_t max_irq = 0;
|
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|
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uint32_t max_prio = plic->target_priority[addrid];
|
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|
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|
2018-03-02 15:31:13 +03:00
|
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for (i = 0; i < plic->bitfield_words; i++) {
|
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|
|
uint32_t pending_enabled_not_claimed =
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(plic->pending[i] & ~plic->claimed[i]) &
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plic->enable[addrid * plic->bitfield_words + i];
|
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|
|
if (!pending_enabled_not_claimed) {
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|
|
continue;
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|
|
|
}
|
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|
for (j = 0; j < 32; j++) {
|
|
|
|
int irq = (i << 5) + j;
|
|
|
|
uint32_t prio = plic->source_priority[irq];
|
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|
|
int enabled = pending_enabled_not_claimed & (1 << j);
|
2020-06-18 23:23:43 +03:00
|
|
|
if (enabled && prio > max_prio) {
|
|
|
|
max_irq = irq;
|
|
|
|
max_prio = prio;
|
2018-03-02 15:31:13 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2020-06-18 23:23:43 +03:00
|
|
|
|
|
|
|
if (max_irq) {
|
|
|
|
sifive_plic_set_pending(plic, max_irq, false);
|
|
|
|
sifive_plic_set_claimed(plic, max_irq, true);
|
|
|
|
}
|
|
|
|
return max_irq;
|
2018-03-02 15:31:13 +03:00
|
|
|
}
|
|
|
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|
|
|
static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
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|
|
|
SiFivePLICState *plic = opaque;
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|
|
|
|
|
|
/* writes must be 4 byte words */
|
|
|
|
if ((addr & 0x3) != 0) {
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|
goto err;
|
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|
|
}
|
|
|
|
|
|
|
|
if (addr >= plic->priority_base && /* 4 bytes per source */
|
|
|
|
addr < plic->priority_base + (plic->num_sources << 2))
|
|
|
|
{
|
2019-04-04 21:15:23 +03:00
|
|
|
uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
|
2018-03-02 15:31:13 +03:00
|
|
|
if (RISCV_DEBUG_PLIC) {
|
|
|
|
qemu_log("plic: read priority: irq=%d priority=%d\n",
|
|
|
|
irq, plic->source_priority[irq]);
|
|
|
|
}
|
|
|
|
return plic->source_priority[irq];
|
|
|
|
} else if (addr >= plic->pending_base && /* 1 bit per source */
|
|
|
|
addr < plic->pending_base + (plic->num_sources >> 3))
|
|
|
|
{
|
2018-12-14 03:18:54 +03:00
|
|
|
uint32_t word = (addr - plic->pending_base) >> 2;
|
2018-03-02 15:31:13 +03:00
|
|
|
if (RISCV_DEBUG_PLIC) {
|
|
|
|
qemu_log("plic: read pending: word=%d value=%d\n",
|
|
|
|
word, plic->pending[word]);
|
|
|
|
}
|
|
|
|
return plic->pending[word];
|
|
|
|
} else if (addr >= plic->enable_base && /* 1 bit per source */
|
|
|
|
addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
|
|
|
|
{
|
|
|
|
uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
|
|
|
|
uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
|
|
|
|
if (wordid < plic->bitfield_words) {
|
|
|
|
if (RISCV_DEBUG_PLIC) {
|
|
|
|
qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
|
|
|
|
plic->addr_config[addrid].hartid,
|
|
|
|
mode_to_char(plic->addr_config[addrid].mode), wordid,
|
|
|
|
plic->enable[addrid * plic->bitfield_words + wordid]);
|
|
|
|
}
|
|
|
|
return plic->enable[addrid * plic->bitfield_words + wordid];
|
|
|
|
}
|
|
|
|
} else if (addr >= plic->context_base && /* 1 bit per source */
|
|
|
|
addr < plic->context_base + plic->num_addrs * plic->context_stride)
|
|
|
|
{
|
|
|
|
uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
|
|
|
|
uint32_t contextid = (addr & (plic->context_stride - 1));
|
|
|
|
if (contextid == 0) {
|
|
|
|
if (RISCV_DEBUG_PLIC) {
|
|
|
|
qemu_log("plic: read priority: hart%d-%c priority=%x\n",
|
|
|
|
plic->addr_config[addrid].hartid,
|
|
|
|
mode_to_char(plic->addr_config[addrid].mode),
|
|
|
|
plic->target_priority[addrid]);
|
|
|
|
}
|
|
|
|
return plic->target_priority[addrid];
|
|
|
|
} else if (contextid == 4) {
|
|
|
|
uint32_t value = sifive_plic_claim(plic, addrid);
|
|
|
|
if (RISCV_DEBUG_PLIC) {
|
|
|
|
qemu_log("plic: read claim: hart%d-%c irq=%x\n",
|
|
|
|
plic->addr_config[addrid].hartid,
|
|
|
|
mode_to_char(plic->addr_config[addrid].mode),
|
|
|
|
value);
|
|
|
|
}
|
2020-06-19 00:06:49 +03:00
|
|
|
sifive_plic_update(plic);
|
2018-03-02 15:31:13 +03:00
|
|
|
return value;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
err:
|
2019-04-04 21:15:34 +03:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: Invalid register read 0x%" HWADDR_PRIx "\n",
|
|
|
|
__func__, addr);
|
2018-03-02 15:31:13 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
SiFivePLICState *plic = opaque;
|
|
|
|
|
|
|
|
/* writes must be 4 byte words */
|
|
|
|
if ((addr & 0x3) != 0) {
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (addr >= plic->priority_base && /* 4 bytes per source */
|
|
|
|
addr < plic->priority_base + (plic->num_sources << 2))
|
|
|
|
{
|
2019-04-04 21:15:23 +03:00
|
|
|
uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
|
2018-03-02 15:31:13 +03:00
|
|
|
plic->source_priority[irq] = value & 7;
|
|
|
|
if (RISCV_DEBUG_PLIC) {
|
|
|
|
qemu_log("plic: write priority: irq=%d priority=%d\n",
|
|
|
|
irq, plic->source_priority[irq]);
|
|
|
|
}
|
2020-06-19 00:06:49 +03:00
|
|
|
sifive_plic_update(plic);
|
2018-03-02 15:31:13 +03:00
|
|
|
return;
|
|
|
|
} else if (addr >= plic->pending_base && /* 1 bit per source */
|
|
|
|
addr < plic->pending_base + (plic->num_sources >> 3))
|
|
|
|
{
|
2019-04-04 21:15:34 +03:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: invalid pending write: 0x%" HWADDR_PRIx "",
|
|
|
|
__func__, addr);
|
2018-03-02 15:31:13 +03:00
|
|
|
return;
|
|
|
|
} else if (addr >= plic->enable_base && /* 1 bit per source */
|
|
|
|
addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
|
|
|
|
{
|
|
|
|
uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
|
|
|
|
uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
|
|
|
|
if (wordid < plic->bitfield_words) {
|
|
|
|
plic->enable[addrid * plic->bitfield_words + wordid] = value;
|
|
|
|
if (RISCV_DEBUG_PLIC) {
|
|
|
|
qemu_log("plic: write enable: hart%d-%c word=%d value=%x\n",
|
|
|
|
plic->addr_config[addrid].hartid,
|
|
|
|
mode_to_char(plic->addr_config[addrid].mode), wordid,
|
|
|
|
plic->enable[addrid * plic->bitfield_words + wordid]);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else if (addr >= plic->context_base && /* 4 bytes per reg */
|
|
|
|
addr < plic->context_base + plic->num_addrs * plic->context_stride)
|
|
|
|
{
|
|
|
|
uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
|
|
|
|
uint32_t contextid = (addr & (plic->context_stride - 1));
|
|
|
|
if (contextid == 0) {
|
|
|
|
if (RISCV_DEBUG_PLIC) {
|
|
|
|
qemu_log("plic: write priority: hart%d-%c priority=%x\n",
|
|
|
|
plic->addr_config[addrid].hartid,
|
|
|
|
mode_to_char(plic->addr_config[addrid].mode),
|
|
|
|
plic->target_priority[addrid]);
|
|
|
|
}
|
|
|
|
if (value <= plic->num_priorities) {
|
|
|
|
plic->target_priority[addrid] = value;
|
|
|
|
sifive_plic_update(plic);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
} else if (contextid == 4) {
|
|
|
|
if (RISCV_DEBUG_PLIC) {
|
|
|
|
qemu_log("plic: write claim: hart%d-%c irq=%x\n",
|
|
|
|
plic->addr_config[addrid].hartid,
|
|
|
|
mode_to_char(plic->addr_config[addrid].mode),
|
|
|
|
(uint32_t)value);
|
|
|
|
}
|
|
|
|
if (value < plic->num_sources) {
|
|
|
|
sifive_plic_set_claimed(plic, value, false);
|
|
|
|
sifive_plic_update(plic);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
err:
|
2019-04-04 21:15:34 +03:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: Invalid register write 0x%" HWADDR_PRIx "\n",
|
|
|
|
__func__, addr);
|
2018-03-02 15:31:13 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps sifive_plic_ops = {
|
|
|
|
.read = sifive_plic_read,
|
|
|
|
.write = sifive_plic_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static Property sifive_plic_properties[] = {
|
|
|
|
DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
|
2020-05-15 07:55:33 +03:00
|
|
|
DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
|
2018-03-02 15:31:13 +03:00
|
|
|
DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
|
|
|
|
DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
|
|
|
|
DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
|
|
|
|
DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
|
|
|
|
DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
|
|
|
|
DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
|
|
|
|
DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
|
|
|
|
DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
|
|
|
|
DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* parse PLIC hart/mode address offset config
|
|
|
|
*
|
|
|
|
* "M" 1 hart with M mode
|
|
|
|
* "MS,MS" 2 harts, 0-1 with M and S mode
|
|
|
|
* "M,MS,MS,MS,MS" 5 harts, 0 with M mode, 1-5 with M and S mode
|
|
|
|
*/
|
|
|
|
static void parse_hart_config(SiFivePLICState *plic)
|
|
|
|
{
|
|
|
|
int addrid, hartid, modes;
|
|
|
|
const char *p;
|
|
|
|
char c;
|
|
|
|
|
|
|
|
/* count and validate hart/mode combinations */
|
|
|
|
addrid = 0, hartid = 0, modes = 0;
|
|
|
|
p = plic->hart_config;
|
|
|
|
while ((c = *p++)) {
|
|
|
|
if (c == ',') {
|
2019-03-16 04:20:11 +03:00
|
|
|
addrid += ctpop8(modes);
|
2018-03-02 15:31:13 +03:00
|
|
|
modes = 0;
|
|
|
|
hartid++;
|
|
|
|
} else {
|
|
|
|
int m = 1 << char_to_mode(c);
|
|
|
|
if (modes == (modes | m)) {
|
|
|
|
error_report("plic: duplicate mode '%c' in config: %s",
|
|
|
|
c, plic->hart_config);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
modes |= m;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (modes) {
|
2019-03-16 04:20:11 +03:00
|
|
|
addrid += ctpop8(modes);
|
2018-03-02 15:31:13 +03:00
|
|
|
}
|
|
|
|
hartid++;
|
|
|
|
|
|
|
|
plic->num_addrs = addrid;
|
2020-05-15 07:55:33 +03:00
|
|
|
plic->num_harts = hartid;
|
|
|
|
|
|
|
|
/* store hart/mode combinations */
|
2018-03-02 15:31:13 +03:00
|
|
|
plic->addr_config = g_new(PLICAddr, plic->num_addrs);
|
2020-05-15 07:55:33 +03:00
|
|
|
addrid = 0, hartid = plic->hartid_base;
|
2018-03-02 15:31:13 +03:00
|
|
|
p = plic->hart_config;
|
|
|
|
while ((c = *p++)) {
|
|
|
|
if (c == ',') {
|
|
|
|
hartid++;
|
|
|
|
} else {
|
|
|
|
plic->addr_config[addrid].addrid = addrid;
|
|
|
|
plic->addr_config[addrid].hartid = hartid;
|
|
|
|
plic->addr_config[addrid].mode = char_to_mode(c);
|
|
|
|
addrid++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sifive_plic_irq_request(void *opaque, int irq, int level)
|
|
|
|
{
|
|
|
|
SiFivePLICState *plic = opaque;
|
|
|
|
if (RISCV_DEBUG_PLIC) {
|
|
|
|
qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
|
|
|
|
}
|
|
|
|
sifive_plic_set_pending(plic, irq, level > 0);
|
|
|
|
sifive_plic_update(plic);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sifive_plic_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
SiFivePLICState *plic = SIFIVE_PLIC(dev);
|
2019-03-16 04:20:20 +03:00
|
|
|
int i;
|
2018-03-02 15:31:13 +03:00
|
|
|
|
|
|
|
memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
|
|
|
|
TYPE_SIFIVE_PLIC, plic->aperture_size);
|
|
|
|
parse_hart_config(plic);
|
|
|
|
plic->bitfield_words = (plic->num_sources + 31) >> 5;
|
2020-10-26 14:55:30 +03:00
|
|
|
plic->num_enables = plic->bitfield_words * plic->num_addrs;
|
2018-03-02 15:31:13 +03:00
|
|
|
plic->source_priority = g_new0(uint32_t, plic->num_sources);
|
|
|
|
plic->target_priority = g_new(uint32_t, plic->num_addrs);
|
|
|
|
plic->pending = g_new0(uint32_t, plic->bitfield_words);
|
|
|
|
plic->claimed = g_new0(uint32_t, plic->bitfield_words);
|
2020-10-26 14:55:30 +03:00
|
|
|
plic->enable = g_new0(uint32_t, plic->num_enables);
|
2018-03-02 15:31:13 +03:00
|
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
|
2018-04-26 23:54:12 +03:00
|
|
|
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
|
2019-03-16 04:20:20 +03:00
|
|
|
|
|
|
|
/* We can't allow the supervisor to control SEIP as this would allow the
|
|
|
|
* supervisor to clear a pending external interrupt which will result in
|
|
|
|
* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
|
|
|
|
* hardware controlled when a PLIC is attached.
|
|
|
|
*/
|
2020-05-15 07:55:33 +03:00
|
|
|
for (i = 0; i < plic->num_harts; i++) {
|
|
|
|
RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
|
2019-03-16 04:20:20 +03:00
|
|
|
if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
|
|
|
|
error_report("SEIP already claimed");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
2019-03-28 12:18:53 +03:00
|
|
|
|
2019-03-15 23:05:36 +03:00
|
|
|
msi_nonbroken = true;
|
2018-03-02 15:31:13 +03:00
|
|
|
}
|
|
|
|
|
2020-10-26 14:55:30 +03:00
|
|
|
static const VMStateDescription vmstate_sifive_plic = {
|
|
|
|
.name = "riscv_sifive_plic",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
|
|
|
|
num_sources, 0,
|
|
|
|
vmstate_info_uint32, uint32_t),
|
|
|
|
VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
|
|
|
|
num_addrs, 0,
|
|
|
|
vmstate_info_uint32, uint32_t),
|
|
|
|
VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
|
|
|
|
vmstate_info_uint32, uint32_t),
|
|
|
|
VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
|
|
|
|
vmstate_info_uint32, uint32_t),
|
|
|
|
VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
|
|
|
|
vmstate_info_uint32, uint32_t),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2018-03-02 15:31:13 +03:00
|
|
|
static void sifive_plic_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
2020-01-10 18:30:32 +03:00
|
|
|
device_class_set_props(dc, sifive_plic_properties);
|
2018-03-02 15:31:13 +03:00
|
|
|
dc->realize = sifive_plic_realize;
|
2020-10-26 14:55:30 +03:00
|
|
|
dc->vmsd = &vmstate_sifive_plic;
|
2018-03-02 15:31:13 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo sifive_plic_info = {
|
|
|
|
.name = TYPE_SIFIVE_PLIC,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(SiFivePLICState),
|
|
|
|
.class_init = sifive_plic_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void sifive_plic_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&sifive_plic_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(sifive_plic_register_types)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Create PLIC device.
|
|
|
|
*/
|
|
|
|
DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
|
2020-05-15 07:55:33 +03:00
|
|
|
uint32_t hartid_base, uint32_t num_sources,
|
|
|
|
uint32_t num_priorities, uint32_t priority_base,
|
|
|
|
uint32_t pending_base, uint32_t enable_base,
|
|
|
|
uint32_t enable_stride, uint32_t context_base,
|
|
|
|
uint32_t context_stride, uint32_t aperture_size)
|
2018-03-02 15:31:13 +03:00
|
|
|
{
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:31:58 +03:00
|
|
|
DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
|
2018-03-02 15:31:13 +03:00
|
|
|
assert(enable_stride == (enable_stride & -enable_stride));
|
|
|
|
assert(context_stride == (context_stride & -context_stride));
|
|
|
|
qdev_prop_set_string(dev, "hart-config", hart_config);
|
2020-05-15 07:55:33 +03:00
|
|
|
qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
|
2018-03-02 15:31:13 +03:00
|
|
|
qdev_prop_set_uint32(dev, "num-sources", num_sources);
|
|
|
|
qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
|
|
|
|
qdev_prop_set_uint32(dev, "priority-base", priority_base);
|
|
|
|
qdev_prop_set_uint32(dev, "pending-base", pending_base);
|
|
|
|
qdev_prop_set_uint32(dev, "enable-base", enable_base);
|
|
|
|
qdev_prop_set_uint32(dev, "enable-stride", enable_stride);
|
|
|
|
qdev_prop_set_uint32(dev, "context-base", context_base);
|
|
|
|
qdev_prop_set_uint32(dev, "context-stride", context_stride);
|
|
|
|
qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:32:34 +03:00
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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2018-03-02 15:31:13 +03:00
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
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return dev;
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}
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