RISC-V: Allow interrupt controllers to claim interrupts
We can't allow the supervisor to control SEIP as this would allow the supervisor to clear a pending external interrupt which will result in lost a interrupt in the case a PLIC is attached. The SEIP bit must be hardware controlled when a PLIC is attached. This logic was previously hard-coded so SEIP was always masked even if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts so that the PLIC can register control of SEIP. In the case of models without a PLIC (spike), the SEIP bit remains software controlled. This interface allows for hardware control of supervisor timer and software interrupts by other interrupt controller models. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
parent
244df42133
commit
e3e7039cc2
@ -23,6 +23,7 @@
|
||||
#include "qemu/error-report.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "target/riscv/cpu.h"
|
||||
#include "sysemu/sysemu.h"
|
||||
#include "hw/riscv/sifive_plic.h"
|
||||
|
||||
#define RISCV_DEBUG_PLIC 0
|
||||
@ -431,6 +432,7 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
|
||||
static void sifive_plic_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
SiFivePLICState *plic = SIFIVE_PLIC(dev);
|
||||
int i;
|
||||
|
||||
memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
|
||||
TYPE_SIFIVE_PLIC, plic->aperture_size);
|
||||
@ -443,6 +445,19 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
|
||||
plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
|
||||
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
|
||||
|
||||
/* We can't allow the supervisor to control SEIP as this would allow the
|
||||
* supervisor to clear a pending external interrupt which will result in
|
||||
* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
|
||||
* hardware controlled when a PLIC is attached.
|
||||
*/
|
||||
for (i = 0; i < smp_cpus; i++) {
|
||||
RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
|
||||
if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
|
||||
error_report("SEIP already claimed");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void sifive_plic_class_init(ObjectClass *klass, void *data)
|
||||
|
@ -140,6 +140,7 @@ struct CPURISCVState {
|
||||
* mip is 32-bits to allow atomic_read on 32-bit hosts.
|
||||
*/
|
||||
uint32_t mip;
|
||||
uint32_t miclaim;
|
||||
|
||||
target_ulong mie;
|
||||
target_ulong mideleg;
|
||||
@ -266,6 +267,7 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
|
||||
#define cpu_mmu_index riscv_cpu_mmu_index
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
|
||||
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
|
||||
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
|
||||
#endif
|
||||
|
@ -72,6 +72,17 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
|
||||
{
|
||||
CPURISCVState *env = &cpu->env;
|
||||
if (env->miclaim & interrupts) {
|
||||
return -1;
|
||||
} else {
|
||||
env->miclaim |= interrupts;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* iothread_mutex must be held */
|
||||
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
|
||||
{
|
||||
|
@ -550,16 +550,10 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
|
||||
target_ulong new_value, target_ulong write_mask)
|
||||
{
|
||||
RISCVCPU *cpu = riscv_env_get_cpu(env);
|
||||
target_ulong mask = write_mask & delegable_ints;
|
||||
/* Allow software control of delegable interrupts not claimed by hardware */
|
||||
target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
|
||||
uint32_t old_mip;
|
||||
|
||||
/* We can't allow the supervisor to control SEIP as this would allow the
|
||||
* supervisor to clear a pending external interrupt which will result in
|
||||
* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
|
||||
* hardware controlled when a PLIC is attached. This should be an option
|
||||
* for CPUs with software-delegated Supervisor External Interrupts. */
|
||||
mask &= ~MIP_SEIP;
|
||||
|
||||
if (mask) {
|
||||
qemu_mutex_lock_iothread();
|
||||
old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
|
||||
|
Loading…
Reference in New Issue
Block a user