2020-06-26 06:31:07 +03:00
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/*
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* ARM v8.5-MemTag Operations
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*
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* Copyright (c) 2020 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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2022-02-07 11:27:56 +03:00
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#include "qemu/log.h"
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2020-06-26 06:31:07 +03:00
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#include "cpu.h"
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#include "internals.h"
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#include "exec/exec-all.h"
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2020-06-26 06:31:42 +03:00
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#include "exec/ram_addr.h"
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2020-06-26 06:31:07 +03:00
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#include "exec/cpu_ldst.h"
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#include "exec/helper-proto.h"
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2020-07-27 18:12:11 +03:00
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#include "qapi/error.h"
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#include "qemu/guest-random.h"
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2020-06-26 06:31:07 +03:00
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static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude)
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{
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if (exclude == 0xffff) {
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return 0;
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}
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if (offset == 0) {
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while (exclude & (1 << tag)) {
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tag = (tag + 1) & 15;
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}
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} else {
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do {
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do {
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tag = (tag + 1) & 15;
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} while (exclude & (1 << tag));
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} while (--offset > 0);
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}
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return tag;
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}
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2020-06-26 06:31:13 +03:00
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/**
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* allocation_tag_mem:
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* @env: the cpu environment
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* @ptr_mmu_idx: the addressing regime to use for the virtual address
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* @ptr: the virtual address for which to look up tag memory
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* @ptr_access: the access to use for the virtual address
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* @ptr_size: the number of bytes in the normal memory access
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* @tag_access: the access to use for the tag memory
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* @tag_size: the number of bytes in the tag memory access
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* @ra: the return address for exception handling
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*
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* Our tag memory is formatted as a sequence of little-endian nibbles.
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* That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two
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* tags, with the tag at [3:0] for the lower addr and the tag at [7:4]
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* for the higher addr.
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*
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* Here, resolve the physical address from the virtual address, and return
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* a pointer to the corresponding tag byte. Exit with exception if the
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* virtual address is not accessible for @ptr_access.
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*
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* The @ptr_size and @tag_size values may not have an obvious relation
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* due to the alignment of @ptr, and the number of tag checks required.
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*
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* If there is no tag storage corresponding to @ptr, return NULL.
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*/
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static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
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uint64_t ptr, MMUAccessType ptr_access,
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int ptr_size, MMUAccessType tag_access,
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int tag_size, uintptr_t ra)
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{
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2020-06-26 06:31:42 +03:00
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#ifdef CONFIG_USER_ONLY
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2021-02-12 21:49:00 +03:00
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uint64_t clean_ptr = useronly_clean_ptr(ptr);
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int flags = page_get_flags(clean_ptr);
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uint8_t *tags;
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uintptr_t index;
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2021-04-06 20:40:21 +03:00
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if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) {
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2021-09-18 03:49:05 +03:00
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cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access,
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!(flags & PAGE_VALID), ra);
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2021-02-12 21:49:00 +03:00
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}
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/* Require both MAP_ANON and PROT_MTE for the page. */
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if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) {
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return NULL;
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}
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tags = page_get_target_data(clean_ptr);
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if (tags == NULL) {
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size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1);
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tags = page_alloc_target_data(clean_ptr, alloc_size);
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assert(tags != NULL);
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}
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index = extract32(ptr, LOG2_TAG_GRANULE + 1,
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TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1);
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return tags + index;
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2020-06-26 06:31:42 +03:00
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#else
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uintptr_t index;
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2022-08-20 00:20:37 +03:00
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CPUTLBEntryFull *full;
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2020-06-26 06:31:42 +03:00
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int in_page, flags;
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ram_addr_t ptr_ra;
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hwaddr ptr_paddr, tag_paddr, xlat;
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MemoryRegion *mr;
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ARMASIdx tag_asi;
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AddressSpace *tag_as;
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void *host;
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/*
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* Probe the first byte of the virtual address. This raises an
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* exception for inaccessible pages, and resolves the virtual address
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* into the softmmu tlb.
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*
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2021-04-16 21:31:04 +03:00
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* When RA == 0, this is for mte_probe. The page is expected to be
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2020-06-26 06:31:42 +03:00
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* valid. Indicate to probe_access_flags no-fault, then assert that
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* we received a valid page.
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*/
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flags = probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx,
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ra == 0, &host, ra);
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assert(!(flags & TLB_INVALID_MASK));
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/*
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2022-08-20 00:20:37 +03:00
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* Find the CPUTLBEntryFull for ptr. This *must* be present in the TLB
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2020-06-26 06:31:42 +03:00
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* because we just found the mapping.
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* TODO: Perhaps there should be a cputlb helper that returns a
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* matching tlb entry + iotlb entry.
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*/
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index = tlb_index(env, ptr_mmu_idx, ptr);
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# ifdef CONFIG_DEBUG_TCG
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{
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CPUTLBEntry *entry = tlb_entry(env, ptr_mmu_idx, ptr);
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target_ulong comparator = (ptr_access == MMU_DATA_LOAD
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? entry->addr_read
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: tlb_addr_write(entry));
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g_assert(tlb_hit(comparator, ptr));
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}
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# endif
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2022-08-20 00:20:37 +03:00
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full = &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index];
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2020-06-26 06:31:42 +03:00
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/* If the virtual page MemAttr != Tagged, access unchecked. */
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2022-08-20 00:20:37 +03:00
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if (!arm_tlb_mte_tagged(&full->attrs)) {
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2020-06-26 06:31:42 +03:00
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return NULL;
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}
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/*
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* If not backed by host ram, there is no tag storage: access unchecked.
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* This is probably a guest os bug though, so log it.
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*/
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if (unlikely(flags & TLB_MMIO)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Page @ 0x%" PRIx64 " indicates Tagged Normal memory "
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"but is not backed by host ram\n", ptr);
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return NULL;
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}
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/*
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* The Normal memory access can extend to the next page. E.g. a single
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* 8-byte access to the last byte of a page will check only the last
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* tag on the first page.
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* Any page access exception has priority over tag check exception.
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*/
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in_page = -(ptr | TARGET_PAGE_MASK);
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if (unlikely(ptr_size > in_page)) {
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void *ignore;
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flags |= probe_access_flags(env, ptr + in_page, ptr_access,
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ptr_mmu_idx, ra == 0, &ignore, ra);
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assert(!(flags & TLB_INVALID_MASK));
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}
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/* Any debug exception has priority over a tag check exception. */
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if (unlikely(flags & TLB_WATCHPOINT)) {
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int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE;
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assert(ra != 0);
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cpu_check_watchpoint(env_cpu(env), ptr, ptr_size,
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2022-08-20 00:20:37 +03:00
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full->attrs, wp, ra);
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2020-06-26 06:31:42 +03:00
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}
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/*
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* Find the physical address within the normal mem space.
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* The memory region lookup must succeed because TLB_MMIO was
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* not set in the cputlb lookup above.
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*/
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mr = memory_region_from_host(host, &ptr_ra);
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tcg_debug_assert(mr != NULL);
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tcg_debug_assert(memory_region_is_ram(mr));
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ptr_paddr = ptr_ra;
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do {
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ptr_paddr += mr->addr;
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mr = mr->container;
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} while (mr);
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/* Convert to the physical address in tag space. */
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tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1);
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/* Look up the address in tag space. */
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2022-08-20 00:20:37 +03:00
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tag_asi = full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
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2020-06-26 06:31:42 +03:00
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tag_as = cpu_get_address_space(env_cpu(env), tag_asi);
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mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL,
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tag_access == MMU_DATA_STORE,
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2022-08-20 00:20:37 +03:00
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full->attrs);
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2020-06-26 06:31:42 +03:00
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/*
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* Note that @mr will never be NULL. If there is nothing in the address
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* space at @tag_paddr, the translation will return the unallocated memory
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* region. For our purposes, the result must be ram.
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*/
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if (unlikely(!memory_region_is_ram(mr))) {
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/* ??? Failure is a board configuration error. */
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qemu_log_mask(LOG_UNIMP,
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"Tag Memory @ 0x%" HWADDR_PRIx " not found for "
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"Normal Memory @ 0x%" HWADDR_PRIx "\n",
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tag_paddr, ptr_paddr);
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return NULL;
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}
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/*
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* Ensure the tag memory is dirty on write, for migration.
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* Tag memory can never contain code or display memory (vga).
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*/
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if (tag_access == MMU_DATA_STORE) {
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ram_addr_t tag_ra = memory_region_get_ram_addr(mr) + xlat;
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cpu_physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION);
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}
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return memory_region_get_ram_ptr(mr) + xlat;
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#endif
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2020-06-26 06:31:13 +03:00
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}
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2020-06-26 06:31:07 +03:00
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uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm)
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{
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uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16);
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2020-07-27 18:12:11 +03:00
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int rrnd = extract32(env->cp15.gcr_el1, 16, 1);
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2020-06-26 06:31:07 +03:00
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int start = extract32(env->cp15.rgsr_el1, 0, 4);
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int seed = extract32(env->cp15.rgsr_el1, 8, 16);
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2020-07-27 18:12:11 +03:00
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int offset, i, rtag;
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/*
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* Our IMPDEF choice for GCR_EL1.RRND==1 is to continue to use the
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* deterministic algorithm. Except that with RRND==1 the kernel is
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* not required to have set RGSR_EL1.SEED != 0, which is required for
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* the deterministic algorithm to function. So we force a non-zero
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* SEED for that case.
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*/
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if (unlikely(seed == 0) && rrnd) {
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do {
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Error *err = NULL;
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uint16_t two;
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if (qemu_guest_getrandom(&two, sizeof(two), &err) < 0) {
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/*
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* Failed, for unknown reasons in the crypto subsystem.
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* Best we can do is log the reason and use a constant seed.
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*/
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qemu_log_mask(LOG_UNIMP, "IRG: Crypto failure: %s\n",
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error_get_pretty(err));
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error_free(err);
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two = 1;
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}
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seed = two;
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} while (seed == 0);
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}
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2020-06-26 06:31:07 +03:00
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/* RandomTag */
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for (i = offset = 0; i < 4; ++i) {
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/* NextRandomTagBit */
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int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^
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extract32(seed, 2, 1) ^ extract32(seed, 0, 1));
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seed = (top << 15) | (seed >> 1);
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offset |= top << i;
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}
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rtag = choose_nonexcluded_tag(start, offset, exclude);
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env->cp15.rgsr_el1 = rtag | (seed << 8);
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return address_with_allocation_tag(rn, rtag);
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}
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2020-06-26 06:31:09 +03:00
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uint64_t HELPER(addsubg)(CPUARMState *env, uint64_t ptr,
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int32_t offset, uint32_t tag_offset)
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{
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int start_tag = allocation_tag_from_addr(ptr);
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uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16);
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int rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude);
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return address_with_allocation_tag(ptr + offset, rtag);
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}
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2020-06-26 06:31:13 +03:00
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static int load_tag1(uint64_t ptr, uint8_t *mem)
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{
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int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4;
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return extract32(*mem, ofs, 4);
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}
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uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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uint8_t *mem;
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int rtag = 0;
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/* Trap if accessing an invalid page. */
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mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, 1,
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MMU_DATA_LOAD, 1, GETPC());
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/* Load if page supports tags. */
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if (mem) {
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rtag = load_tag1(ptr, mem);
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}
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return address_with_allocation_tag(xt, rtag);
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}
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static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra)
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{
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if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) {
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|
|
arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE,
|
|
|
|
cpu_mmu_index(env, false), ra);
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* For use in a non-parallel context, store to the given nibble. */
|
|
|
|
static void store_tag1(uint64_t ptr, uint8_t *mem, int tag)
|
|
|
|
{
|
|
|
|
int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4;
|
|
|
|
*mem = deposit32(*mem, ofs, 4, tag);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* For use in a parallel context, atomically store to the given nibble. */
|
|
|
|
static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag)
|
|
|
|
{
|
|
|
|
int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4;
|
2020-09-23 13:56:46 +03:00
|
|
|
uint8_t old = qatomic_read(mem);
|
2020-06-26 06:31:13 +03:00
|
|
|
|
|
|
|
while (1) {
|
|
|
|
uint8_t new = deposit32(old, ofs, 4, tag);
|
2020-09-23 13:56:46 +03:00
|
|
|
uint8_t cmp = qatomic_cmpxchg(mem, old, new);
|
2020-06-26 06:31:13 +03:00
|
|
|
if (likely(cmp == old)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
old = cmp;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
typedef void stg_store1(uint64_t, uint8_t *, int);
|
|
|
|
|
|
|
|
static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt,
|
|
|
|
uintptr_t ra, stg_store1 store1)
|
|
|
|
{
|
|
|
|
int mmu_idx = cpu_mmu_index(env, false);
|
|
|
|
uint8_t *mem;
|
|
|
|
|
|
|
|
check_tag_aligned(env, ptr, ra);
|
|
|
|
|
|
|
|
/* Trap if accessing an invalid page. */
|
|
|
|
mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, TAG_GRANULE,
|
|
|
|
MMU_DATA_STORE, 1, ra);
|
|
|
|
|
|
|
|
/* Store if page supports tags. */
|
|
|
|
if (mem) {
|
|
|
|
store1(ptr, mem, allocation_tag_from_addr(xt));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void HELPER(stg)(CPUARMState *env, uint64_t ptr, uint64_t xt)
|
|
|
|
{
|
|
|
|
do_stg(env, ptr, xt, GETPC(), store_tag1);
|
|
|
|
}
|
|
|
|
|
|
|
|
void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt)
|
|
|
|
{
|
|
|
|
do_stg(env, ptr, xt, GETPC(), store_tag1_parallel);
|
|
|
|
}
|
|
|
|
|
|
|
|
void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr)
|
|
|
|
{
|
|
|
|
int mmu_idx = cpu_mmu_index(env, false);
|
|
|
|
uintptr_t ra = GETPC();
|
|
|
|
|
|
|
|
check_tag_aligned(env, ptr, ra);
|
|
|
|
probe_write(env, ptr, TAG_GRANULE, mmu_idx, ra);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt,
|
|
|
|
uintptr_t ra, stg_store1 store1)
|
|
|
|
{
|
|
|
|
int mmu_idx = cpu_mmu_index(env, false);
|
|
|
|
int tag = allocation_tag_from_addr(xt);
|
|
|
|
uint8_t *mem1, *mem2;
|
|
|
|
|
|
|
|
check_tag_aligned(env, ptr, ra);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Trap if accessing an invalid page(s).
|
|
|
|
* This takes priority over !allocation_tag_access_enabled.
|
|
|
|
*/
|
|
|
|
if (ptr & TAG_GRANULE) {
|
|
|
|
/* Two stores unaligned mod TAG_GRANULE*2 -- modify two bytes. */
|
|
|
|
mem1 = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
|
|
|
|
TAG_GRANULE, MMU_DATA_STORE, 1, ra);
|
|
|
|
mem2 = allocation_tag_mem(env, mmu_idx, ptr + TAG_GRANULE,
|
|
|
|
MMU_DATA_STORE, TAG_GRANULE,
|
|
|
|
MMU_DATA_STORE, 1, ra);
|
|
|
|
|
|
|
|
/* Store if page(s) support tags. */
|
|
|
|
if (mem1) {
|
|
|
|
store1(TAG_GRANULE, mem1, tag);
|
|
|
|
}
|
|
|
|
if (mem2) {
|
|
|
|
store1(0, mem2, tag);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Two stores aligned mod TAG_GRANULE*2 -- modify one byte. */
|
|
|
|
mem1 = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
|
|
|
|
2 * TAG_GRANULE, MMU_DATA_STORE, 1, ra);
|
|
|
|
if (mem1) {
|
|
|
|
tag |= tag << 4;
|
2020-09-23 13:56:46 +03:00
|
|
|
qatomic_set(mem1, tag);
|
2020-06-26 06:31:13 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void HELPER(st2g)(CPUARMState *env, uint64_t ptr, uint64_t xt)
|
|
|
|
{
|
|
|
|
do_st2g(env, ptr, xt, GETPC(), store_tag1);
|
|
|
|
}
|
|
|
|
|
|
|
|
void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt)
|
|
|
|
{
|
|
|
|
do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel);
|
|
|
|
}
|
|
|
|
|
|
|
|
void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
|
|
|
|
{
|
|
|
|
int mmu_idx = cpu_mmu_index(env, false);
|
|
|
|
uintptr_t ra = GETPC();
|
|
|
|
int in_page = -(ptr | TARGET_PAGE_MASK);
|
|
|
|
|
|
|
|
check_tag_aligned(env, ptr, ra);
|
|
|
|
|
|
|
|
if (likely(in_page >= 2 * TAG_GRANULE)) {
|
|
|
|
probe_write(env, ptr, 2 * TAG_GRANULE, mmu_idx, ra);
|
|
|
|
} else {
|
|
|
|
probe_write(env, ptr, TAG_GRANULE, mmu_idx, ra);
|
|
|
|
probe_write(env, ptr + TAG_GRANULE, TAG_GRANULE, mmu_idx, ra);
|
|
|
|
}
|
|
|
|
}
|
2020-06-26 06:31:17 +03:00
|
|
|
|
|
|
|
#define LDGM_STGM_SIZE (4 << GMID_EL1_BS)
|
|
|
|
|
|
|
|
uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
|
|
|
|
{
|
|
|
|
int mmu_idx = cpu_mmu_index(env, false);
|
|
|
|
uintptr_t ra = GETPC();
|
|
|
|
void *tag_mem;
|
|
|
|
|
|
|
|
ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
|
|
|
|
|
|
|
|
/* Trap if accessing an invalid page. */
|
|
|
|
tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
|
|
|
|
LDGM_STGM_SIZE, MMU_DATA_LOAD,
|
|
|
|
LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
|
|
|
|
|
|
|
|
/* The tag is squashed to zero if the page does not support tags. */
|
|
|
|
if (!tag_mem) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
|
|
|
|
/*
|
|
|
|
* We are loading 64-bits worth of tags. The ordering of elements
|
|
|
|
* within the word corresponds to a 64-bit little-endian operation.
|
|
|
|
*/
|
|
|
|
return ldq_le_p(tag_mem);
|
|
|
|
}
|
|
|
|
|
|
|
|
void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
|
|
|
|
{
|
|
|
|
int mmu_idx = cpu_mmu_index(env, false);
|
|
|
|
uintptr_t ra = GETPC();
|
|
|
|
void *tag_mem;
|
|
|
|
|
|
|
|
ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
|
|
|
|
|
|
|
|
/* Trap if accessing an invalid page. */
|
|
|
|
tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
|
|
|
|
LDGM_STGM_SIZE, MMU_DATA_LOAD,
|
|
|
|
LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Tag store only happens if the page support tags,
|
|
|
|
* and if the OS has enabled access to the tags.
|
|
|
|
*/
|
|
|
|
if (!tag_mem) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
|
|
|
|
/*
|
|
|
|
* We are storing 64-bits worth of tags. The ordering of elements
|
|
|
|
* within the word corresponds to a 64-bit little-endian operation.
|
|
|
|
*/
|
|
|
|
stq_le_p(tag_mem, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
|
|
|
|
{
|
|
|
|
uintptr_t ra = GETPC();
|
|
|
|
int mmu_idx = cpu_mmu_index(env, false);
|
|
|
|
int log2_dcz_bytes, log2_tag_bytes;
|
|
|
|
intptr_t dcz_bytes, tag_bytes;
|
|
|
|
uint8_t *mem;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In arm_cpu_realizefn, we assert that dcz > LOG2_TAG_GRANULE+1,
|
|
|
|
* i.e. 32 bytes, which is an unreasonably small dcz anyway,
|
|
|
|
* to make sure that we can access one complete tag byte here.
|
|
|
|
*/
|
|
|
|
log2_dcz_bytes = env_archcpu(env)->dcz_blocksize + 2;
|
|
|
|
log2_tag_bytes = log2_dcz_bytes - (LOG2_TAG_GRANULE + 1);
|
|
|
|
dcz_bytes = (intptr_t)1 << log2_dcz_bytes;
|
|
|
|
tag_bytes = (intptr_t)1 << log2_tag_bytes;
|
|
|
|
ptr &= -dcz_bytes;
|
|
|
|
|
|
|
|
mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, dcz_bytes,
|
|
|
|
MMU_DATA_STORE, tag_bytes, ra);
|
|
|
|
if (mem) {
|
|
|
|
int tag_pair = (val & 0xf) * 0x11;
|
|
|
|
memset(mem, tag_pair, tag_bytes);
|
|
|
|
}
|
|
|
|
}
|
2020-06-26 06:31:21 +03:00
|
|
|
|
2021-06-16 22:56:14 +03:00
|
|
|
static void mte_sync_check_fail(CPUARMState *env, uint32_t desc,
|
|
|
|
uint64_t dirty_ptr, uintptr_t ra)
|
|
|
|
{
|
|
|
|
int is_write, syn;
|
|
|
|
|
|
|
|
env->exception.vaddress = dirty_ptr;
|
|
|
|
|
|
|
|
is_write = FIELD_EX32(desc, MTEDESC, WRITE);
|
|
|
|
syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, is_write,
|
|
|
|
0x11);
|
|
|
|
raise_exception_ra(env, EXCP_DATA_ABORT, syn, exception_target_el(env), ra);
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mte_async_check_fail(CPUARMState *env, uint64_t dirty_ptr,
|
|
|
|
uintptr_t ra, ARMMMUIdx arm_mmu_idx, int el)
|
|
|
|
{
|
|
|
|
int select;
|
|
|
|
|
|
|
|
if (regime_has_2_ranges(arm_mmu_idx)) {
|
|
|
|
select = extract64(dirty_ptr, 55, 1);
|
|
|
|
} else {
|
|
|
|
select = 0;
|
|
|
|
}
|
|
|
|
env->cp15.tfsr_el[el] |= 1 << select;
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
|
|
/*
|
|
|
|
* Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT,
|
|
|
|
* which then sends a SIGSEGV when the thread is next scheduled.
|
|
|
|
* This cpu will return to the main loop at the end of the TB,
|
|
|
|
* which is rather sooner than "normal". But the alternative
|
|
|
|
* is waiting until the next syscall.
|
|
|
|
*/
|
|
|
|
qemu_cpu_kick(env_cpu(env));
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2020-06-26 06:31:23 +03:00
|
|
|
/* Record a tag check failure. */
|
2020-08-28 12:02:44 +03:00
|
|
|
static void mte_check_fail(CPUARMState *env, uint32_t desc,
|
2020-06-26 06:31:23 +03:00
|
|
|
uint64_t dirty_ptr, uintptr_t ra)
|
|
|
|
{
|
2020-08-28 12:02:44 +03:00
|
|
|
int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
|
2020-06-26 06:31:23 +03:00
|
|
|
ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
|
2021-06-16 22:56:14 +03:00
|
|
|
int el, reg_el, tcf;
|
2020-06-26 06:31:23 +03:00
|
|
|
uint64_t sctlr;
|
|
|
|
|
|
|
|
reg_el = regime_el(env, arm_mmu_idx);
|
|
|
|
sctlr = env->cp15.sctlr_el[reg_el];
|
|
|
|
|
2021-02-19 23:18:20 +03:00
|
|
|
switch (arm_mmu_idx) {
|
|
|
|
case ARMMMUIdx_E10_0:
|
|
|
|
case ARMMMUIdx_E20_0:
|
|
|
|
el = 0;
|
2020-06-26 06:31:23 +03:00
|
|
|
tcf = extract64(sctlr, 38, 2);
|
2021-02-19 23:18:20 +03:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
el = reg_el;
|
2020-06-26 06:31:23 +03:00
|
|
|
tcf = extract64(sctlr, 40, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (tcf) {
|
|
|
|
case 1:
|
2021-05-26 15:18:46 +03:00
|
|
|
/* Tag check fail causes a synchronous exception. */
|
2021-06-16 22:56:14 +03:00
|
|
|
mte_sync_check_fail(env, desc, dirty_ptr, ra);
|
|
|
|
break;
|
2020-06-26 06:31:23 +03:00
|
|
|
|
|
|
|
case 0:
|
|
|
|
/*
|
|
|
|
* Tag check fail does not affect the PE.
|
|
|
|
* We eliminate this case by not setting MTE_ACTIVE
|
|
|
|
* in tb_flags, so that we never make this runtime call.
|
|
|
|
*/
|
|
|
|
g_assert_not_reached();
|
|
|
|
|
|
|
|
case 2:
|
|
|
|
/* Tag check fail causes asynchronous flag set. */
|
2021-06-16 22:56:14 +03:00
|
|
|
mte_async_check_fail(env, dirty_ptr, ra, arm_mmu_idx, el);
|
2020-06-26 06:31:23 +03:00
|
|
|
break;
|
|
|
|
|
2021-06-16 22:56:14 +03:00
|
|
|
case 3:
|
|
|
|
/*
|
|
|
|
* Tag check fail causes asynchronous flag set for stores, or
|
|
|
|
* a synchronous exception for loads.
|
|
|
|
*/
|
|
|
|
if (FIELD_EX32(desc, MTEDESC, WRITE)) {
|
|
|
|
mte_async_check_fail(env, dirty_ptr, ra, arm_mmu_idx, el);
|
|
|
|
} else {
|
|
|
|
mte_sync_check_fail(env, desc, dirty_ptr, ra);
|
|
|
|
}
|
2020-06-26 06:31:23 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-06-26 06:31:24 +03:00
|
|
|
/**
|
|
|
|
* checkN:
|
|
|
|
* @tag: tag memory to test
|
|
|
|
* @odd: true to begin testing at tags at odd nibble
|
|
|
|
* @cmp: the tag to compare against
|
|
|
|
* @count: number of tags to test
|
|
|
|
*
|
|
|
|
* Return the number of successful tests.
|
|
|
|
* Thus a return value < @count indicates a failure.
|
|
|
|
*
|
|
|
|
* A note about sizes: count is expected to be small.
|
|
|
|
*
|
|
|
|
* The most common use will be LDP/STP of two integer registers,
|
|
|
|
* which means 16 bytes of memory touching at most 2 tags, but
|
|
|
|
* often the access is aligned and thus just 1 tag.
|
|
|
|
*
|
|
|
|
* Using AdvSIMD LD/ST (multiple), one can access 64 bytes of memory,
|
|
|
|
* touching at most 5 tags. SVE LDR/STR (vector) with the default
|
|
|
|
* vector length is also 64 bytes; the maximum architectural length
|
|
|
|
* is 256 bytes touching at most 9 tags.
|
|
|
|
*
|
|
|
|
* The loop below uses 7 logical operations and 1 memory operation
|
|
|
|
* per tag pair. An implementation that loads an aligned word and
|
|
|
|
* uses masking to ignore adjacent tags requires 18 logical operations
|
|
|
|
* and thus does not begin to pay off until 6 tags.
|
|
|
|
* Which, according to the survey above, is unlikely to be common.
|
|
|
|
*/
|
|
|
|
static int checkN(uint8_t *mem, int odd, int cmp, int count)
|
|
|
|
{
|
|
|
|
int n = 0, diff;
|
|
|
|
|
|
|
|
/* Replicate the test tag and compare. */
|
|
|
|
cmp *= 0x11;
|
|
|
|
diff = *mem++ ^ cmp;
|
|
|
|
|
|
|
|
if (odd) {
|
|
|
|
goto start_odd;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (1) {
|
|
|
|
/* Test even tag. */
|
|
|
|
if (unlikely((diff) & 0x0f)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (++n == count) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
start_odd:
|
|
|
|
/* Test odd tag. */
|
|
|
|
if (unlikely((diff) & 0xf0)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (++n == count) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
diff = *mem++ ^ cmp;
|
|
|
|
}
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
2021-04-16 21:30:59 +03:00
|
|
|
/**
|
|
|
|
* mte_probe_int() - helper for mte_probe and mte_check
|
|
|
|
* @env: CPU environment
|
|
|
|
* @desc: MTEDESC descriptor
|
|
|
|
* @ptr: virtual address of the base of the access
|
|
|
|
* @fault: return virtual address of the first check failure
|
|
|
|
*
|
|
|
|
* Internal routine for both mte_probe and mte_check.
|
|
|
|
* Return zero on failure, filling in *fault.
|
|
|
|
* Return negative on trivial success for tbi disabled.
|
|
|
|
* Return positive on success with tbi enabled.
|
|
|
|
*/
|
|
|
|
static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr,
|
2021-04-16 21:31:02 +03:00
|
|
|
uintptr_t ra, uint64_t *fault)
|
2020-06-26 06:31:24 +03:00
|
|
|
{
|
|
|
|
int mmu_idx, ptr_tag, bit55;
|
2021-04-16 21:30:58 +03:00
|
|
|
uint64_t ptr_last, prev_page, next_page;
|
|
|
|
uint64_t tag_first, tag_last;
|
|
|
|
uint64_t tag_byte_first, tag_byte_last;
|
2021-04-16 21:31:02 +03:00
|
|
|
uint32_t sizem1, tag_count, tag_size, n, c;
|
2020-06-26 06:31:24 +03:00
|
|
|
uint8_t *mem1, *mem2;
|
|
|
|
MMUAccessType type;
|
|
|
|
|
|
|
|
bit55 = extract64(ptr, 55, 1);
|
2021-04-16 21:30:59 +03:00
|
|
|
*fault = ptr;
|
2020-06-26 06:31:24 +03:00
|
|
|
|
|
|
|
/* If TBI is disabled, the access is unchecked, and ptr is not dirty. */
|
|
|
|
if (unlikely(!tbi_check(desc, bit55))) {
|
2021-04-16 21:30:59 +03:00
|
|
|
return -1;
|
2020-06-26 06:31:24 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
ptr_tag = allocation_tag_from_addr(ptr);
|
|
|
|
|
|
|
|
if (tcma_check(desc, bit55, ptr_tag)) {
|
2021-04-16 21:30:59 +03:00
|
|
|
return 1;
|
2020-06-26 06:31:24 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
|
|
|
|
type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD;
|
2021-04-16 21:31:02 +03:00
|
|
|
sizem1 = FIELD_EX32(desc, MTEDESC, SIZEM1);
|
2020-06-26 06:31:24 +03:00
|
|
|
|
2021-04-16 21:30:58 +03:00
|
|
|
/* Find the addr of the end of the access */
|
2021-04-16 21:31:02 +03:00
|
|
|
ptr_last = ptr + sizem1;
|
2020-06-26 06:31:24 +03:00
|
|
|
|
|
|
|
/* Round the bounds to the tag granule, and compute the number of tags. */
|
|
|
|
tag_first = QEMU_ALIGN_DOWN(ptr, TAG_GRANULE);
|
2021-04-16 21:30:58 +03:00
|
|
|
tag_last = QEMU_ALIGN_DOWN(ptr_last, TAG_GRANULE);
|
|
|
|
tag_count = ((tag_last - tag_first) / TAG_GRANULE) + 1;
|
2020-06-26 06:31:24 +03:00
|
|
|
|
|
|
|
/* Round the bounds to twice the tag granule, and compute the bytes. */
|
|
|
|
tag_byte_first = QEMU_ALIGN_DOWN(ptr, 2 * TAG_GRANULE);
|
2021-04-16 21:30:58 +03:00
|
|
|
tag_byte_last = QEMU_ALIGN_DOWN(ptr_last, 2 * TAG_GRANULE);
|
2020-06-26 06:31:24 +03:00
|
|
|
|
|
|
|
/* Locate the page boundaries. */
|
|
|
|
prev_page = ptr & TARGET_PAGE_MASK;
|
|
|
|
next_page = prev_page + TARGET_PAGE_SIZE;
|
|
|
|
|
2021-06-12 22:57:07 +03:00
|
|
|
if (likely(tag_last - prev_page < TARGET_PAGE_SIZE)) {
|
2020-06-26 06:31:24 +03:00
|
|
|
/* Memory access stays on one page. */
|
2021-04-16 21:30:58 +03:00
|
|
|
tag_size = ((tag_byte_last - tag_byte_first) / (2 * TAG_GRANULE)) + 1;
|
2021-04-16 21:31:02 +03:00
|
|
|
mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, sizem1 + 1,
|
2020-06-26 06:31:24 +03:00
|
|
|
MMU_DATA_LOAD, tag_size, ra);
|
|
|
|
if (!mem1) {
|
2021-04-16 21:30:59 +03:00
|
|
|
return 1;
|
2020-06-26 06:31:24 +03:00
|
|
|
}
|
|
|
|
/* Perform all of the comparisons. */
|
|
|
|
n = checkN(mem1, ptr & TAG_GRANULE, ptr_tag, tag_count);
|
|
|
|
} else {
|
|
|
|
/* Memory access crosses to next page. */
|
|
|
|
tag_size = (next_page - tag_byte_first) / (2 * TAG_GRANULE);
|
|
|
|
mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, next_page - ptr,
|
|
|
|
MMU_DATA_LOAD, tag_size, ra);
|
|
|
|
|
2021-04-16 21:30:58 +03:00
|
|
|
tag_size = ((tag_byte_last - next_page) / (2 * TAG_GRANULE)) + 1;
|
2020-06-26 06:31:24 +03:00
|
|
|
mem2 = allocation_tag_mem(env, mmu_idx, next_page, type,
|
2021-04-16 21:30:58 +03:00
|
|
|
ptr_last - next_page + 1,
|
2020-06-26 06:31:24 +03:00
|
|
|
MMU_DATA_LOAD, tag_size, ra);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Perform all of the comparisons.
|
|
|
|
* Note the possible but unlikely case of the operation spanning
|
|
|
|
* two pages that do not both have tagging enabled.
|
|
|
|
*/
|
|
|
|
n = c = (next_page - tag_first) / TAG_GRANULE;
|
|
|
|
if (mem1) {
|
|
|
|
n = checkN(mem1, ptr & TAG_GRANULE, ptr_tag, c);
|
|
|
|
}
|
|
|
|
if (n == c) {
|
|
|
|
if (!mem2) {
|
2021-04-16 21:30:59 +03:00
|
|
|
return 1;
|
2020-06-26 06:31:24 +03:00
|
|
|
}
|
|
|
|
n += checkN(mem2, 0, ptr_tag, tag_count - c);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-16 21:30:59 +03:00
|
|
|
if (likely(n == tag_count)) {
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2020-06-26 06:31:24 +03:00
|
|
|
/*
|
2021-04-16 21:30:58 +03:00
|
|
|
* If we failed, we know which granule. For the first granule, the
|
|
|
|
* failure address is @ptr, the first byte accessed. Otherwise the
|
|
|
|
* failure address is the first byte of the nth granule.
|
2020-06-26 06:31:24 +03:00
|
|
|
*/
|
2021-04-16 21:30:59 +03:00
|
|
|
if (n > 0) {
|
|
|
|
*fault = tag_first + n * TAG_GRANULE;
|
2020-06-26 06:31:24 +03:00
|
|
|
}
|
2021-04-16 21:30:59 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-04-16 21:31:03 +03:00
|
|
|
uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra)
|
2021-04-16 21:30:59 +03:00
|
|
|
{
|
|
|
|
uint64_t fault;
|
2021-04-16 21:31:02 +03:00
|
|
|
int ret = mte_probe_int(env, desc, ptr, ra, &fault);
|
2020-06-26 06:31:24 +03:00
|
|
|
|
2021-04-16 21:30:59 +03:00
|
|
|
if (unlikely(ret == 0)) {
|
|
|
|
mte_check_fail(env, desc, fault, ra);
|
|
|
|
} else if (ret < 0) {
|
|
|
|
return ptr;
|
|
|
|
}
|
2020-06-26 06:31:24 +03:00
|
|
|
return useronly_clean_ptr(ptr);
|
|
|
|
}
|
|
|
|
|
2021-04-16 21:31:03 +03:00
|
|
|
uint64_t HELPER(mte_check)(CPUARMState *env, uint32_t desc, uint64_t ptr)
|
2020-06-26 06:31:22 +03:00
|
|
|
{
|
2021-04-16 21:31:03 +03:00
|
|
|
return mte_check(env, desc, ptr, GETPC());
|
2021-04-16 21:31:00 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2021-04-16 21:31:04 +03:00
|
|
|
* No-fault version of mte_check, to be used by SVE for MemSingleNF.
|
2021-04-16 21:31:00 +03:00
|
|
|
* Returns false if the access is Checked and the check failed. This
|
|
|
|
* is only intended to probe the tag -- the validity of the page must
|
|
|
|
* be checked beforehand.
|
|
|
|
*/
|
2021-04-16 21:31:04 +03:00
|
|
|
bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr)
|
2021-04-16 21:31:00 +03:00
|
|
|
{
|
|
|
|
uint64_t fault;
|
2021-04-16 21:31:02 +03:00
|
|
|
int ret = mte_probe_int(env, desc, ptr, 0, &fault);
|
2021-04-16 21:31:00 +03:00
|
|
|
|
|
|
|
return ret != 0;
|
|
|
|
}
|
|
|
|
|
2020-06-26 06:31:25 +03:00
|
|
|
/*
|
|
|
|
* Perform an MTE checked access for DC_ZVA.
|
|
|
|
*/
|
|
|
|
uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr)
|
|
|
|
{
|
|
|
|
uintptr_t ra = GETPC();
|
|
|
|
int log2_dcz_bytes, log2_tag_bytes;
|
|
|
|
int mmu_idx, bit55;
|
|
|
|
intptr_t dcz_bytes, tag_bytes, i;
|
|
|
|
void *mem;
|
|
|
|
uint64_t ptr_tag, mem_tag, align_ptr;
|
|
|
|
|
|
|
|
bit55 = extract64(ptr, 55, 1);
|
|
|
|
|
|
|
|
/* If TBI is disabled, the access is unchecked, and ptr is not dirty. */
|
|
|
|
if (unlikely(!tbi_check(desc, bit55))) {
|
|
|
|
return ptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
ptr_tag = allocation_tag_from_addr(ptr);
|
|
|
|
|
|
|
|
if (tcma_check(desc, bit55, ptr_tag)) {
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In arm_cpu_realizefn, we asserted that dcz > LOG2_TAG_GRANULE+1,
|
|
|
|
* i.e. 32 bytes, which is an unreasonably small dcz anyway, to make
|
|
|
|
* sure that we can access one complete tag byte here.
|
|
|
|
*/
|
|
|
|
log2_dcz_bytes = env_archcpu(env)->dcz_blocksize + 2;
|
|
|
|
log2_tag_bytes = log2_dcz_bytes - (LOG2_TAG_GRANULE + 1);
|
|
|
|
dcz_bytes = (intptr_t)1 << log2_dcz_bytes;
|
|
|
|
tag_bytes = (intptr_t)1 << log2_tag_bytes;
|
|
|
|
align_ptr = ptr & -dcz_bytes;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Trap if accessing an invalid page. DC_ZVA requires that we supply
|
|
|
|
* the original pointer for an invalid page. But watchpoints require
|
|
|
|
* that we probe the actual space. So do both.
|
|
|
|
*/
|
|
|
|
mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
|
|
|
|
(void) probe_write(env, ptr, 1, mmu_idx, ra);
|
|
|
|
mem = allocation_tag_mem(env, mmu_idx, align_ptr, MMU_DATA_STORE,
|
|
|
|
dcz_bytes, MMU_DATA_LOAD, tag_bytes, ra);
|
|
|
|
if (!mem) {
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Unlike the reasoning for checkN, DC_ZVA is always aligned, and thus
|
|
|
|
* it is quite easy to perform all of the comparisons at once without
|
|
|
|
* any extra masking.
|
|
|
|
*
|
|
|
|
* The most common zva block size is 64; some of the thunderx cpus use
|
|
|
|
* a block size of 128. For user-only, aarch64_max_initfn will set the
|
|
|
|
* block size to 512. Fill out the other cases for future-proofing.
|
|
|
|
*
|
|
|
|
* In order to be able to find the first miscompare later, we want the
|
|
|
|
* tag bytes to be in little-endian order.
|
|
|
|
*/
|
|
|
|
switch (log2_tag_bytes) {
|
|
|
|
case 0: /* zva_blocksize 32 */
|
|
|
|
mem_tag = *(uint8_t *)mem;
|
|
|
|
ptr_tag *= 0x11u;
|
|
|
|
break;
|
|
|
|
case 1: /* zva_blocksize 64 */
|
|
|
|
mem_tag = cpu_to_le16(*(uint16_t *)mem);
|
|
|
|
ptr_tag *= 0x1111u;
|
|
|
|
break;
|
|
|
|
case 2: /* zva_blocksize 128 */
|
|
|
|
mem_tag = cpu_to_le32(*(uint32_t *)mem);
|
|
|
|
ptr_tag *= 0x11111111u;
|
|
|
|
break;
|
|
|
|
case 3: /* zva_blocksize 256 */
|
|
|
|
mem_tag = cpu_to_le64(*(uint64_t *)mem);
|
|
|
|
ptr_tag *= 0x1111111111111111ull;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default: /* zva_blocksize 512, 1024, 2048 */
|
|
|
|
ptr_tag *= 0x1111111111111111ull;
|
|
|
|
i = 0;
|
|
|
|
do {
|
|
|
|
mem_tag = cpu_to_le64(*(uint64_t *)(mem + i));
|
|
|
|
if (unlikely(mem_tag != ptr_tag)) {
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
i += 8;
|
|
|
|
align_ptr += 16 * TAG_GRANULE;
|
|
|
|
} while (i < tag_bytes);
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (likely(mem_tag == ptr_tag)) {
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
fail:
|
|
|
|
/* Locate the first nibble that differs. */
|
|
|
|
i = ctz64(mem_tag ^ ptr_tag) >> 4;
|
2020-08-28 12:02:44 +03:00
|
|
|
mte_check_fail(env, desc, align_ptr + i * TAG_GRANULE, ra);
|
2020-06-26 06:31:25 +03:00
|
|
|
|
|
|
|
done:
|
|
|
|
return useronly_clean_ptr(ptr);
|
|
|
|
}
|