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target/arm: Implement the ADDG, SUBG instructions

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-06-25 20:31:09 -07:00 committed by Peter Maydell
parent 21a8b343ea
commit efbc78ad97
4 changed files with 71 additions and 0 deletions
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1
target/arm/helper-a64.h
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@ -105,3 +105,4 @@ DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64)
DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64)
DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32)

9
target/arm/internals.h
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@ -1261,6 +1261,15 @@ void arm_log_exception(int idx);
*/
#define GMID_EL1_BS 6
/* We associate one allocation tag per 16 bytes, the minimum. */
#define LOG2_TAG_GRANULE 4
#define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
static inline int allocation_tag_from_addr(uint64_t ptr)
{
return extract64(ptr, 56, 4);
}
static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag)
{
return deposit64(ptr, 56, 4, rtag);

10
target/arm/mte_helper.c
View File

@ -70,3 +70,13 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm)
return address_with_allocation_tag(rn, rtag);
}
uint64_t HELPER(addsubg)(CPUARMState *env, uint64_t ptr,
int32_t offset, uint32_t tag_offset)
{
int start_tag = allocation_tag_from_addr(ptr);
uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16);
int rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude);
return address_with_allocation_tag(ptr + offset, rtag);
}

51
target/arm/translate-a64.c
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@ -3808,6 +3808,54 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_result);
}
/*
* Add/subtract (immediate, with tags)
*
* 31 30 29 28 23 22 21 16 14 10 9 5 4 0
* +--+--+--+-------------+--+---------+--+-------+-----+-----+
* |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
* +--+--+--+-------------+--+---------+--+-------+-----+-----+
*
* op: 0 -> add, 1 -> sub
*/
static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int uimm4 = extract32(insn, 10, 4);
int uimm6 = extract32(insn, 16, 6);
bool sub_op = extract32(insn, 30, 1);
TCGv_i64 tcg_rn, tcg_rd;
int imm;
/* Test all of sf=1, S=0, o2=0, o3=0. */
if ((insn & 0xa040c000u) != 0x80000000u ||
!dc_isar_feature(aa64_mte_insn_reg, s)) {
unallocated_encoding(s);
return;
}
imm = uimm6 << LOG2_TAG_GRANULE;
if (sub_op) {
imm = -imm;
}
tcg_rn = cpu_reg_sp(s, rn);
tcg_rd = cpu_reg_sp(s, rd);
if (s->ata) {
TCGv_i32 offset = tcg_const_i32(imm);
TCGv_i32 tag_offset = tcg_const_i32(uimm4);
gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset);
tcg_temp_free_i32(tag_offset);
tcg_temp_free_i32(offset);
} else {
tcg_gen_addi_i64(tcg_rd, tcg_rn, imm);
gen_address_with_allocation_tag0(tcg_rd, tcg_rd);
}
}
/* The input should be a value in the bottom e bits (with higher
* bits zero); returns that value replicated into every element
* of size e in a 64 bit integer.
@ -4170,6 +4218,9 @@ static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
case 0x22: /* Add/subtract (immediate) */
disas_add_sub_imm(s, insn);
break;
case 0x23: /* Add/subtract (immediate, with tags) */
disas_add_sub_imm_with_tags(s, insn);
break;
case 0x24: /* Logical (immediate) */
disas_logic_imm(s, insn);
break;