2003-11-11 16:48:59 +03:00
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/*
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2008-01-14 06:05:55 +03:00
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* QEMU IDE disk and CD/DVD-ROM Emulator
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2007-09-17 01:08:06 +04:00
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*
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2003-11-11 16:48:59 +03:00
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* Copyright (c) 2003 Fabrice Bellard
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2007-04-30 04:51:09 +04:00
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* Copyright (c) 2006 Openedhand Ltd.
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2007-09-17 01:08:06 +04:00
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*
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2003-11-11 16:48:59 +03:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2009-08-20 17:22:26 +04:00
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#include <hw/hw.h>
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2013-02-05 20:06:20 +04:00
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#include <hw/i386/pc.h>
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2012-12-12 16:24:50 +04:00
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#include <hw/pci/pci.h>
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2013-02-05 20:06:20 +04:00
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#include <hw/isa/isa.h>
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2012-12-17 21:20:00 +04:00
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#include "qemu/error-report.h"
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#include "qemu/timer.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/sysemu.h"
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#include "sysemu/dma.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/block/block.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/blockdev.h"
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2009-08-20 17:22:26 +04:00
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#include <hw/ide/internal.h>
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2009-08-07 23:33:04 +04:00
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2011-03-01 16:30:23 +03:00
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/* These values were based on a Seagate ST3500418AS but have been modified
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to make more sense in QEMU */
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static const int smart_attributes[][12] = {
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/* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
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/* raw read error rate*/
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{ 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
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/* spin up */
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{ 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
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/* start stop count */
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{ 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
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/* remapped sectors */
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{ 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
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/* power on hours */
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{ 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
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/* power cycle count */
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{ 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
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/* airflow-temperature-celsius */
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{ 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
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2009-08-07 23:33:04 +04:00
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};
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2009-11-27 15:25:38 +03:00
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static int ide_handle_rw_error(IDEState *s, int error, int op);
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2011-07-04 16:07:50 +04:00
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static void ide_dummy_transfer_stop(IDEState *s);
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2004-06-25 18:54:19 +04:00
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2003-11-11 16:48:59 +03:00
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static void padstr(char *str, const char *src, int len)
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{
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int i, v;
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for(i = 0; i < len; i++) {
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if (*src)
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v = *src++;
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else
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v = ' ';
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2007-12-17 06:15:52 +03:00
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str[i^1] = v;
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2003-11-11 16:48:59 +03:00
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}
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}
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2004-04-01 03:37:16 +04:00
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static void put_le16(uint16_t *p, unsigned int v)
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{
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2004-04-26 02:09:16 +04:00
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*p = cpu_to_le16(v);
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2004-04-01 03:37:16 +04:00
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}
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2003-11-11 16:48:59 +03:00
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static void ide_identify(IDEState *s)
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{
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uint16_t *p;
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unsigned int oldsize;
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2011-05-19 12:58:19 +04:00
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IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
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2003-11-11 16:48:59 +03:00
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2006-02-02 01:20:12 +03:00
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if (s->identify_set) {
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memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
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return;
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}
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2003-11-11 16:48:59 +03:00
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memset(s->io_buffer, 0, 512);
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p = (uint16_t *)s->io_buffer;
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2004-04-01 03:37:16 +04:00
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put_le16(p + 0, 0x0040);
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2007-09-17 01:08:06 +04:00
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put_le16(p + 1, s->cylinders);
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2004-04-01 03:37:16 +04:00
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put_le16(p + 3, s->heads);
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put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
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put_le16(p + 5, 512); /* XXX: retired, remove ? */
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2007-09-17 01:08:06 +04:00
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put_le16(p + 6, s->sectors);
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2009-01-07 20:32:33 +03:00
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padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
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2004-04-01 03:37:16 +04:00
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put_le16(p + 20, 3); /* XXX: retired, remove ? */
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put_le16(p + 21, 512); /* cache size in sectors */
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put_le16(p + 22, 4); /* ecc bytes */
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2010-01-14 16:44:12 +03:00
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padstr((char *)(p + 23), s->version, 8); /* firmware version */
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2012-03-13 00:05:09 +04:00
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padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
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2007-09-17 12:09:54 +04:00
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#if MAX_MULT_SECTORS > 1
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2004-04-01 03:37:16 +04:00
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put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
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2003-11-11 16:48:59 +03:00
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#endif
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2004-04-01 03:37:16 +04:00
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put_le16(p + 48, 1); /* dword I/O */
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2006-02-02 01:20:12 +03:00
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put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
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2004-04-01 03:37:16 +04:00
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put_le16(p + 51, 0x200); /* PIO transfer cycle */
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put_le16(p + 52, 0x200); /* DMA transfer cycle */
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2006-02-02 01:20:12 +03:00
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put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
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2004-04-01 03:37:16 +04:00
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put_le16(p + 54, s->cylinders);
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put_le16(p + 55, s->heads);
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put_le16(p + 56, s->sectors);
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2003-11-11 16:48:59 +03:00
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oldsize = s->cylinders * s->heads * s->sectors;
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2004-04-01 03:37:16 +04:00
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put_le16(p + 57, oldsize);
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put_le16(p + 58, oldsize >> 16);
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2003-11-11 16:48:59 +03:00
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if (s->mult_sectors)
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2004-04-01 03:37:16 +04:00
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put_le16(p + 59, 0x100 | s->mult_sectors);
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put_le16(p + 60, s->nb_sectors);
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put_le16(p + 61, s->nb_sectors >> 16);
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2008-07-18 20:49:42 +04:00
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put_le16(p + 62, 0x07); /* single word dma0-2 supported */
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2006-02-02 01:20:12 +03:00
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put_le16(p + 63, 0x07); /* mdma0-2 supported */
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2010-09-03 16:57:46 +04:00
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put_le16(p + 64, 0x03); /* pio3-4 supported */
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2006-02-02 01:20:12 +03:00
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put_le16(p + 65, 120);
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put_le16(p + 66, 120);
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put_le16(p + 67, 120);
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put_le16(p + 68, 120);
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2011-05-19 12:58:19 +04:00
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if (dev && dev->conf.discard_granularity) {
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put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
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}
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2010-12-14 03:34:37 +03:00
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if (s->ncq_queues) {
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put_le16(p + 75, s->ncq_queues - 1);
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/* NCQ supported */
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put_le16(p + 76, (1 << 8));
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}
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2006-02-02 01:20:12 +03:00
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put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
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put_le16(p + 81, 0x16); /* conforms to ata5 */
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2010-10-04 17:29:41 +04:00
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/* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
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put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
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2006-04-26 01:24:22 +04:00
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/* 13=flush_cache_ext,12=flush_cache,10=lba48 */
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put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
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2012-03-13 16:31:47 +04:00
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/* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
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if (s->wwn) {
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put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
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} else {
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put_le16(p + 84, (1 << 14) | 0);
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}
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2009-09-04 21:01:15 +04:00
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/* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
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if (bdrv_enable_write_cache(s->bs))
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put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
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else
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put_le16(p + 85, (1 << 14) | 1);
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2006-04-26 01:24:22 +04:00
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/* 13=flush_cache_ext,12=flush_cache,10=lba48 */
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2012-03-13 17:44:22 +04:00
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put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
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2012-03-13 16:31:47 +04:00
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/* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
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if (s->wwn) {
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put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
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} else {
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put_le16(p + 87, (1 << 14) | 0);
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}
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2006-02-02 01:20:12 +03:00
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put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
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put_le16(p + 93, 1 | (1 << 14) | 0x2000);
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2006-04-26 01:24:22 +04:00
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put_le16(p + 100, s->nb_sectors);
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put_le16(p + 101, s->nb_sectors >> 16);
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put_le16(p + 102, s->nb_sectors >> 32);
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put_le16(p + 103, s->nb_sectors >> 48);
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2011-05-19 12:58:19 +04:00
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2010-05-28 17:38:46 +04:00
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if (dev && dev->conf.physical_block_size)
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put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
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2012-03-13 16:31:47 +04:00
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if (s->wwn) {
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/* LE 16-bit words 111-108 contain 64-bit World Wide Name */
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put_le16(p + 108, s->wwn >> 48);
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put_le16(p + 109, s->wwn >> 32);
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put_le16(p + 110, s->wwn >> 16);
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put_le16(p + 111, s->wwn);
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}
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2011-05-19 12:58:19 +04:00
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if (dev && dev->conf.discard_granularity) {
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put_le16(p + 169, 1); /* TRIM support */
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}
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2006-02-02 01:20:12 +03:00
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memcpy(s->identify_data, p, sizeof(s->identify_data));
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s->identify_set = 1;
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2003-11-11 16:48:59 +03:00
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}
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static void ide_atapi_identify(IDEState *s)
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{
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uint16_t *p;
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2006-02-02 01:20:12 +03:00
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if (s->identify_set) {
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memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
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return;
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}
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2003-11-11 16:48:59 +03:00
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memset(s->io_buffer, 0, 512);
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p = (uint16_t *)s->io_buffer;
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/* Removable CDROM, 50us response, 12 byte packets */
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2004-04-01 03:37:16 +04:00
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put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
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2009-01-07 20:32:33 +03:00
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padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
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2004-04-01 03:37:16 +04:00
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put_le16(p + 20, 3); /* buffer type */
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put_le16(p + 21, 512); /* cache size in sectors */
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put_le16(p + 22, 4); /* ecc bytes */
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2010-01-14 16:44:12 +03:00
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padstr((char *)(p + 23), s->version, 8); /* firmware version */
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2012-03-13 00:05:09 +04:00
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padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
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2004-04-01 03:37:16 +04:00
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put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
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2006-08-08 01:36:34 +04:00
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#ifdef USE_DMA_CDROM
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put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
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put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
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2008-07-18 20:49:42 +04:00
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put_le16(p + 62, 7); /* single word dma0-2 supported */
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2006-08-08 01:36:34 +04:00
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put_le16(p + 63, 7); /* mdma0-2 supported */
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#else
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2004-04-01 03:37:16 +04:00
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put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
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put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
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put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
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2006-08-08 01:36:34 +04:00
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#endif
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2010-09-03 16:57:46 +04:00
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put_le16(p + 64, 3); /* pio3-4 supported */
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2004-04-01 03:37:16 +04:00
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put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
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put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
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put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
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put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
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2006-02-02 01:20:12 +03:00
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2004-04-01 03:37:16 +04:00
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put_le16(p + 71, 30); /* in ns */
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put_le16(p + 72, 30); /* in ns */
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2003-11-11 16:48:59 +03:00
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2010-12-14 18:23:38 +03:00
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if (s->ncq_queues) {
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put_le16(p + 75, s->ncq_queues - 1);
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/* NCQ supported */
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put_le16(p + 76, (1 << 8));
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}
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2004-04-01 03:37:16 +04:00
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put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
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2006-08-08 01:36:34 +04:00
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#ifdef USE_DMA_CDROM
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put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
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#endif
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2006-02-02 01:20:12 +03:00
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memcpy(s->identify_data, p, sizeof(s->identify_data));
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s->identify_set = 1;
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2003-11-11 16:48:59 +03:00
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}
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2007-04-30 04:51:09 +04:00
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static void ide_cfata_identify(IDEState *s)
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{
|
|
|
|
uint16_t *p;
|
|
|
|
uint32_t cur_sec;
|
|
|
|
|
|
|
|
p = (uint16_t *) s->identify_data;
|
|
|
|
if (s->identify_set)
|
|
|
|
goto fill_buffer;
|
|
|
|
|
|
|
|
memset(p, 0, sizeof(s->identify_data));
|
|
|
|
|
|
|
|
cur_sec = s->cylinders * s->heads * s->sectors;
|
|
|
|
|
|
|
|
put_le16(p + 0, 0x848a); /* CF Storage Card signature */
|
|
|
|
put_le16(p + 1, s->cylinders); /* Default cylinders */
|
|
|
|
put_le16(p + 3, s->heads); /* Default heads */
|
|
|
|
put_le16(p + 6, s->sectors); /* Default sectors per track */
|
|
|
|
put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
|
|
|
|
put_le16(p + 8, s->nb_sectors); /* Sectors per card */
|
2009-01-07 20:32:33 +03:00
|
|
|
padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
|
2007-04-30 04:51:09 +04:00
|
|
|
put_le16(p + 22, 0x0004); /* ECC bytes */
|
2010-01-14 16:44:12 +03:00
|
|
|
padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
|
2012-03-13 00:05:09 +04:00
|
|
|
padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
|
2007-04-30 04:51:09 +04:00
|
|
|
#if MAX_MULT_SECTORS > 1
|
|
|
|
put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
|
|
|
|
#else
|
|
|
|
put_le16(p + 47, 0x0000);
|
|
|
|
#endif
|
|
|
|
put_le16(p + 49, 0x0f00); /* Capabilities */
|
|
|
|
put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
|
|
|
|
put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
|
|
|
|
put_le16(p + 53, 0x0003); /* Translation params valid */
|
|
|
|
put_le16(p + 54, s->cylinders); /* Current cylinders */
|
|
|
|
put_le16(p + 55, s->heads); /* Current heads */
|
|
|
|
put_le16(p + 56, s->sectors); /* Current sectors */
|
|
|
|
put_le16(p + 57, cur_sec); /* Current capacity */
|
|
|
|
put_le16(p + 58, cur_sec >> 16); /* Current capacity */
|
|
|
|
if (s->mult_sectors) /* Multiple sector setting */
|
|
|
|
put_le16(p + 59, 0x100 | s->mult_sectors);
|
|
|
|
put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
|
|
|
|
put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
|
|
|
|
put_le16(p + 63, 0x0203); /* Multiword DMA capability */
|
|
|
|
put_le16(p + 64, 0x0001); /* Flow Control PIO support */
|
|
|
|
put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
|
|
|
|
put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
|
|
|
|
put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
|
|
|
|
put_le16(p + 82, 0x400c); /* Command Set supported */
|
|
|
|
put_le16(p + 83, 0x7068); /* Command Set supported */
|
|
|
|
put_le16(p + 84, 0x4000); /* Features supported */
|
|
|
|
put_le16(p + 85, 0x000c); /* Command Set enabled */
|
|
|
|
put_le16(p + 86, 0x7044); /* Command Set enabled */
|
|
|
|
put_le16(p + 87, 0x4000); /* Features enabled */
|
|
|
|
put_le16(p + 91, 0x4060); /* Current APM level */
|
|
|
|
put_le16(p + 129, 0x0002); /* Current features option */
|
|
|
|
put_le16(p + 130, 0x0005); /* Reassigned sectors */
|
|
|
|
put_le16(p + 131, 0x0001); /* Initial power mode */
|
|
|
|
put_le16(p + 132, 0x0000); /* User signature */
|
|
|
|
put_le16(p + 160, 0x8100); /* Power requirement */
|
|
|
|
put_le16(p + 161, 0x8001); /* CF command set */
|
|
|
|
|
|
|
|
s->identify_set = 1;
|
|
|
|
|
|
|
|
fill_buffer:
|
|
|
|
memcpy(s->io_buffer, p, sizeof(s->identify_data));
|
|
|
|
}
|
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
static void ide_set_signature(IDEState *s)
|
|
|
|
{
|
|
|
|
s->select &= 0xf0; /* clear head */
|
|
|
|
/* put signature */
|
|
|
|
s->nsector = 1;
|
|
|
|
s->sector = 1;
|
2010-05-28 15:32:45 +04:00
|
|
|
if (s->drive_kind == IDE_CD) {
|
2003-11-11 16:48:59 +03:00
|
|
|
s->lcyl = 0x14;
|
|
|
|
s->hcyl = 0xeb;
|
|
|
|
} else if (s->bs) {
|
|
|
|
s->lcyl = 0;
|
|
|
|
s->hcyl = 0;
|
|
|
|
} else {
|
|
|
|
s->lcyl = 0xff;
|
|
|
|
s->hcyl = 0xff;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-05-19 12:58:19 +04:00
|
|
|
typedef struct TrimAIOCB {
|
|
|
|
BlockDriverAIOCB common;
|
|
|
|
QEMUBH *bh;
|
|
|
|
int ret;
|
2013-01-14 19:26:57 +04:00
|
|
|
QEMUIOVector *qiov;
|
|
|
|
BlockDriverAIOCB *aiocb;
|
|
|
|
int i, j;
|
2011-05-19 12:58:19 +04:00
|
|
|
} TrimAIOCB;
|
|
|
|
|
|
|
|
static void trim_aio_cancel(BlockDriverAIOCB *acb)
|
|
|
|
{
|
|
|
|
TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
|
|
|
|
|
2013-01-14 19:26:57 +04:00
|
|
|
/* Exit the loop in case bdrv_aio_cancel calls ide_issue_trim_cb again. */
|
|
|
|
iocb->j = iocb->qiov->niov - 1;
|
|
|
|
iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
|
|
|
|
|
|
|
|
/* Tell ide_issue_trim_cb not to trigger the completion, too. */
|
2011-05-19 12:58:19 +04:00
|
|
|
qemu_bh_delete(iocb->bh);
|
|
|
|
iocb->bh = NULL;
|
2013-01-14 19:26:57 +04:00
|
|
|
|
|
|
|
if (iocb->aiocb) {
|
|
|
|
bdrv_aio_cancel(iocb->aiocb);
|
|
|
|
}
|
2011-05-19 12:58:19 +04:00
|
|
|
qemu_aio_release(iocb);
|
|
|
|
}
|
|
|
|
|
2012-10-31 19:34:37 +04:00
|
|
|
static const AIOCBInfo trim_aiocb_info = {
|
2011-05-19 12:58:19 +04:00
|
|
|
.aiocb_size = sizeof(TrimAIOCB),
|
|
|
|
.cancel = trim_aio_cancel,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void ide_trim_bh_cb(void *opaque)
|
|
|
|
{
|
|
|
|
TrimAIOCB *iocb = opaque;
|
|
|
|
|
|
|
|
iocb->common.cb(iocb->common.opaque, iocb->ret);
|
|
|
|
|
|
|
|
qemu_bh_delete(iocb->bh);
|
|
|
|
iocb->bh = NULL;
|
|
|
|
qemu_aio_release(iocb);
|
|
|
|
}
|
|
|
|
|
2013-01-14 19:26:57 +04:00
|
|
|
static void ide_issue_trim_cb(void *opaque, int ret)
|
|
|
|
{
|
|
|
|
TrimAIOCB *iocb = opaque;
|
|
|
|
if (ret >= 0) {
|
|
|
|
while (iocb->j < iocb->qiov->niov) {
|
|
|
|
int j = iocb->j;
|
|
|
|
while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
|
|
|
|
int i = iocb->i;
|
|
|
|
uint64_t *buffer = iocb->qiov->iov[j].iov_base;
|
|
|
|
|
|
|
|
/* 6-byte LBA + 2-byte range per entry */
|
|
|
|
uint64_t entry = le64_to_cpu(buffer[i]);
|
|
|
|
uint64_t sector = entry & 0x0000ffffffffffffULL;
|
|
|
|
uint16_t count = entry >> 48;
|
|
|
|
|
|
|
|
if (count == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Got an entry! Submit and exit. */
|
|
|
|
iocb->aiocb = bdrv_aio_discard(iocb->common.bs, sector, count,
|
|
|
|
ide_issue_trim_cb, opaque);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
iocb->j++;
|
|
|
|
iocb->i = -1;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
iocb->ret = ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
iocb->aiocb = NULL;
|
|
|
|
if (iocb->bh) {
|
|
|
|
qemu_bh_schedule(iocb->bh);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-05-19 12:58:19 +04:00
|
|
|
BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
|
|
|
|
int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
|
|
|
|
BlockDriverCompletionFunc *cb, void *opaque)
|
|
|
|
{
|
|
|
|
TrimAIOCB *iocb;
|
|
|
|
|
2012-10-31 19:34:37 +04:00
|
|
|
iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque);
|
2011-05-19 12:58:19 +04:00
|
|
|
iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
|
|
|
|
iocb->ret = 0;
|
2013-01-14 19:26:57 +04:00
|
|
|
iocb->qiov = qiov;
|
|
|
|
iocb->i = -1;
|
|
|
|
iocb->j = 0;
|
|
|
|
ide_issue_trim_cb(iocb, 0);
|
2011-05-19 12:58:19 +04:00
|
|
|
return &iocb->common;
|
|
|
|
}
|
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
static inline void ide_abort_command(IDEState *s)
|
|
|
|
{
|
|
|
|
s->status = READY_STAT | ERR_STAT;
|
|
|
|
s->error = ABRT_ERR;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* prepare data transfer and tell what to do after */
|
2011-04-18 18:45:49 +04:00
|
|
|
void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
|
|
|
|
EndTransferFunc *end_transfer_func)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
|
|
|
s->end_transfer_func = end_transfer_func;
|
|
|
|
s->data_ptr = buf;
|
|
|
|
s->data_end = buf + size;
|
2010-12-15 02:23:00 +03:00
|
|
|
if (!(s->status & ERR_STAT)) {
|
2007-08-20 01:46:53 +04:00
|
|
|
s->status |= DRQ_STAT;
|
2010-12-15 02:23:00 +03:00
|
|
|
}
|
|
|
|
s->bus->dma->ops->start_transfer(s->bus->dma);
|
2003-11-11 16:48:59 +03:00
|
|
|
}
|
|
|
|
|
2011-04-18 18:45:49 +04:00
|
|
|
void ide_transfer_stop(IDEState *s)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
|
|
|
s->end_transfer_func = ide_transfer_stop;
|
|
|
|
s->data_ptr = s->io_buffer;
|
|
|
|
s->data_end = s->io_buffer;
|
|
|
|
s->status &= ~DRQ_STAT;
|
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
int64_t ide_get_sector(IDEState *s)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
|
|
|
int64_t sector_num;
|
|
|
|
if (s->select & 0x40) {
|
|
|
|
/* lba */
|
2006-04-26 01:24:22 +04:00
|
|
|
if (!s->lba48) {
|
|
|
|
sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
|
|
|
|
(s->lcyl << 8) | s->sector;
|
|
|
|
} else {
|
|
|
|
sector_num = ((int64_t)s->hob_hcyl << 40) |
|
|
|
|
((int64_t) s->hob_lcyl << 32) |
|
|
|
|
((int64_t) s->hob_sector << 24) |
|
|
|
|
((int64_t) s->hcyl << 16) |
|
|
|
|
((int64_t) s->lcyl << 8) | s->sector;
|
|
|
|
}
|
2003-11-11 16:48:59 +03:00
|
|
|
} else {
|
|
|
|
sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
|
2006-04-26 01:24:22 +04:00
|
|
|
(s->select & 0x0f) * s->sectors + (s->sector - 1);
|
2003-11-11 16:48:59 +03:00
|
|
|
}
|
|
|
|
return sector_num;
|
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
void ide_set_sector(IDEState *s, int64_t sector_num)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
|
|
|
unsigned int cyl, r;
|
|
|
|
if (s->select & 0x40) {
|
2006-04-26 01:24:22 +04:00
|
|
|
if (!s->lba48) {
|
|
|
|
s->select = (s->select & 0xf0) | (sector_num >> 24);
|
|
|
|
s->hcyl = (sector_num >> 16);
|
|
|
|
s->lcyl = (sector_num >> 8);
|
|
|
|
s->sector = (sector_num);
|
|
|
|
} else {
|
|
|
|
s->sector = sector_num;
|
|
|
|
s->lcyl = sector_num >> 8;
|
|
|
|
s->hcyl = sector_num >> 16;
|
|
|
|
s->hob_sector = sector_num >> 24;
|
|
|
|
s->hob_lcyl = sector_num >> 32;
|
|
|
|
s->hob_hcyl = sector_num >> 40;
|
|
|
|
}
|
2003-11-11 16:48:59 +03:00
|
|
|
} else {
|
|
|
|
cyl = sector_num / (s->heads * s->sectors);
|
|
|
|
r = sector_num % (s->heads * s->sectors);
|
|
|
|
s->hcyl = cyl >> 8;
|
|
|
|
s->lcyl = cyl;
|
2004-04-25 21:58:25 +04:00
|
|
|
s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
|
2003-11-11 16:48:59 +03:00
|
|
|
s->sector = (r % s->sectors) + 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-10-01 05:13:37 +04:00
|
|
|
static void ide_rw_error(IDEState *s) {
|
|
|
|
ide_abort_command(s);
|
2009-08-28 18:37:42 +04:00
|
|
|
ide_set_irq(s->bus);
|
2008-10-01 05:13:37 +04:00
|
|
|
}
|
|
|
|
|
2012-03-29 13:31:30 +04:00
|
|
|
static void ide_sector_read_cb(void *opaque, int ret)
|
|
|
|
{
|
|
|
|
IDEState *s = opaque;
|
|
|
|
int n;
|
|
|
|
|
|
|
|
s->pio_aiocb = NULL;
|
|
|
|
s->status &= ~BUSY_STAT;
|
|
|
|
|
|
|
|
bdrv_acct_done(s->bs, &s->acct);
|
|
|
|
if (ret != 0) {
|
|
|
|
if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY |
|
|
|
|
BM_STATUS_RETRY_READ)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
n = s->nsector;
|
|
|
|
if (n > s->req_nb_sectors) {
|
|
|
|
n = s->req_nb_sectors;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Allow the guest to read the io_buffer */
|
|
|
|
ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
|
|
|
|
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
|
|
|
|
ide_set_sector(s, ide_get_sector(s) + n);
|
|
|
|
s->nsector -= n;
|
|
|
|
}
|
|
|
|
|
2010-12-15 02:23:00 +03:00
|
|
|
void ide_sector_read(IDEState *s)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
|
|
|
int64_t sector_num;
|
2012-03-29 13:31:30 +04:00
|
|
|
int n;
|
2003-11-11 16:48:59 +03:00
|
|
|
|
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
2004-01-23 02:52:27 +03:00
|
|
|
s->error = 0; /* not needed by IDE spec, but needed by Windows */
|
2003-11-11 16:48:59 +03:00
|
|
|
sector_num = ide_get_sector(s);
|
|
|
|
n = s->nsector;
|
2012-03-29 13:31:30 +04:00
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
if (n == 0) {
|
|
|
|
ide_transfer_stop(s);
|
2012-03-29 13:31:30 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->status |= BUSY_STAT;
|
|
|
|
|
|
|
|
if (n > s->req_nb_sectors) {
|
|
|
|
n = s->req_nb_sectors;
|
|
|
|
}
|
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
#if defined(DEBUG_IDE)
|
2012-03-29 13:31:30 +04:00
|
|
|
printf("sector=%" PRId64 "\n", sector_num);
|
2003-11-11 16:48:59 +03:00
|
|
|
#endif
|
2011-08-25 10:26:01 +04:00
|
|
|
|
2012-03-29 13:31:30 +04:00
|
|
|
s->iov.iov_base = s->io_buffer;
|
|
|
|
s->iov.iov_len = n * BDRV_SECTOR_SIZE;
|
|
|
|
qemu_iovec_init_external(&s->qiov, &s->iov, 1);
|
|
|
|
|
|
|
|
bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
|
|
|
|
s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n,
|
|
|
|
ide_sector_read_cb, s);
|
2003-11-11 16:48:59 +03:00
|
|
|
}
|
|
|
|
|
2011-12-15 18:11:16 +04:00
|
|
|
static void dma_buf_commit(IDEState *s)
|
2009-01-22 19:59:28 +03:00
|
|
|
{
|
2009-02-06 00:24:02 +03:00
|
|
|
qemu_sglist_destroy(&s->sg);
|
2009-01-22 19:59:28 +03:00
|
|
|
}
|
|
|
|
|
2013-07-15 13:25:55 +04:00
|
|
|
static void ide_async_cmd_done(IDEState *s)
|
|
|
|
{
|
|
|
|
if (s->bus->dma->ops->async_cmd_done) {
|
|
|
|
s->bus->dma->ops->async_cmd_done(s->bus->dma);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-04-18 18:45:49 +04:00
|
|
|
void ide_set_inactive(IDEState *s)
|
2010-11-26 18:31:37 +03:00
|
|
|
{
|
2010-12-15 02:23:00 +03:00
|
|
|
s->bus->dma->aiocb = NULL;
|
|
|
|
s->bus->dma->ops->set_inactive(s->bus->dma);
|
2013-07-15 13:25:55 +04:00
|
|
|
ide_async_cmd_done(s);
|
2010-11-26 18:31:37 +03:00
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
void ide_dma_error(IDEState *s)
|
2008-10-01 05:13:37 +04:00
|
|
|
{
|
|
|
|
ide_transfer_stop(s);
|
|
|
|
s->error = ABRT_ERR;
|
|
|
|
s->status = READY_STAT | ERR_STAT;
|
2010-12-15 02:23:00 +03:00
|
|
|
ide_set_inactive(s);
|
2009-08-28 18:37:42 +04:00
|
|
|
ide_set_irq(s->bus);
|
2008-10-01 05:13:37 +04:00
|
|
|
}
|
|
|
|
|
2009-11-27 15:25:38 +03:00
|
|
|
static int ide_handle_rw_error(IDEState *s, int error, int op)
|
2009-01-21 21:59:04 +03:00
|
|
|
{
|
2012-09-28 19:22:56 +04:00
|
|
|
bool is_read = (op & BM_STATUS_RETRY_READ) != 0;
|
2012-09-28 19:22:57 +04:00
|
|
|
BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error);
|
2009-01-21 21:59:04 +03:00
|
|
|
|
2012-09-28 19:22:57 +04:00
|
|
|
if (action == BDRV_ACTION_STOP) {
|
2010-12-15 02:23:00 +03:00
|
|
|
s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
|
2011-05-26 17:00:34 +04:00
|
|
|
s->bus->error_status = op;
|
2012-09-28 19:22:57 +04:00
|
|
|
} else if (action == BDRV_ACTION_REPORT) {
|
2009-11-27 15:25:38 +03:00
|
|
|
if (op & BM_STATUS_DMA_RETRY) {
|
2011-12-15 18:11:16 +04:00
|
|
|
dma_buf_commit(s);
|
2009-01-21 21:59:04 +03:00
|
|
|
ide_dma_error(s);
|
2009-01-22 19:59:28 +03:00
|
|
|
} else {
|
2009-01-21 21:59:04 +03:00
|
|
|
ide_rw_error(s);
|
2009-01-22 19:59:28 +03:00
|
|
|
}
|
2009-01-21 21:59:04 +03:00
|
|
|
}
|
2012-09-28 19:22:57 +04:00
|
|
|
bdrv_error_action(s->bs, action, is_read, error);
|
|
|
|
return action != BDRV_ACTION_IGNORE;
|
2009-01-21 21:59:04 +03:00
|
|
|
}
|
|
|
|
|
2010-12-20 15:45:48 +03:00
|
|
|
void ide_dma_cb(void *opaque, int ret)
|
2004-06-25 18:54:19 +04:00
|
|
|
{
|
2010-12-15 02:23:00 +03:00
|
|
|
IDEState *s = opaque;
|
2006-08-08 01:36:34 +04:00
|
|
|
int n;
|
|
|
|
int64_t sector_num;
|
2012-11-20 20:27:43 +04:00
|
|
|
bool stay_active = false;
|
2006-08-08 01:36:34 +04:00
|
|
|
|
2008-10-01 05:13:37 +04:00
|
|
|
if (ret < 0) {
|
2010-12-20 15:45:48 +03:00
|
|
|
int op = BM_STATUS_DMA_RETRY;
|
|
|
|
|
2011-05-19 12:58:09 +04:00
|
|
|
if (s->dma_cmd == IDE_DMA_READ)
|
2010-12-20 15:45:48 +03:00
|
|
|
op |= BM_STATUS_RETRY_READ;
|
2011-05-19 12:58:19 +04:00
|
|
|
else if (s->dma_cmd == IDE_DMA_TRIM)
|
|
|
|
op |= BM_STATUS_RETRY_TRIM;
|
|
|
|
|
2010-12-20 15:45:48 +03:00
|
|
|
if (ide_handle_rw_error(s, -ret, op)) {
|
2009-11-27 15:25:38 +03:00
|
|
|
return;
|
|
|
|
}
|
2008-10-01 05:13:37 +04:00
|
|
|
}
|
|
|
|
|
2006-08-08 01:36:34 +04:00
|
|
|
n = s->io_buffer_size >> 9;
|
2012-11-20 20:27:43 +04:00
|
|
|
if (n > s->nsector) {
|
|
|
|
/* The PRDs were longer than needed for this request. Shorten them so
|
|
|
|
* we don't get a negative remainder. The Active bit must remain set
|
|
|
|
* after the request completes. */
|
|
|
|
n = s->nsector;
|
|
|
|
stay_active = true;
|
|
|
|
}
|
|
|
|
|
2006-08-08 01:36:34 +04:00
|
|
|
sector_num = ide_get_sector(s);
|
|
|
|
if (n > 0) {
|
2011-12-15 18:11:16 +04:00
|
|
|
dma_buf_commit(s);
|
2006-08-08 01:36:34 +04:00
|
|
|
sector_num += n;
|
|
|
|
ide_set_sector(s, sector_num);
|
|
|
|
s->nsector -= n;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* end of transfer ? */
|
|
|
|
if (s->nsector == 0) {
|
2004-06-25 18:54:19 +04:00
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
2009-08-28 18:37:42 +04:00
|
|
|
ide_set_irq(s->bus);
|
2010-12-20 15:45:48 +03:00
|
|
|
goto eot;
|
2004-06-25 18:54:19 +04:00
|
|
|
}
|
2006-08-08 01:36:34 +04:00
|
|
|
|
|
|
|
/* launch next transfer */
|
|
|
|
n = s->nsector;
|
2010-12-20 15:45:58 +03:00
|
|
|
s->io_buffer_index = 0;
|
2006-08-08 01:36:34 +04:00
|
|
|
s->io_buffer_size = n * 512;
|
2011-05-19 12:58:09 +04:00
|
|
|
if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
|
2011-05-19 18:42:24 +04:00
|
|
|
/* The PRDs were too short. Reset the Active bit, but don't raise an
|
|
|
|
* interrupt. */
|
2012-11-20 20:27:44 +04:00
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
2009-01-22 19:59:28 +03:00
|
|
|
goto eot;
|
2011-05-19 18:42:24 +04:00
|
|
|
}
|
2010-12-20 15:45:48 +03:00
|
|
|
|
2006-08-08 01:36:34 +04:00
|
|
|
#ifdef DEBUG_AIO
|
2011-05-19 12:58:09 +04:00
|
|
|
printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
|
|
|
|
sector_num, n, s->dma_cmd);
|
2006-08-08 01:36:34 +04:00
|
|
|
#endif
|
2010-12-20 15:45:48 +03:00
|
|
|
|
2011-05-19 12:58:09 +04:00
|
|
|
switch (s->dma_cmd) {
|
|
|
|
case IDE_DMA_READ:
|
2010-12-20 15:45:48 +03:00
|
|
|
s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
|
|
|
|
ide_dma_cb, s);
|
2011-05-19 12:58:09 +04:00
|
|
|
break;
|
|
|
|
case IDE_DMA_WRITE:
|
2010-12-20 15:45:48 +03:00
|
|
|
s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
|
|
|
|
ide_dma_cb, s);
|
2011-05-19 12:58:09 +04:00
|
|
|
break;
|
2011-05-19 12:58:19 +04:00
|
|
|
case IDE_DMA_TRIM:
|
|
|
|
s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
|
2012-03-27 06:42:23 +04:00
|
|
|
ide_issue_trim, ide_dma_cb, s,
|
|
|
|
DMA_DIRECTION_TO_DEVICE);
|
2011-05-19 12:58:19 +04:00
|
|
|
break;
|
2010-12-20 15:45:48 +03:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
|
|
|
|
eot:
|
2011-08-25 10:26:01 +04:00
|
|
|
if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
|
|
|
|
bdrv_acct_done(s->bs, &s->acct);
|
|
|
|
}
|
|
|
|
ide_set_inactive(s);
|
2012-11-20 20:27:43 +04:00
|
|
|
if (stay_active) {
|
|
|
|
s->bus->dma->ops->add_status(s->bus->dma, BM_STATUS_DMAING);
|
|
|
|
}
|
2004-06-25 18:54:19 +04:00
|
|
|
}
|
|
|
|
|
2011-05-19 12:58:09 +04:00
|
|
|
static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
|
2004-06-25 18:54:19 +04:00
|
|
|
{
|
2006-08-08 01:36:34 +04:00
|
|
|
s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
|
2004-06-25 18:54:19 +04:00
|
|
|
s->io_buffer_index = 0;
|
|
|
|
s->io_buffer_size = 0;
|
2011-05-19 12:58:09 +04:00
|
|
|
s->dma_cmd = dma_cmd;
|
2011-08-25 10:26:01 +04:00
|
|
|
|
|
|
|
switch (dma_cmd) {
|
|
|
|
case IDE_DMA_READ:
|
|
|
|
bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
|
|
|
|
BDRV_ACCT_READ);
|
|
|
|
break;
|
|
|
|
case IDE_DMA_WRITE:
|
|
|
|
bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
|
|
|
|
BDRV_ACCT_WRITE);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-12-20 15:45:48 +03:00
|
|
|
s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
|
2004-06-25 18:54:19 +04:00
|
|
|
}
|
|
|
|
|
2005-04-30 20:10:35 +04:00
|
|
|
static void ide_sector_write_timer_cb(void *opaque)
|
|
|
|
{
|
|
|
|
IDEState *s = opaque;
|
2009-08-28 18:37:42 +04:00
|
|
|
ide_set_irq(s->bus);
|
2005-04-30 20:10:35 +04:00
|
|
|
}
|
|
|
|
|
2012-03-29 13:31:31 +04:00
|
|
|
static void ide_sector_write_cb(void *opaque, int ret)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
2012-03-29 13:31:31 +04:00
|
|
|
IDEState *s = opaque;
|
|
|
|
int n;
|
2011-08-25 10:26:01 +04:00
|
|
|
|
|
|
|
bdrv_acct_done(s->bs, &s->acct);
|
2009-01-21 21:59:04 +03:00
|
|
|
|
2012-03-29 13:31:31 +04:00
|
|
|
s->pio_aiocb = NULL;
|
|
|
|
s->status &= ~BUSY_STAT;
|
|
|
|
|
2008-10-01 05:13:37 +04:00
|
|
|
if (ret != 0) {
|
2012-03-29 13:31:31 +04:00
|
|
|
if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) {
|
2009-01-21 21:59:04 +03:00
|
|
|
return;
|
2012-03-29 13:31:31 +04:00
|
|
|
}
|
2008-10-01 05:13:37 +04:00
|
|
|
}
|
|
|
|
|
2012-03-29 13:31:31 +04:00
|
|
|
n = s->nsector;
|
|
|
|
if (n > s->req_nb_sectors) {
|
|
|
|
n = s->req_nb_sectors;
|
|
|
|
}
|
2003-11-11 16:48:59 +03:00
|
|
|
s->nsector -= n;
|
|
|
|
if (s->nsector == 0) {
|
2007-02-19 03:59:34 +03:00
|
|
|
/* no more sectors to write */
|
2003-11-11 16:48:59 +03:00
|
|
|
ide_transfer_stop(s);
|
|
|
|
} else {
|
2012-03-29 13:31:31 +04:00
|
|
|
int n1 = s->nsector;
|
|
|
|
if (n1 > s->req_nb_sectors) {
|
2003-11-11 16:48:59 +03:00
|
|
|
n1 = s->req_nb_sectors;
|
2012-03-29 13:31:31 +04:00
|
|
|
}
|
|
|
|
ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
|
|
|
|
ide_sector_write);
|
2003-11-11 16:48:59 +03:00
|
|
|
}
|
2012-03-29 13:31:31 +04:00
|
|
|
ide_set_sector(s, ide_get_sector(s) + n);
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2007-11-08 19:38:17 +03:00
|
|
|
if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
|
|
|
|
/* It seems there is a bug in the Windows 2000 installer HDD
|
|
|
|
IDE driver which fills the disk with empty logs when the
|
|
|
|
IDE write IRQ comes too early. This hack tries to correct
|
|
|
|
that at the expense of slower write performances. Use this
|
|
|
|
option _only_ to install Windows 2000. You must disable it
|
|
|
|
for normal use. */
|
2010-03-27 09:20:53 +03:00
|
|
|
qemu_mod_timer(s->sector_write_timer,
|
2011-03-11 18:47:48 +03:00
|
|
|
qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
|
2010-03-27 09:20:53 +03:00
|
|
|
} else {
|
2009-08-28 18:37:42 +04:00
|
|
|
ide_set_irq(s->bus);
|
2007-11-08 19:38:17 +03:00
|
|
|
}
|
2003-11-11 16:48:59 +03:00
|
|
|
}
|
|
|
|
|
2012-03-29 13:31:31 +04:00
|
|
|
void ide_sector_write(IDEState *s)
|
|
|
|
{
|
|
|
|
int64_t sector_num;
|
|
|
|
int n;
|
|
|
|
|
|
|
|
s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
|
|
|
|
sector_num = ide_get_sector(s);
|
|
|
|
#if defined(DEBUG_IDE)
|
|
|
|
printf("sector=%" PRId64 "\n", sector_num);
|
|
|
|
#endif
|
|
|
|
n = s->nsector;
|
|
|
|
if (n > s->req_nb_sectors) {
|
|
|
|
n = s->req_nb_sectors;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->iov.iov_base = s->io_buffer;
|
|
|
|
s->iov.iov_len = n * BDRV_SECTOR_SIZE;
|
|
|
|
qemu_iovec_init_external(&s->qiov, &s->iov, 1);
|
|
|
|
|
|
|
|
bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
|
|
|
|
s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n,
|
|
|
|
ide_sector_write_cb, s);
|
|
|
|
}
|
|
|
|
|
2009-09-04 21:02:06 +04:00
|
|
|
static void ide_flush_cb(void *opaque, int ret)
|
|
|
|
{
|
|
|
|
IDEState *s = opaque;
|
|
|
|
|
2010-10-18 19:13:05 +04:00
|
|
|
if (ret < 0) {
|
|
|
|
/* XXX: What sector number to set here? */
|
|
|
|
if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
2009-09-04 21:02:06 +04:00
|
|
|
|
2011-08-25 10:26:01 +04:00
|
|
|
bdrv_acct_done(s->bs, &s->acct);
|
2009-09-04 21:02:06 +04:00
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
2013-07-15 13:25:55 +04:00
|
|
|
ide_async_cmd_done(s);
|
2009-09-04 21:02:06 +04:00
|
|
|
ide_set_irq(s->bus);
|
|
|
|
}
|
|
|
|
|
2010-12-15 02:23:00 +03:00
|
|
|
void ide_flush_cache(IDEState *s)
|
2010-10-18 19:10:49 +04:00
|
|
|
{
|
2010-10-27 15:04:15 +04:00
|
|
|
if (s->bs == NULL) {
|
2010-10-18 19:10:49 +04:00
|
|
|
ide_flush_cb(s, 0);
|
2010-10-27 15:04:15 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-06-05 17:17:57 +04:00
|
|
|
s->status |= BUSY_STAT;
|
2011-08-25 10:26:01 +04:00
|
|
|
bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
|
2011-11-30 12:12:30 +04:00
|
|
|
bdrv_aio_flush(s->bs, ide_flush_cb, s);
|
2010-10-18 19:10:49 +04:00
|
|
|
}
|
|
|
|
|
2007-04-30 04:51:09 +04:00
|
|
|
static void ide_cfata_metadata_inquiry(IDEState *s)
|
|
|
|
{
|
|
|
|
uint16_t *p;
|
|
|
|
uint32_t spd;
|
|
|
|
|
|
|
|
p = (uint16_t *) s->io_buffer;
|
|
|
|
memset(p, 0, 0x200);
|
|
|
|
spd = ((s->mdata_size - 1) >> 9) + 1;
|
|
|
|
|
|
|
|
put_le16(p + 0, 0x0001); /* Data format revision */
|
|
|
|
put_le16(p + 1, 0x0000); /* Media property: silicon */
|
|
|
|
put_le16(p + 2, s->media_changed); /* Media status */
|
|
|
|
put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
|
|
|
|
put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
|
|
|
|
put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
|
|
|
|
put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ide_cfata_metadata_read(IDEState *s)
|
|
|
|
{
|
|
|
|
uint16_t *p;
|
|
|
|
|
|
|
|
if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
|
|
|
|
s->status = ERR_STAT;
|
|
|
|
s->error = ABRT_ERR;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
p = (uint16_t *) s->io_buffer;
|
|
|
|
memset(p, 0, 0x200);
|
|
|
|
|
|
|
|
put_le16(p + 0, s->media_changed); /* Media status */
|
|
|
|
memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
|
|
|
|
MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
|
|
|
|
s->nsector << 9), 0x200 - 2));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ide_cfata_metadata_write(IDEState *s)
|
|
|
|
{
|
|
|
|
if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
|
|
|
|
s->status = ERR_STAT;
|
|
|
|
s->error = ABRT_ERR;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->media_changed = 0;
|
|
|
|
|
|
|
|
memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
|
|
|
|
s->io_buffer + 2,
|
|
|
|
MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
|
|
|
|
s->nsector << 9), 0x200 - 2));
|
|
|
|
}
|
|
|
|
|
2006-12-22 05:14:49 +03:00
|
|
|
/* called when the inserted state of the media has changed */
|
2011-09-06 20:58:59 +04:00
|
|
|
static void ide_cd_change_cb(void *opaque, bool load)
|
2006-12-22 05:14:49 +03:00
|
|
|
{
|
|
|
|
IDEState *s = opaque;
|
2007-12-17 04:35:20 +03:00
|
|
|
uint64_t nb_sectors;
|
2006-12-22 05:14:49 +03:00
|
|
|
|
2011-09-06 20:59:00 +04:00
|
|
|
s->tray_open = !load;
|
2006-12-22 05:14:49 +03:00
|
|
|
bdrv_get_geometry(s->bs, &nb_sectors);
|
|
|
|
s->nb_sectors = nb_sectors;
|
2008-11-11 23:57:30 +03:00
|
|
|
|
2011-04-18 15:45:46 +04:00
|
|
|
/*
|
|
|
|
* First indicate to the guest that a CD has been removed. That's
|
|
|
|
* done on the next command the guest sends us.
|
|
|
|
*
|
2011-09-13 16:41:56 +04:00
|
|
|
* Then we set UNIT_ATTENTION, by which the guest will
|
2011-04-18 15:45:46 +04:00
|
|
|
* detect a new CD in the drive. See ide_atapi_cmd() for details.
|
|
|
|
*/
|
2009-08-02 12:36:47 +04:00
|
|
|
s->cdrom_changed = 1;
|
2011-04-12 20:06:07 +04:00
|
|
|
s->events.new_media = true;
|
2011-10-25 14:53:39 +04:00
|
|
|
s->events.eject_request = false;
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ide_cd_eject_request_cb(void *opaque, bool force)
|
|
|
|
{
|
|
|
|
IDEState *s = opaque;
|
|
|
|
|
|
|
|
s->events.eject_request = true;
|
|
|
|
if (force) {
|
|
|
|
s->tray_locked = false;
|
|
|
|
}
|
2009-08-28 18:37:42 +04:00
|
|
|
ide_set_irq(s->bus);
|
2006-12-22 05:14:49 +03:00
|
|
|
}
|
|
|
|
|
2006-04-26 01:24:22 +04:00
|
|
|
static void ide_cmd_lba48_transform(IDEState *s, int lba48)
|
|
|
|
{
|
|
|
|
s->lba48 = lba48;
|
|
|
|
|
|
|
|
/* handle the 'magic' 0 nsector count conversion here. to avoid
|
|
|
|
* fiddling with the rest of the read logic, we just store the
|
|
|
|
* full sector count in ->nsector and ignore ->hob_nsector from now
|
|
|
|
*/
|
|
|
|
if (!s->lba48) {
|
|
|
|
if (!s->nsector)
|
|
|
|
s->nsector = 256;
|
|
|
|
} else {
|
|
|
|
if (!s->nsector && !s->hob_nsector)
|
|
|
|
s->nsector = 65536;
|
|
|
|
else {
|
|
|
|
int lo = s->nsector;
|
|
|
|
int hi = s->hob_nsector;
|
|
|
|
|
|
|
|
s->nsector = (hi << 8) | lo;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:17 +04:00
|
|
|
static void ide_clear_hob(IDEBus *bus)
|
2006-04-26 01:24:22 +04:00
|
|
|
{
|
|
|
|
/* any write clears HOB high bit of device control register */
|
2009-08-20 17:22:17 +04:00
|
|
|
bus->ifs[0].select &= ~(1 << 7);
|
|
|
|
bus->ifs[1].select &= ~(1 << 7);
|
2006-04-26 01:24:22 +04:00
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
|
2004-03-15 00:40:43 +03:00
|
|
|
{
|
2009-08-20 17:22:17 +04:00
|
|
|
IDEBus *bus = opaque;
|
2003-11-11 16:48:59 +03:00
|
|
|
|
|
|
|
#ifdef DEBUG_IDE
|
|
|
|
printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
|
|
|
|
#endif
|
2006-04-26 01:24:22 +04:00
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
addr &= 7;
|
2008-08-22 02:40:00 +04:00
|
|
|
|
|
|
|
/* ignore writes to command block while busy with previous command */
|
2009-08-20 17:22:17 +04:00
|
|
|
if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
|
2008-08-22 02:40:00 +04:00
|
|
|
return;
|
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
switch(addr) {
|
|
|
|
case 0:
|
|
|
|
break;
|
|
|
|
case 1:
|
2009-08-20 17:22:17 +04:00
|
|
|
ide_clear_hob(bus);
|
2004-03-21 01:01:15 +03:00
|
|
|
/* NOTE: data is written to the two drives */
|
2009-08-20 17:22:17 +04:00
|
|
|
bus->ifs[0].hob_feature = bus->ifs[0].feature;
|
|
|
|
bus->ifs[1].hob_feature = bus->ifs[1].feature;
|
|
|
|
bus->ifs[0].feature = val;
|
|
|
|
bus->ifs[1].feature = val;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
case 2:
|
2009-08-20 17:22:17 +04:00
|
|
|
ide_clear_hob(bus);
|
|
|
|
bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
|
|
|
|
bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
|
|
|
|
bus->ifs[0].nsector = val;
|
|
|
|
bus->ifs[1].nsector = val;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
case 3:
|
2009-08-20 17:22:17 +04:00
|
|
|
ide_clear_hob(bus);
|
|
|
|
bus->ifs[0].hob_sector = bus->ifs[0].sector;
|
|
|
|
bus->ifs[1].hob_sector = bus->ifs[1].sector;
|
|
|
|
bus->ifs[0].sector = val;
|
|
|
|
bus->ifs[1].sector = val;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
case 4:
|
2009-08-20 17:22:17 +04:00
|
|
|
ide_clear_hob(bus);
|
|
|
|
bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
|
|
|
|
bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
|
|
|
|
bus->ifs[0].lcyl = val;
|
|
|
|
bus->ifs[1].lcyl = val;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
case 5:
|
2009-08-20 17:22:17 +04:00
|
|
|
ide_clear_hob(bus);
|
|
|
|
bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
|
|
|
|
bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
|
|
|
|
bus->ifs[0].hcyl = val;
|
|
|
|
bus->ifs[1].hcyl = val;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
case 6:
|
2006-04-26 01:24:22 +04:00
|
|
|
/* FIXME: HOB readback uses bit 7 */
|
2009-08-20 17:22:17 +04:00
|
|
|
bus->ifs[0].select = (val & ~0x10) | 0xa0;
|
|
|
|
bus->ifs[1].select = (val | 0x10) | 0xa0;
|
2003-11-11 16:48:59 +03:00
|
|
|
/* select drive */
|
2009-08-20 17:22:17 +04:00
|
|
|
bus->unit = (val >> 4) & 1;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 7:
|
|
|
|
/* command */
|
2010-12-14 03:34:33 +03:00
|
|
|
ide_exec_cmd(bus, val);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:25:58 +04:00
|
|
|
static bool cmd_nop(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:25:56 +04:00
|
|
|
static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
switch (s->feature) {
|
|
|
|
case DSM_TRIM:
|
|
|
|
if (s->bs) {
|
|
|
|
ide_sector_start_dma(s, IDE_DMA_TRIM);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:25:57 +04:00
|
|
|
static bool cmd_identify(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
if (s->bs && s->drive_kind != IDE_CD) {
|
|
|
|
if (s->drive_kind != IDE_CFATA) {
|
|
|
|
ide_identify(s);
|
|
|
|
} else {
|
|
|
|
ide_cfata_identify(s);
|
|
|
|
}
|
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
|
|
|
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
if (s->drive_kind == IDE_CD) {
|
|
|
|
ide_set_signature(s);
|
|
|
|
}
|
|
|
|
ide_abort_command(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:25:59 +04:00
|
|
|
static bool cmd_verify(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
bool lba48 = (cmd == WIN_VERIFY_EXT);
|
|
|
|
|
|
|
|
/* do sector number check ? */
|
|
|
|
ide_cmd_lba48_transform(s, lba48);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:00 +04:00
|
|
|
static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
|
|
|
|
/* Disable Read and Write Multiple */
|
|
|
|
s->mult_sectors = 0;
|
|
|
|
} else if ((s->nsector & 0xff) != 0 &&
|
|
|
|
((s->nsector & 0xff) > MAX_MULT_SECTORS ||
|
|
|
|
(s->nsector & (s->nsector - 1)) != 0)) {
|
|
|
|
ide_abort_command(s);
|
|
|
|
} else {
|
|
|
|
s->mult_sectors = s->nsector & 0xff;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
bool lba48 = (cmd == WIN_MULTREAD_EXT);
|
|
|
|
|
|
|
|
if (!s->bs || !s->mult_sectors) {
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ide_cmd_lba48_transform(s, lba48);
|
|
|
|
s->req_nb_sectors = s->mult_sectors;
|
|
|
|
ide_sector_read(s);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
bool lba48 = (cmd == WIN_MULTWRITE_EXT);
|
|
|
|
int n;
|
|
|
|
|
|
|
|
if (!s->bs || !s->mult_sectors) {
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ide_cmd_lba48_transform(s, lba48);
|
|
|
|
|
|
|
|
s->req_nb_sectors = s->mult_sectors;
|
|
|
|
n = MIN(s->nsector, s->req_nb_sectors);
|
|
|
|
|
|
|
|
s->status = SEEK_STAT | READY_STAT;
|
|
|
|
ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
|
|
|
|
|
|
|
|
s->media_changed = 1;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:01 +04:00
|
|
|
static bool cmd_read_pio(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
bool lba48 = (cmd == WIN_READ_EXT);
|
|
|
|
|
|
|
|
if (s->drive_kind == IDE_CD) {
|
|
|
|
ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!s->bs) {
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ide_cmd_lba48_transform(s, lba48);
|
|
|
|
s->req_nb_sectors = 1;
|
|
|
|
ide_sector_read(s);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_write_pio(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
bool lba48 = (cmd == WIN_WRITE_EXT);
|
|
|
|
|
|
|
|
if (!s->bs) {
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ide_cmd_lba48_transform(s, lba48);
|
|
|
|
|
|
|
|
s->req_nb_sectors = 1;
|
|
|
|
s->status = SEEK_STAT | READY_STAT;
|
|
|
|
ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
|
|
|
|
|
|
|
|
s->media_changed = 1;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:02 +04:00
|
|
|
static bool cmd_read_dma(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
bool lba48 = (cmd == WIN_READDMA_EXT);
|
|
|
|
|
|
|
|
if (!s->bs) {
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ide_cmd_lba48_transform(s, lba48);
|
|
|
|
ide_sector_start_dma(s, IDE_DMA_READ);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_write_dma(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
bool lba48 = (cmd == WIN_WRITEDMA_EXT);
|
|
|
|
|
|
|
|
if (!s->bs) {
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ide_cmd_lba48_transform(s, lba48);
|
|
|
|
ide_sector_start_dma(s, IDE_DMA_WRITE);
|
|
|
|
|
|
|
|
s->media_changed = 1;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:06 +04:00
|
|
|
static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
ide_flush_cache(s);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:07 +04:00
|
|
|
static bool cmd_seek(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
/* XXX: Check that seek is within bounds */
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:03 +04:00
|
|
|
static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
|
|
|
|
|
|
|
|
/* Refuse if no sectors are addressable (e.g. medium not inserted) */
|
|
|
|
if (s->nb_sectors == 0) {
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ide_cmd_lba48_transform(s, lba48);
|
|
|
|
ide_set_sector(s, s->nb_sectors - 1);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:04 +04:00
|
|
|
static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
s->nsector = 0xff; /* device active or idle */
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:05 +04:00
|
|
|
static bool cmd_set_features(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
uint16_t *identify_data;
|
|
|
|
|
|
|
|
if (!s->bs) {
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX: valid for CDROM ? */
|
|
|
|
switch (s->feature) {
|
|
|
|
case 0x02: /* write cache enable */
|
|
|
|
bdrv_set_enable_write_cache(s->bs, true);
|
|
|
|
identify_data = (uint16_t *)s->identify_data;
|
|
|
|
put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
|
|
|
|
return true;
|
|
|
|
case 0x82: /* write cache disable */
|
|
|
|
bdrv_set_enable_write_cache(s->bs, false);
|
|
|
|
identify_data = (uint16_t *)s->identify_data;
|
|
|
|
put_le16(identify_data + 85, (1 << 14) | 1);
|
|
|
|
ide_flush_cache(s);
|
|
|
|
return false;
|
|
|
|
case 0xcc: /* reverting to power-on defaults enable */
|
|
|
|
case 0x66: /* reverting to power-on defaults disable */
|
|
|
|
case 0xaa: /* read look-ahead enable */
|
|
|
|
case 0x55: /* read look-ahead disable */
|
|
|
|
case 0x05: /* set advanced power management mode */
|
|
|
|
case 0x85: /* disable advanced power management mode */
|
|
|
|
case 0x69: /* NOP */
|
|
|
|
case 0x67: /* NOP */
|
|
|
|
case 0x96: /* NOP */
|
|
|
|
case 0x9a: /* NOP */
|
|
|
|
case 0x42: /* enable Automatic Acoustic Mode */
|
|
|
|
case 0xc2: /* disable Automatic Acoustic Mode */
|
|
|
|
return true;
|
|
|
|
case 0x03: /* set transfer mode */
|
|
|
|
{
|
|
|
|
uint8_t val = s->nsector & 0x07;
|
|
|
|
identify_data = (uint16_t *)s->identify_data;
|
|
|
|
|
|
|
|
switch (s->nsector >> 3) {
|
|
|
|
case 0x00: /* pio default */
|
|
|
|
case 0x01: /* pio mode */
|
|
|
|
put_le16(identify_data + 62, 0x07);
|
|
|
|
put_le16(identify_data + 63, 0x07);
|
|
|
|
put_le16(identify_data + 88, 0x3f);
|
|
|
|
break;
|
|
|
|
case 0x02: /* sigle word dma mode*/
|
|
|
|
put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
|
|
|
|
put_le16(identify_data + 63, 0x07);
|
|
|
|
put_le16(identify_data + 88, 0x3f);
|
|
|
|
break;
|
|
|
|
case 0x04: /* mdma mode */
|
|
|
|
put_le16(identify_data + 62, 0x07);
|
|
|
|
put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
|
|
|
|
put_le16(identify_data + 88, 0x3f);
|
|
|
|
break;
|
|
|
|
case 0x08: /* udma mode */
|
|
|
|
put_le16(identify_data + 62, 0x07);
|
|
|
|
put_le16(identify_data + 63, 0x07);
|
|
|
|
put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
goto abort_cmd;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
abort_cmd:
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:08 +04:00
|
|
|
|
|
|
|
/*** ATAPI commands ***/
|
|
|
|
|
|
|
|
static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
ide_atapi_identify(s);
|
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
|
|
|
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
ide_set_signature(s);
|
|
|
|
|
|
|
|
if (s->drive_kind == IDE_CD) {
|
|
|
|
s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
|
|
|
|
* devices to return a clear status register
|
|
|
|
* with READY_STAT *not* set. */
|
|
|
|
} else {
|
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
|
|
|
/* The bits of the error register are not as usual for this command!
|
|
|
|
* They are part of the regular output (this is why ERR_STAT isn't set)
|
|
|
|
* Device 0 passed, Device 1 passed or not present. */
|
|
|
|
s->error = 0x01;
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_device_reset(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
ide_set_signature(s);
|
|
|
|
s->status = 0x00; /* NOTE: READY is _not_ set */
|
|
|
|
s->error = 0x01;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_packet(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
/* overlapping commands not supported */
|
|
|
|
if (s->feature & 0x02) {
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
|
|
|
s->atapi_dma = s->feature & 1;
|
|
|
|
s->nsector = 1;
|
|
|
|
ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
|
|
|
|
ide_atapi_cmd);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:09 +04:00
|
|
|
|
|
|
|
/*** CF-ATA commands ***/
|
|
|
|
|
|
|
|
static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
s->error = 0x09; /* miscellaneous error */
|
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
/* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
|
|
|
|
* required for Windows 8 to work with AHCI */
|
|
|
|
|
|
|
|
if (cmd == CFA_WEAR_LEVEL) {
|
|
|
|
s->nsector = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cmd == CFA_ERASE_SECTORS) {
|
|
|
|
s->media_changed = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
|
|
|
|
|
|
|
memset(s->io_buffer, 0, 0x200);
|
|
|
|
s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
|
|
|
|
s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
|
|
|
|
s->io_buffer[0x02] = s->select; /* Head */
|
|
|
|
s->io_buffer[0x03] = s->sector; /* Sector */
|
|
|
|
s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
|
|
|
|
s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
|
|
|
|
s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
|
|
|
|
s->io_buffer[0x13] = 0x00; /* Erase flag */
|
|
|
|
s->io_buffer[0x18] = 0x00; /* Hot count */
|
|
|
|
s->io_buffer[0x19] = 0x00; /* Hot count */
|
|
|
|
s->io_buffer[0x1a] = 0x01; /* Hot count */
|
|
|
|
|
|
|
|
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
switch (s->feature) {
|
|
|
|
case 0x02: /* Inquiry Metadata Storage */
|
|
|
|
ide_cfata_metadata_inquiry(s);
|
|
|
|
break;
|
|
|
|
case 0x03: /* Read Metadata Storage */
|
|
|
|
ide_cfata_metadata_read(s);
|
|
|
|
break;
|
|
|
|
case 0x04: /* Write Metadata Storage */
|
|
|
|
ide_cfata_metadata_write(s);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
|
|
|
s->status = 0x00; /* NOTE: READY is _not_ set */
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
switch (s->feature) {
|
|
|
|
case 0x01: /* sense temperature in device */
|
|
|
|
s->nsector = 0x50; /* +20 C */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:10 +04:00
|
|
|
|
|
|
|
/*** SMART commands ***/
|
|
|
|
|
|
|
|
static bool cmd_smart(IDEState *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
int n;
|
|
|
|
|
|
|
|
if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
|
|
|
|
goto abort_cmd;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!s->smart_enabled && s->feature != SMART_ENABLE) {
|
|
|
|
goto abort_cmd;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (s->feature) {
|
|
|
|
case SMART_DISABLE:
|
|
|
|
s->smart_enabled = 0;
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case SMART_ENABLE:
|
|
|
|
s->smart_enabled = 1;
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case SMART_ATTR_AUTOSAVE:
|
|
|
|
switch (s->sector) {
|
|
|
|
case 0x00:
|
|
|
|
s->smart_autosave = 0;
|
|
|
|
break;
|
|
|
|
case 0xf1:
|
|
|
|
s->smart_autosave = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
goto abort_cmd;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case SMART_STATUS:
|
|
|
|
if (!s->smart_errors) {
|
|
|
|
s->hcyl = 0xc2;
|
|
|
|
s->lcyl = 0x4f;
|
|
|
|
} else {
|
|
|
|
s->hcyl = 0x2c;
|
|
|
|
s->lcyl = 0xf4;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case SMART_READ_THRESH:
|
|
|
|
memset(s->io_buffer, 0, 0x200);
|
|
|
|
s->io_buffer[0] = 0x01; /* smart struct version */
|
|
|
|
|
|
|
|
for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
|
|
|
|
s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
|
|
|
|
s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
|
|
|
|
}
|
|
|
|
|
|
|
|
/* checksum */
|
|
|
|
for (n = 0; n < 511; n++) {
|
|
|
|
s->io_buffer[511] += s->io_buffer[n];
|
|
|
|
}
|
|
|
|
s->io_buffer[511] = 0x100 - s->io_buffer[511];
|
|
|
|
|
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
|
|
|
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
return false;
|
|
|
|
|
|
|
|
case SMART_READ_DATA:
|
|
|
|
memset(s->io_buffer, 0, 0x200);
|
|
|
|
s->io_buffer[0] = 0x01; /* smart struct version */
|
|
|
|
|
|
|
|
for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
|
|
|
|
int i;
|
|
|
|
for (i = 0; i < 11; i++) {
|
|
|
|
s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
|
|
|
|
if (s->smart_selftest_count == 0) {
|
|
|
|
s->io_buffer[363] = 0;
|
|
|
|
} else {
|
|
|
|
s->io_buffer[363] =
|
|
|
|
s->smart_selftest_data[3 +
|
|
|
|
(s->smart_selftest_count - 1) *
|
|
|
|
24];
|
|
|
|
}
|
|
|
|
s->io_buffer[364] = 0x20;
|
|
|
|
s->io_buffer[365] = 0x01;
|
|
|
|
/* offline data collection capacity: execute + self-test*/
|
|
|
|
s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
|
|
|
|
s->io_buffer[368] = 0x03; /* smart capability (1) */
|
|
|
|
s->io_buffer[369] = 0x00; /* smart capability (2) */
|
|
|
|
s->io_buffer[370] = 0x01; /* error logging supported */
|
|
|
|
s->io_buffer[372] = 0x02; /* minutes for poll short test */
|
|
|
|
s->io_buffer[373] = 0x36; /* minutes for poll ext test */
|
|
|
|
s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
|
|
|
|
|
|
|
|
for (n = 0; n < 511; n++) {
|
|
|
|
s->io_buffer[511] += s->io_buffer[n];
|
|
|
|
}
|
|
|
|
s->io_buffer[511] = 0x100 - s->io_buffer[511];
|
|
|
|
|
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
|
|
|
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
return false;
|
|
|
|
|
|
|
|
case SMART_READ_LOG:
|
|
|
|
switch (s->sector) {
|
|
|
|
case 0x01: /* summary smart error log */
|
|
|
|
memset(s->io_buffer, 0, 0x200);
|
|
|
|
s->io_buffer[0] = 0x01;
|
|
|
|
s->io_buffer[1] = 0x00; /* no error entries */
|
|
|
|
s->io_buffer[452] = s->smart_errors & 0xff;
|
|
|
|
s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
|
|
|
|
|
|
|
|
for (n = 0; n < 511; n++) {
|
|
|
|
s->io_buffer[511] += s->io_buffer[n];
|
|
|
|
}
|
|
|
|
s->io_buffer[511] = 0x100 - s->io_buffer[511];
|
|
|
|
break;
|
|
|
|
case 0x06: /* smart self test log */
|
|
|
|
memset(s->io_buffer, 0, 0x200);
|
|
|
|
s->io_buffer[0] = 0x01;
|
|
|
|
if (s->smart_selftest_count == 0) {
|
|
|
|
s->io_buffer[508] = 0;
|
|
|
|
} else {
|
|
|
|
s->io_buffer[508] = s->smart_selftest_count;
|
|
|
|
for (n = 2; n < 506; n++) {
|
|
|
|
s->io_buffer[n] = s->smart_selftest_data[n];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (n = 0; n < 511; n++) {
|
|
|
|
s->io_buffer[511] += s->io_buffer[n];
|
|
|
|
}
|
|
|
|
s->io_buffer[511] = 0x100 - s->io_buffer[511];
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
goto abort_cmd;
|
|
|
|
}
|
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
|
|
|
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
return false;
|
|
|
|
|
|
|
|
case SMART_EXECUTE_OFFLINE:
|
|
|
|
switch (s->sector) {
|
|
|
|
case 0: /* off-line routine */
|
|
|
|
case 1: /* short self test */
|
|
|
|
case 2: /* extended self test */
|
|
|
|
s->smart_selftest_count++;
|
|
|
|
if (s->smart_selftest_count > 21) {
|
|
|
|
s->smart_selftest_count = 0;
|
|
|
|
}
|
|
|
|
n = 2 + (s->smart_selftest_count - 1) * 24;
|
|
|
|
s->smart_selftest_data[n] = s->sector;
|
|
|
|
s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
|
|
|
|
s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
|
|
|
|
s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
goto abort_cmd;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
abort_cmd:
|
|
|
|
ide_abort_command(s);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-09-06 20:58:35 +04:00
|
|
|
#define HD_OK (1u << IDE_HD)
|
|
|
|
#define CD_OK (1u << IDE_CD)
|
|
|
|
#define CFA_OK (1u << IDE_CFATA)
|
|
|
|
#define HD_CFA_OK (HD_OK | CFA_OK)
|
|
|
|
#define ALL_OK (HD_OK | CD_OK | CFA_OK)
|
|
|
|
|
2013-06-18 12:25:55 +04:00
|
|
|
/* Set the Disk Seek Completed status bit during completion */
|
|
|
|
#define SET_DSC (1u << 8)
|
|
|
|
|
2011-09-06 20:58:35 +04:00
|
|
|
/* See ACS-2 T13/2015-D Table B.2 Command codes */
|
2013-06-18 12:25:55 +04:00
|
|
|
static const struct {
|
|
|
|
/* Returns true if the completion code should be run */
|
|
|
|
bool (*handler)(IDEState *s, uint8_t cmd);
|
|
|
|
int flags;
|
|
|
|
} ide_cmd_table[0x100] = {
|
2011-09-06 20:58:35 +04:00
|
|
|
/* NOP not implemented, mandatory for CD */
|
2013-06-18 12:26:09 +04:00
|
|
|
[CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
|
2013-06-18 12:25:56 +04:00
|
|
|
[WIN_DSM] = { cmd_data_set_management, ALL_OK },
|
2013-06-18 12:26:08 +04:00
|
|
|
[WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
|
2013-06-18 12:25:58 +04:00
|
|
|
[WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
|
2013-06-18 12:26:01 +04:00
|
|
|
[WIN_READ] = { cmd_read_pio, ALL_OK },
|
|
|
|
[WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
|
|
|
|
[WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
|
2013-06-18 12:26:02 +04:00
|
|
|
[WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
|
2013-06-18 12:26:03 +04:00
|
|
|
[WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
|
2013-06-18 12:26:00 +04:00
|
|
|
[WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
|
2013-06-18 12:26:01 +04:00
|
|
|
[WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
|
|
|
|
[WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
|
|
|
|
[WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
|
2013-06-18 12:26:02 +04:00
|
|
|
[WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
|
2013-06-18 12:26:01 +04:00
|
|
|
[CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
|
2013-06-18 12:26:00 +04:00
|
|
|
[WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
|
2013-06-18 12:26:01 +04:00
|
|
|
[WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
|
2013-06-18 12:25:59 +04:00
|
|
|
[WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
|
|
|
|
[WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
|
|
|
|
[WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
|
2013-06-18 12:26:07 +04:00
|
|
|
[WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
|
2013-06-18 12:26:09 +04:00
|
|
|
[CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
|
2013-06-18 12:26:08 +04:00
|
|
|
[WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
|
2013-06-18 12:25:58 +04:00
|
|
|
[WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
|
|
|
|
[WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
|
|
|
|
[WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
|
|
|
|
[WIN_STANDBY2] = { cmd_nop, ALL_OK },
|
|
|
|
[WIN_SETIDLE2] = { cmd_nop, ALL_OK },
|
2013-06-18 12:26:04 +04:00
|
|
|
[WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC },
|
2013-06-18 12:25:58 +04:00
|
|
|
[WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
|
2013-06-18 12:26:08 +04:00
|
|
|
[WIN_PACKETCMD] = { cmd_packet, CD_OK },
|
|
|
|
[WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
|
2013-06-18 12:26:10 +04:00
|
|
|
[WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
|
2013-06-18 12:26:09 +04:00
|
|
|
[CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
|
|
|
|
[CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
|
2013-06-18 12:26:00 +04:00
|
|
|
[WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
|
|
|
|
[WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
|
|
|
|
[WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
|
2013-06-18 12:26:02 +04:00
|
|
|
[WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
|
|
|
|
[WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
|
|
|
|
[WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
|
|
|
|
[WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
|
2013-06-18 12:26:00 +04:00
|
|
|
[CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
|
2013-06-18 12:25:58 +04:00
|
|
|
[WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
|
|
|
|
[WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
|
|
|
|
[WIN_STANDBY] = { cmd_nop, ALL_OK },
|
|
|
|
[WIN_SETIDLE1] = { cmd_nop, ALL_OK },
|
2013-06-18 12:26:04 +04:00
|
|
|
[WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC },
|
2013-06-18 12:25:58 +04:00
|
|
|
[WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
|
2013-06-18 12:26:06 +04:00
|
|
|
[WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
|
|
|
|
[WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
|
2013-06-18 12:25:57 +04:00
|
|
|
[WIN_IDENTIFY] = { cmd_identify, ALL_OK },
|
2013-06-18 12:26:05 +04:00
|
|
|
[WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
|
2013-06-18 12:26:09 +04:00
|
|
|
[IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
|
|
|
|
[CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
|
2013-06-18 12:26:03 +04:00
|
|
|
[WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC },
|
2011-09-06 20:58:35 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
|
|
|
|
{
|
|
|
|
return cmd < ARRAY_SIZE(ide_cmd_table)
|
2013-06-18 12:25:55 +04:00
|
|
|
&& (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
|
2011-09-06 20:58:35 +04:00
|
|
|
}
|
2010-12-14 03:34:33 +03:00
|
|
|
|
|
|
|
void ide_exec_cmd(IDEBus *bus, uint32_t val)
|
|
|
|
{
|
|
|
|
IDEState *s;
|
2013-06-18 12:26:11 +04:00
|
|
|
bool complete;
|
2010-12-14 03:34:33 +03:00
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
#if defined(DEBUG_IDE)
|
2010-12-14 03:34:34 +03:00
|
|
|
printf("ide: CMD=%02x\n", val);
|
2003-11-11 16:48:59 +03:00
|
|
|
#endif
|
2010-12-14 03:34:34 +03:00
|
|
|
s = idebus_active_if(bus);
|
2011-11-29 12:52:39 +04:00
|
|
|
/* ignore commands to non existent slave */
|
2010-12-14 03:34:34 +03:00
|
|
|
if (s != bus->ifs && !s->bs)
|
|
|
|
return;
|
2006-04-26 01:24:22 +04:00
|
|
|
|
2010-12-14 03:34:34 +03:00
|
|
|
/* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
|
|
|
|
if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
|
|
|
|
return;
|
2008-08-22 02:40:00 +04:00
|
|
|
|
2011-09-06 20:58:35 +04:00
|
|
|
if (!ide_cmd_permitted(s, val)) {
|
2013-06-18 12:26:11 +04:00
|
|
|
ide_abort_command(s);
|
|
|
|
ide_set_irq(s->bus);
|
|
|
|
return;
|
2011-09-06 20:58:35 +04:00
|
|
|
}
|
|
|
|
|
2013-06-18 12:26:11 +04:00
|
|
|
s->status = READY_STAT | BUSY_STAT;
|
|
|
|
s->error = 0;
|
2013-06-18 12:25:55 +04:00
|
|
|
|
2013-06-18 12:26:11 +04:00
|
|
|
complete = ide_cmd_table[val].handler(s, val);
|
|
|
|
if (complete) {
|
|
|
|
s->status &= ~BUSY_STAT;
|
|
|
|
assert(!!s->error == !!(s->status & ERR_STAT));
|
2013-06-18 12:25:55 +04:00
|
|
|
|
2013-06-18 12:26:11 +04:00
|
|
|
if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
|
|
|
|
s->status |= SEEK_STAT;
|
2013-06-18 12:25:55 +04:00
|
|
|
}
|
|
|
|
|
2010-12-14 03:34:34 +03:00
|
|
|
ide_set_irq(s->bus);
|
|
|
|
}
|
2003-11-11 16:48:59 +03:00
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
2009-08-20 17:22:17 +04:00
|
|
|
IDEBus *bus = opaque;
|
|
|
|
IDEState *s = idebus_active_if(bus);
|
2003-11-11 16:48:59 +03:00
|
|
|
uint32_t addr;
|
2006-04-26 01:24:22 +04:00
|
|
|
int ret, hob;
|
2003-11-11 16:48:59 +03:00
|
|
|
|
|
|
|
addr = addr1 & 7;
|
2006-04-26 01:24:22 +04:00
|
|
|
/* FIXME: HOB readback uses bit 7, but it's always set right now */
|
|
|
|
//hob = s->select & (1 << 7);
|
|
|
|
hob = 0;
|
2003-11-11 16:48:59 +03:00
|
|
|
switch(addr) {
|
|
|
|
case 0:
|
|
|
|
ret = 0xff;
|
|
|
|
break;
|
|
|
|
case 1:
|
2009-08-20 17:22:17 +04:00
|
|
|
if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
|
|
|
|
(s != bus->ifs && !s->bs))
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = 0;
|
2006-04-26 01:24:22 +04:00
|
|
|
else if (!hob)
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = s->error;
|
2006-04-26 01:24:22 +04:00
|
|
|
else
|
|
|
|
ret = s->hob_feature;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
case 2:
|
2009-08-20 17:22:17 +04:00
|
|
|
if (!bus->ifs[0].bs && !bus->ifs[1].bs)
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = 0;
|
2006-04-26 01:24:22 +04:00
|
|
|
else if (!hob)
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = s->nsector & 0xff;
|
2006-04-26 01:24:22 +04:00
|
|
|
else
|
|
|
|
ret = s->hob_nsector;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
case 3:
|
2009-08-20 17:22:17 +04:00
|
|
|
if (!bus->ifs[0].bs && !bus->ifs[1].bs)
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = 0;
|
2006-04-26 01:24:22 +04:00
|
|
|
else if (!hob)
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = s->sector;
|
2006-04-26 01:24:22 +04:00
|
|
|
else
|
|
|
|
ret = s->hob_sector;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
case 4:
|
2009-08-20 17:22:17 +04:00
|
|
|
if (!bus->ifs[0].bs && !bus->ifs[1].bs)
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = 0;
|
2006-04-26 01:24:22 +04:00
|
|
|
else if (!hob)
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = s->lcyl;
|
2006-04-26 01:24:22 +04:00
|
|
|
else
|
|
|
|
ret = s->hob_lcyl;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
case 5:
|
2009-08-20 17:22:17 +04:00
|
|
|
if (!bus->ifs[0].bs && !bus->ifs[1].bs)
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = 0;
|
2006-04-26 01:24:22 +04:00
|
|
|
else if (!hob)
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = s->hcyl;
|
2006-04-26 01:24:22 +04:00
|
|
|
else
|
|
|
|
ret = s->hob_hcyl;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
case 6:
|
2009-08-20 17:22:17 +04:00
|
|
|
if (!bus->ifs[0].bs && !bus->ifs[1].bs)
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = 0;
|
|
|
|
else
|
2004-04-08 02:13:51 +04:00
|
|
|
ret = s->select;
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 7:
|
2009-08-20 17:22:17 +04:00
|
|
|
if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
|
|
|
|
(s != bus->ifs && !s->bs))
|
2004-03-21 01:01:15 +03:00
|
|
|
ret = 0;
|
|
|
|
else
|
|
|
|
ret = s->status;
|
2009-08-28 18:37:42 +04:00
|
|
|
qemu_irq_lower(bus->irq);
|
2003-11-11 16:48:59 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
#ifdef DEBUG_IDE
|
|
|
|
printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
|
|
|
|
#endif
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
uint32_t ide_status_read(void *opaque, uint32_t addr)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
2009-08-20 17:22:17 +04:00
|
|
|
IDEBus *bus = opaque;
|
|
|
|
IDEState *s = idebus_active_if(bus);
|
2003-11-11 16:48:59 +03:00
|
|
|
int ret;
|
2004-04-08 02:13:51 +04:00
|
|
|
|
2009-08-20 17:22:17 +04:00
|
|
|
if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
|
|
|
|
(s != bus->ifs && !s->bs))
|
2004-04-08 02:13:51 +04:00
|
|
|
ret = 0;
|
|
|
|
else
|
|
|
|
ret = s->status;
|
2003-11-11 16:48:59 +03:00
|
|
|
#ifdef DEBUG_IDE
|
|
|
|
printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
|
|
|
|
#endif
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
2009-08-20 17:22:17 +04:00
|
|
|
IDEBus *bus = opaque;
|
2003-11-11 16:48:59 +03:00
|
|
|
IDEState *s;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
#ifdef DEBUG_IDE
|
|
|
|
printf("ide: write control addr=0x%x val=%02x\n", addr, val);
|
|
|
|
#endif
|
|
|
|
/* common for both drives */
|
2009-08-28 18:37:42 +04:00
|
|
|
if (!(bus->cmd & IDE_CMD_RESET) &&
|
2003-11-11 16:48:59 +03:00
|
|
|
(val & IDE_CMD_RESET)) {
|
|
|
|
/* reset low to high */
|
|
|
|
for(i = 0;i < 2; i++) {
|
2009-08-20 17:22:17 +04:00
|
|
|
s = &bus->ifs[i];
|
2003-11-11 16:48:59 +03:00
|
|
|
s->status = BUSY_STAT | SEEK_STAT;
|
|
|
|
s->error = 0x01;
|
|
|
|
}
|
2009-08-28 18:37:42 +04:00
|
|
|
} else if ((bus->cmd & IDE_CMD_RESET) &&
|
2003-11-11 16:48:59 +03:00
|
|
|
!(val & IDE_CMD_RESET)) {
|
|
|
|
/* high to low */
|
|
|
|
for(i = 0;i < 2; i++) {
|
2009-08-20 17:22:17 +04:00
|
|
|
s = &bus->ifs[i];
|
2010-05-28 15:32:45 +04:00
|
|
|
if (s->drive_kind == IDE_CD)
|
2004-01-04 21:08:12 +03:00
|
|
|
s->status = 0x00; /* NOTE: READY is _not_ set */
|
|
|
|
else
|
2004-02-01 20:24:11 +03:00
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
2003-11-11 16:48:59 +03:00
|
|
|
ide_set_signature(s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-28 18:37:42 +04:00
|
|
|
bus->cmd = val;
|
2003-11-11 16:48:59 +03:00
|
|
|
}
|
|
|
|
|
2011-07-04 16:07:50 +04:00
|
|
|
/*
|
|
|
|
* Returns true if the running PIO transfer is a PIO out (i.e. data is
|
|
|
|
* transferred from the device to the guest), false if it's a PIO in
|
|
|
|
*/
|
|
|
|
static bool ide_is_pio_out(IDEState *s)
|
|
|
|
{
|
|
|
|
if (s->end_transfer_func == ide_sector_write ||
|
|
|
|
s->end_transfer_func == ide_atapi_cmd) {
|
|
|
|
return false;
|
|
|
|
} else if (s->end_transfer_func == ide_sector_read ||
|
|
|
|
s->end_transfer_func == ide_transfer_stop ||
|
|
|
|
s->end_transfer_func == ide_atapi_cmd_reply_end ||
|
|
|
|
s->end_transfer_func == ide_dummy_transfer_stop) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
2009-08-20 17:22:17 +04:00
|
|
|
IDEBus *bus = opaque;
|
|
|
|
IDEState *s = idebus_active_if(bus);
|
2003-11-11 16:48:59 +03:00
|
|
|
uint8_t *p;
|
|
|
|
|
2011-07-04 16:07:50 +04:00
|
|
|
/* PIO data access allowed only when DRQ bit is set. The result of a write
|
|
|
|
* during PIO out is indeterminate, just ignore it. */
|
|
|
|
if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
|
2008-08-22 02:40:00 +04:00
|
|
|
return;
|
2011-07-04 16:07:50 +04:00
|
|
|
}
|
2008-08-22 02:40:00 +04:00
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
p = s->data_ptr;
|
2004-04-26 02:09:16 +04:00
|
|
|
*(uint16_t *)p = le16_to_cpu(val);
|
2003-11-11 16:48:59 +03:00
|
|
|
p += 2;
|
|
|
|
s->data_ptr = p;
|
|
|
|
if (p >= s->data_end)
|
|
|
|
s->end_transfer_func(s);
|
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
uint32_t ide_data_readw(void *opaque, uint32_t addr)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
2009-08-20 17:22:17 +04:00
|
|
|
IDEBus *bus = opaque;
|
|
|
|
IDEState *s = idebus_active_if(bus);
|
2003-11-11 16:48:59 +03:00
|
|
|
uint8_t *p;
|
|
|
|
int ret;
|
2008-08-22 02:40:00 +04:00
|
|
|
|
2011-07-04 16:07:50 +04:00
|
|
|
/* PIO data access allowed only when DRQ bit is set. The result of a read
|
|
|
|
* during PIO in is indeterminate, return 0 and don't move forward. */
|
|
|
|
if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
|
2008-08-22 02:40:00 +04:00
|
|
|
return 0;
|
2011-07-04 16:07:50 +04:00
|
|
|
}
|
2008-08-22 02:40:00 +04:00
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
p = s->data_ptr;
|
2004-04-26 02:09:16 +04:00
|
|
|
ret = cpu_to_le16(*(uint16_t *)p);
|
2003-11-11 16:48:59 +03:00
|
|
|
p += 2;
|
|
|
|
s->data_ptr = p;
|
|
|
|
if (p >= s->data_end)
|
|
|
|
s->end_transfer_func(s);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
2009-08-20 17:22:17 +04:00
|
|
|
IDEBus *bus = opaque;
|
|
|
|
IDEState *s = idebus_active_if(bus);
|
2003-11-11 16:48:59 +03:00
|
|
|
uint8_t *p;
|
|
|
|
|
2011-07-04 16:07:50 +04:00
|
|
|
/* PIO data access allowed only when DRQ bit is set. The result of a write
|
|
|
|
* during PIO out is indeterminate, just ignore it. */
|
|
|
|
if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
|
2008-08-22 02:40:00 +04:00
|
|
|
return;
|
2011-07-04 16:07:50 +04:00
|
|
|
}
|
2008-08-22 02:40:00 +04:00
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
p = s->data_ptr;
|
2004-04-26 02:09:16 +04:00
|
|
|
*(uint32_t *)p = le32_to_cpu(val);
|
2003-11-11 16:48:59 +03:00
|
|
|
p += 4;
|
|
|
|
s->data_ptr = p;
|
|
|
|
if (p >= s->data_end)
|
|
|
|
s->end_transfer_func(s);
|
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:18 +04:00
|
|
|
uint32_t ide_data_readl(void *opaque, uint32_t addr)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
2009-08-20 17:22:17 +04:00
|
|
|
IDEBus *bus = opaque;
|
|
|
|
IDEState *s = idebus_active_if(bus);
|
2003-11-11 16:48:59 +03:00
|
|
|
uint8_t *p;
|
|
|
|
int ret;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2011-07-04 16:07:50 +04:00
|
|
|
/* PIO data access allowed only when DRQ bit is set. The result of a read
|
|
|
|
* during PIO in is indeterminate, return 0 and don't move forward. */
|
|
|
|
if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
|
2008-08-22 02:40:00 +04:00
|
|
|
return 0;
|
2011-07-04 16:07:50 +04:00
|
|
|
}
|
2008-08-22 02:40:00 +04:00
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
p = s->data_ptr;
|
2004-04-26 02:09:16 +04:00
|
|
|
ret = cpu_to_le32(*(uint32_t *)p);
|
2003-11-11 16:48:59 +03:00
|
|
|
p += 4;
|
|
|
|
s->data_ptr = p;
|
|
|
|
if (p >= s->data_end)
|
|
|
|
s->end_transfer_func(s);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-10-10 00:27:55 +04:00
|
|
|
static void ide_dummy_transfer_stop(IDEState *s)
|
|
|
|
{
|
|
|
|
s->data_ptr = s->io_buffer;
|
|
|
|
s->data_end = s->io_buffer;
|
|
|
|
s->io_buffer[0] = 0xff;
|
|
|
|
s->io_buffer[1] = 0xff;
|
|
|
|
s->io_buffer[2] = 0xff;
|
|
|
|
s->io_buffer[3] = 0xff;
|
|
|
|
}
|
|
|
|
|
2009-11-07 17:13:05 +03:00
|
|
|
static void ide_reset(IDEState *s)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
2009-11-07 17:13:05 +03:00
|
|
|
#ifdef DEBUG_IDE
|
|
|
|
printf("ide: reset\n");
|
|
|
|
#endif
|
2012-03-29 13:31:30 +04:00
|
|
|
|
|
|
|
if (s->pio_aiocb) {
|
|
|
|
bdrv_aio_cancel(s->pio_aiocb);
|
|
|
|
s->pio_aiocb = NULL;
|
|
|
|
}
|
|
|
|
|
2010-05-28 15:32:45 +04:00
|
|
|
if (s->drive_kind == IDE_CFATA)
|
2007-04-30 04:51:09 +04:00
|
|
|
s->mult_sectors = 0;
|
|
|
|
else
|
|
|
|
s->mult_sectors = MAX_MULT_SECTORS;
|
2009-11-07 17:13:05 +03:00
|
|
|
/* ide regs */
|
|
|
|
s->feature = 0;
|
|
|
|
s->error = 0;
|
|
|
|
s->nsector = 0;
|
|
|
|
s->sector = 0;
|
|
|
|
s->lcyl = 0;
|
|
|
|
s->hcyl = 0;
|
|
|
|
|
|
|
|
/* lba48 */
|
|
|
|
s->hob_feature = 0;
|
|
|
|
s->hob_sector = 0;
|
|
|
|
s->hob_nsector = 0;
|
|
|
|
s->hob_lcyl = 0;
|
|
|
|
s->hob_hcyl = 0;
|
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
s->select = 0xa0;
|
2008-08-11 22:52:14 +04:00
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
2009-11-07 17:13:05 +03:00
|
|
|
|
|
|
|
s->lba48 = 0;
|
|
|
|
|
|
|
|
/* ATAPI specific */
|
|
|
|
s->sense_key = 0;
|
|
|
|
s->asc = 0;
|
|
|
|
s->cdrom_changed = 0;
|
|
|
|
s->packet_transfer_size = 0;
|
|
|
|
s->elementary_transfer_size = 0;
|
|
|
|
s->io_buffer_index = 0;
|
|
|
|
s->cd_sector_size = 0;
|
|
|
|
s->atapi_dma = 0;
|
2012-12-11 11:55:48 +04:00
|
|
|
s->tray_locked = 0;
|
|
|
|
s->tray_open = 0;
|
2009-11-07 17:13:05 +03:00
|
|
|
/* ATA DMA state */
|
|
|
|
s->io_buffer_size = 0;
|
|
|
|
s->req_nb_sectors = 0;
|
|
|
|
|
2003-11-11 16:48:59 +03:00
|
|
|
ide_set_signature(s);
|
2004-10-10 00:27:55 +04:00
|
|
|
/* init the transfer handler so that 0xffff is returned on data
|
|
|
|
accesses */
|
|
|
|
s->end_transfer_func = ide_dummy_transfer_stop;
|
|
|
|
ide_dummy_transfer_stop(s);
|
2007-04-30 04:51:09 +04:00
|
|
|
s->media_changed = 0;
|
2003-11-11 16:48:59 +03:00
|
|
|
}
|
|
|
|
|
2009-11-07 17:13:05 +03:00
|
|
|
void ide_bus_reset(IDEBus *bus)
|
|
|
|
{
|
|
|
|
bus->unit = 0;
|
|
|
|
bus->cmd = 0;
|
|
|
|
ide_reset(&bus->ifs[0]);
|
|
|
|
ide_reset(&bus->ifs[1]);
|
|
|
|
ide_clear_hob(bus);
|
2010-12-15 02:23:00 +03:00
|
|
|
|
|
|
|
/* pending async DMA */
|
|
|
|
if (bus->dma->aiocb) {
|
|
|
|
#ifdef DEBUG_AIO
|
|
|
|
printf("aio_cancel\n");
|
|
|
|
#endif
|
|
|
|
bdrv_aio_cancel(bus->dma->aiocb);
|
|
|
|
bus->dma->aiocb = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* reset dma provider too */
|
|
|
|
bus->dma->ops->reset(bus->dma);
|
2009-11-07 17:13:05 +03:00
|
|
|
}
|
|
|
|
|
2011-09-06 20:58:53 +04:00
|
|
|
static bool ide_cd_is_tray_open(void *opaque)
|
|
|
|
{
|
|
|
|
return ((IDEState *)opaque)->tray_open;
|
|
|
|
}
|
|
|
|
|
2011-09-06 20:58:46 +04:00
|
|
|
static bool ide_cd_is_medium_locked(void *opaque)
|
|
|
|
{
|
|
|
|
return ((IDEState *)opaque)->tray_locked;
|
|
|
|
}
|
|
|
|
|
2011-08-03 17:07:41 +04:00
|
|
|
static const BlockDevOps ide_cd_block_ops = {
|
2011-08-03 17:07:42 +04:00
|
|
|
.change_media_cb = ide_cd_change_cb,
|
2011-10-25 14:53:39 +04:00
|
|
|
.eject_request_cb = ide_cd_eject_request_cb,
|
2011-09-06 20:58:53 +04:00
|
|
|
.is_tray_open = ide_cd_is_tray_open,
|
2011-09-06 20:58:46 +04:00
|
|
|
.is_medium_locked = ide_cd_is_medium_locked,
|
2011-08-03 17:07:41 +04:00
|
|
|
};
|
|
|
|
|
2011-05-16 17:04:52 +04:00
|
|
|
int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
|
2012-03-13 16:31:47 +04:00
|
|
|
const char *version, const char *serial, const char *model,
|
2012-07-10 13:12:44 +04:00
|
|
|
uint64_t wwn,
|
|
|
|
uint32_t cylinders, uint32_t heads, uint32_t secs,
|
|
|
|
int chs_trans)
|
2009-09-15 23:23:30 +04:00
|
|
|
{
|
|
|
|
uint64_t nb_sectors;
|
|
|
|
|
2010-05-05 18:36:52 +04:00
|
|
|
s->bs = bs;
|
2011-05-16 17:04:52 +04:00
|
|
|
s->drive_kind = kind;
|
|
|
|
|
2010-05-05 18:36:52 +04:00
|
|
|
bdrv_get_geometry(bs, &nb_sectors);
|
2010-06-01 22:32:28 +04:00
|
|
|
s->cylinders = cylinders;
|
|
|
|
s->heads = heads;
|
|
|
|
s->sectors = secs;
|
2012-07-10 13:12:44 +04:00
|
|
|
s->chs_trans = chs_trans;
|
2010-06-01 22:32:28 +04:00
|
|
|
s->nb_sectors = nb_sectors;
|
2012-03-13 16:31:47 +04:00
|
|
|
s->wwn = wwn;
|
2010-06-01 22:32:28 +04:00
|
|
|
/* The SMART values should be preserved across power cycles
|
|
|
|
but they aren't. */
|
|
|
|
s->smart_enabled = 1;
|
|
|
|
s->smart_autosave = 1;
|
|
|
|
s->smart_errors = 0;
|
|
|
|
s->smart_selftest_count = 0;
|
2011-05-16 17:04:52 +04:00
|
|
|
if (kind == IDE_CD) {
|
2011-08-03 17:07:41 +04:00
|
|
|
bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
|
2011-09-06 20:58:56 +04:00
|
|
|
bdrv_set_buffer_alignment(bs, 2048);
|
2010-06-28 21:10:36 +04:00
|
|
|
} else {
|
2010-07-06 16:37:44 +04:00
|
|
|
if (!bdrv_is_inserted(s->bs)) {
|
|
|
|
error_report("Device needs media, but drive is empty");
|
|
|
|
return -1;
|
|
|
|
}
|
2010-06-28 21:10:36 +04:00
|
|
|
if (bdrv_is_read_only(bs)) {
|
|
|
|
error_report("Can't use a read-only drive");
|
|
|
|
return -1;
|
|
|
|
}
|
2009-09-15 23:23:30 +04:00
|
|
|
}
|
2010-05-05 18:36:52 +04:00
|
|
|
if (serial) {
|
2012-03-13 00:05:10 +04:00
|
|
|
pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
|
2010-06-01 22:32:32 +04:00
|
|
|
} else {
|
2009-09-15 23:23:30 +04:00
|
|
|
snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
|
|
|
|
"QM%05d", s->drive_serial);
|
2010-06-01 22:32:28 +04:00
|
|
|
}
|
2012-03-13 00:05:09 +04:00
|
|
|
if (model) {
|
|
|
|
pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
|
|
|
|
} else {
|
|
|
|
switch (kind) {
|
|
|
|
case IDE_CD:
|
|
|
|
strcpy(s->drive_model_str, "QEMU DVD-ROM");
|
|
|
|
break;
|
|
|
|
case IDE_CFATA:
|
|
|
|
strcpy(s->drive_model_str, "QEMU MICRODRIVE");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
strcpy(s->drive_model_str, "QEMU HARDDISK");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-01-14 16:44:12 +03:00
|
|
|
if (version) {
|
|
|
|
pstrcpy(s->version, sizeof(s->version), version);
|
|
|
|
} else {
|
2012-05-30 07:35:51 +04:00
|
|
|
pstrcpy(s->version, sizeof(s->version), qemu_get_version());
|
2010-01-14 16:44:12 +03:00
|
|
|
}
|
2010-12-15 02:23:00 +03:00
|
|
|
|
2009-09-15 23:23:30 +04:00
|
|
|
ide_reset(s);
|
2011-09-27 00:43:52 +04:00
|
|
|
bdrv_iostatus_enable(bs);
|
2010-06-28 21:07:51 +04:00
|
|
|
return 0;
|
2009-09-15 23:23:30 +04:00
|
|
|
}
|
|
|
|
|
2010-06-01 22:32:29 +04:00
|
|
|
static void ide_init1(IDEBus *bus, int unit)
|
2010-05-28 17:38:47 +04:00
|
|
|
{
|
|
|
|
static int drive_serial = 1;
|
|
|
|
IDEState *s = &bus->ifs[unit];
|
|
|
|
|
|
|
|
s->bus = bus;
|
|
|
|
s->unit = unit;
|
|
|
|
s->drive_serial = drive_serial++;
|
2010-09-13 01:44:00 +04:00
|
|
|
/* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
|
2010-07-26 23:38:44 +04:00
|
|
|
s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
|
2011-07-04 16:43:58 +04:00
|
|
|
s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
|
|
|
|
memset(s->io_buffer, 0, s->io_buffer_total_len);
|
|
|
|
|
2010-05-28 17:38:47 +04:00
|
|
|
s->smart_selftest_data = qemu_blockalign(s->bs, 512);
|
2011-07-04 16:43:58 +04:00
|
|
|
memset(s->smart_selftest_data, 0, 512);
|
|
|
|
|
2011-03-11 18:47:48 +03:00
|
|
|
s->sector_write_timer = qemu_new_timer_ns(vm_clock,
|
2010-05-28 17:38:47 +04:00
|
|
|
ide_sector_write_timer_cb, s);
|
2010-06-01 22:32:29 +04:00
|
|
|
}
|
|
|
|
|
2010-12-15 02:23:00 +03:00
|
|
|
static void ide_nop_start(IDEDMA *dma, IDEState *s,
|
|
|
|
BlockDriverCompletionFunc *cb)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ide_nop(IDEDMA *dma)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ide_nop_int(IDEDMA *dma, int x)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-07-29 21:26:33 +04:00
|
|
|
static void ide_nop_restart(void *opaque, int x, RunState y)
|
2010-12-15 02:23:00 +03:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static const IDEDMAOps ide_dma_nop_ops = {
|
|
|
|
.start_dma = ide_nop_start,
|
|
|
|
.start_transfer = ide_nop,
|
|
|
|
.prepare_buf = ide_nop_int,
|
|
|
|
.rw_buf = ide_nop_int,
|
|
|
|
.set_unit = ide_nop_int,
|
|
|
|
.add_status = ide_nop_int,
|
|
|
|
.set_inactive = ide_nop,
|
|
|
|
.restart_cb = ide_nop_restart,
|
|
|
|
.reset = ide_nop,
|
|
|
|
};
|
|
|
|
|
|
|
|
static IDEDMA ide_dma_nop = {
|
|
|
|
.ops = &ide_dma_nop_ops,
|
|
|
|
.aiocb = NULL,
|
|
|
|
};
|
|
|
|
|
2010-06-01 22:32:29 +04:00
|
|
|
void ide_init2(IDEBus *bus, qemu_irq irq)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for(i = 0; i < 2; i++) {
|
|
|
|
ide_init1(bus, i);
|
|
|
|
ide_reset(&bus->ifs[i]);
|
2010-06-01 22:32:28 +04:00
|
|
|
}
|
2010-06-01 22:32:29 +04:00
|
|
|
bus->irq = irq;
|
2010-12-15 02:23:00 +03:00
|
|
|
bus->dma = &ide_dma_nop;
|
2010-05-28 17:38:47 +04:00
|
|
|
}
|
|
|
|
|
2010-06-01 22:32:29 +04:00
|
|
|
/* TODO convert users to qdev and remove */
|
|
|
|
void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
|
|
|
|
DriveInfo *hd1, qemu_irq irq)
|
2003-11-11 16:48:59 +03:00
|
|
|
{
|
2012-07-10 13:12:44 +04:00
|
|
|
int i, trans;
|
2010-06-01 22:32:29 +04:00
|
|
|
DriveInfo *dinfo;
|
2012-07-10 13:12:44 +04:00
|
|
|
uint32_t cyls, heads, secs;
|
2003-11-11 16:48:59 +03:00
|
|
|
|
2004-03-15 00:40:43 +03:00
|
|
|
for(i = 0; i < 2; i++) {
|
2010-06-01 22:32:29 +04:00
|
|
|
dinfo = i == 0 ? hd0 : hd1;
|
|
|
|
ide_init1(bus, i);
|
|
|
|
if (dinfo) {
|
2012-07-10 13:12:44 +04:00
|
|
|
cyls = dinfo->cyls;
|
|
|
|
heads = dinfo->heads;
|
|
|
|
secs = dinfo->secs;
|
|
|
|
trans = dinfo->trans;
|
|
|
|
if (!cyls && !heads && !secs) {
|
|
|
|
hd_geometry_guess(dinfo->bdrv, &cyls, &heads, &secs, &trans);
|
2012-07-10 13:12:53 +04:00
|
|
|
} else if (trans == BIOS_ATA_TRANSLATION_AUTO) {
|
|
|
|
trans = hd_bios_chs_auto_trans(cyls, heads, secs);
|
2012-07-10 13:12:44 +04:00
|
|
|
}
|
2012-07-11 17:08:39 +04:00
|
|
|
if (cyls < 1 || cyls > 65535) {
|
|
|
|
error_report("cyls must be between 1 and 65535");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
if (heads < 1 || heads > 16) {
|
|
|
|
error_report("heads must be between 1 and 16");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
if (secs < 1 || secs > 255) {
|
|
|
|
error_report("secs must be between 1 and 255");
|
|
|
|
exit(1);
|
|
|
|
}
|
2011-05-16 17:04:52 +04:00
|
|
|
if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
|
2012-07-11 17:08:38 +04:00
|
|
|
dinfo->media_cd ? IDE_CD : IDE_HD,
|
|
|
|
NULL, dinfo->serial, NULL, 0,
|
|
|
|
cyls, heads, secs, trans) < 0) {
|
2010-06-28 21:07:51 +04:00
|
|
|
error_report("Can't set up IDE drive %s", dinfo->id);
|
|
|
|
exit(1);
|
|
|
|
}
|
2011-08-03 17:07:40 +04:00
|
|
|
bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]);
|
2010-06-01 22:32:29 +04:00
|
|
|
} else {
|
|
|
|
ide_reset(&bus->ifs[i]);
|
|
|
|
}
|
2003-11-11 16:48:59 +03:00
|
|
|
}
|
2009-08-28 18:37:42 +04:00
|
|
|
bus->irq = irq;
|
2010-12-15 02:23:00 +03:00
|
|
|
bus->dma = &ide_dma_nop;
|
2004-05-19 03:05:28 +04:00
|
|
|
}
|
|
|
|
|
2011-08-16 19:59:00 +04:00
|
|
|
static const MemoryRegionPortio ide_portio_list[] = {
|
|
|
|
{ 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
|
|
|
|
{ 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
|
|
|
|
{ 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
|
|
|
|
PORTIO_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionPortio ide_portio2_list[] = {
|
|
|
|
{ 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
|
|
|
|
PORTIO_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
|
2004-05-19 03:05:28 +04:00
|
|
|
{
|
2011-08-16 19:59:00 +04:00
|
|
|
/* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
|
|
|
|
bridge has been setup properly to always register with ISA. */
|
|
|
|
isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
|
|
|
|
|
2004-03-15 00:40:43 +03:00
|
|
|
if (iobase2) {
|
2011-08-16 19:59:00 +04:00
|
|
|
isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
|
2003-11-11 16:48:59 +03:00
|
|
|
}
|
|
|
|
}
|
2004-05-19 03:05:28 +04:00
|
|
|
|
2009-10-07 19:59:47 +04:00
|
|
|
static bool is_identify_set(void *opaque, int version_id)
|
2007-05-24 22:50:09 +04:00
|
|
|
{
|
2009-10-07 19:59:47 +04:00
|
|
|
IDEState *s = opaque;
|
|
|
|
|
|
|
|
return s->identify_set != 0;
|
|
|
|
}
|
|
|
|
|
2010-07-26 23:38:44 +04:00
|
|
|
static EndTransferFunc* transfer_end_table[] = {
|
|
|
|
ide_sector_read,
|
|
|
|
ide_sector_write,
|
|
|
|
ide_transfer_stop,
|
|
|
|
ide_atapi_cmd_reply_end,
|
|
|
|
ide_atapi_cmd,
|
|
|
|
ide_dummy_transfer_stop,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int transfer_end_table_idx(EndTransferFunc *fn)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
|
|
|
|
if (transfer_end_table[i] == fn)
|
|
|
|
return i;
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2009-10-07 19:59:47 +04:00
|
|
|
static int ide_drive_post_load(void *opaque, int version_id)
|
2007-05-24 22:50:09 +04:00
|
|
|
{
|
2009-10-07 19:59:47 +04:00
|
|
|
IDEState *s = opaque;
|
|
|
|
|
2012-06-06 02:04:54 +04:00
|
|
|
if (s->identify_set) {
|
|
|
|
bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5)));
|
|
|
|
}
|
2009-10-07 19:59:47 +04:00
|
|
|
return 0;
|
2007-05-24 22:50:09 +04:00
|
|
|
}
|
|
|
|
|
2010-07-26 23:38:44 +04:00
|
|
|
static int ide_drive_pio_post_load(void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
IDEState *s = opaque;
|
|
|
|
|
2011-10-26 13:52:47 +04:00
|
|
|
if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
|
2010-07-26 23:38:44 +04:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
|
|
|
|
s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
|
|
|
|
s->data_end = s->data_ptr + s->cur_io_buffer_len;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ide_drive_pio_pre_save(void *opaque)
|
|
|
|
{
|
|
|
|
IDEState *s = opaque;
|
|
|
|
int idx;
|
|
|
|
|
|
|
|
s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
|
|
|
|
s->cur_io_buffer_len = s->data_end - s->data_ptr;
|
|
|
|
|
|
|
|
idx = transfer_end_table_idx(s->end_transfer_func);
|
|
|
|
if (idx == -1) {
|
|
|
|
fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
|
|
|
|
__func__);
|
|
|
|
s->end_transfer_fn_idx = 2;
|
|
|
|
} else {
|
|
|
|
s->end_transfer_fn_idx = idx;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool ide_drive_pio_state_needed(void *opaque)
|
|
|
|
{
|
|
|
|
IDEState *s = opaque;
|
|
|
|
|
2011-06-09 16:12:57 +04:00
|
|
|
return ((s->status & DRQ_STAT) != 0)
|
|
|
|
|| (s->bus->error_status & BM_STATUS_PIO_RETRY);
|
2010-07-26 23:38:44 +04:00
|
|
|
}
|
|
|
|
|
2011-09-06 20:58:50 +04:00
|
|
|
static bool ide_tray_state_needed(void *opaque)
|
|
|
|
{
|
|
|
|
IDEState *s = opaque;
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return s->tray_open || s->tray_locked;
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|
}
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|
2011-04-12 20:06:07 +04:00
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static bool ide_atapi_gesn_needed(void *opaque)
|
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|
{
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|
|
IDEState *s = opaque;
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return s->events.new_media || s->events.eject_request;
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|
}
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|
2011-05-26 17:00:34 +04:00
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static bool ide_error_needed(void *opaque)
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|
{
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|
IDEBus *bus = opaque;
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return (bus->error_status != 0);
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}
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|
2011-04-12 20:06:07 +04:00
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/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
|
2011-08-03 17:08:04 +04:00
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static const VMStateDescription vmstate_ide_atapi_gesn_state = {
|
2011-04-12 20:06:07 +04:00
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.name ="ide_drive/atapi/gesn_state",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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|
|
.fields = (VMStateField []) {
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VMSTATE_BOOL(events.new_media, IDEState),
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VMSTATE_BOOL(events.eject_request, IDEState),
|
2011-06-09 16:15:18 +04:00
|
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VMSTATE_END_OF_LIST()
|
2011-04-12 20:06:07 +04:00
|
|
|
}
|
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|
|
};
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|
2011-09-06 20:58:50 +04:00
|
|
|
static const VMStateDescription vmstate_ide_tray_state = {
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|
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.name = "ide_drive/tray_state",
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|
|
.version_id = 1,
|
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|
|
.minimum_version_id = 1,
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|
|
.minimum_version_id_old = 1,
|
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|
|
.fields = (VMStateField[]) {
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VMSTATE_BOOL(tray_open, IDEState),
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VMSTATE_BOOL(tray_locked, IDEState),
|
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|
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VMSTATE_END_OF_LIST()
|
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|
|
}
|
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|
|
};
|
|
|
|
|
2011-08-03 17:08:04 +04:00
|
|
|
static const VMStateDescription vmstate_ide_drive_pio_state = {
|
2010-07-26 23:38:44 +04:00
|
|
|
.name = "ide_drive/pio_state",
|
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|
|
.version_id = 1,
|
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|
|
.minimum_version_id = 1,
|
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|
|
.minimum_version_id_old = 1,
|
|
|
|
.pre_save = ide_drive_pio_pre_save,
|
|
|
|
.post_load = ide_drive_pio_post_load,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_INT32(req_nb_sectors, IDEState),
|
|
|
|
VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
|
|
|
|
vmstate_info_uint8, uint8_t),
|
|
|
|
VMSTATE_INT32(cur_io_buffer_offset, IDEState),
|
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|
|
VMSTATE_INT32(cur_io_buffer_len, IDEState),
|
|
|
|
VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
|
|
|
|
VMSTATE_INT32(elementary_transfer_size, IDEState),
|
|
|
|
VMSTATE_INT32(packet_transfer_size, IDEState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2009-10-07 19:59:47 +04:00
|
|
|
const VMStateDescription vmstate_ide_drive = {
|
|
|
|
.name = "ide_drive",
|
2010-07-26 23:38:41 +04:00
|
|
|
.version_id = 3,
|
2009-10-07 19:59:47 +04:00
|
|
|
.minimum_version_id = 0,
|
|
|
|
.minimum_version_id_old = 0,
|
|
|
|
.post_load = ide_drive_post_load,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_INT32(mult_sectors, IDEState),
|
|
|
|
VMSTATE_INT32(identify_set, IDEState),
|
|
|
|
VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
|
|
|
|
VMSTATE_UINT8(feature, IDEState),
|
|
|
|
VMSTATE_UINT8(error, IDEState),
|
|
|
|
VMSTATE_UINT32(nsector, IDEState),
|
|
|
|
VMSTATE_UINT8(sector, IDEState),
|
|
|
|
VMSTATE_UINT8(lcyl, IDEState),
|
|
|
|
VMSTATE_UINT8(hcyl, IDEState),
|
|
|
|
VMSTATE_UINT8(hob_feature, IDEState),
|
|
|
|
VMSTATE_UINT8(hob_sector, IDEState),
|
|
|
|
VMSTATE_UINT8(hob_nsector, IDEState),
|
|
|
|
VMSTATE_UINT8(hob_lcyl, IDEState),
|
|
|
|
VMSTATE_UINT8(hob_hcyl, IDEState),
|
|
|
|
VMSTATE_UINT8(select, IDEState),
|
|
|
|
VMSTATE_UINT8(status, IDEState),
|
|
|
|
VMSTATE_UINT8(lba48, IDEState),
|
|
|
|
VMSTATE_UINT8(sense_key, IDEState),
|
|
|
|
VMSTATE_UINT8(asc, IDEState),
|
|
|
|
VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
|
|
|
|
VMSTATE_END_OF_LIST()
|
2010-07-26 23:38:44 +04:00
|
|
|
},
|
|
|
|
.subsections = (VMStateSubsection []) {
|
|
|
|
{
|
|
|
|
.vmsd = &vmstate_ide_drive_pio_state,
|
|
|
|
.needed = ide_drive_pio_state_needed,
|
2011-09-06 20:58:50 +04:00
|
|
|
}, {
|
|
|
|
.vmsd = &vmstate_ide_tray_state,
|
|
|
|
.needed = ide_tray_state_needed,
|
2011-04-12 20:06:07 +04:00
|
|
|
}, {
|
|
|
|
.vmsd = &vmstate_ide_atapi_gesn_state,
|
|
|
|
.needed = ide_atapi_gesn_needed,
|
2010-07-26 23:38:44 +04:00
|
|
|
}, {
|
|
|
|
/* empty */
|
|
|
|
}
|
2009-10-07 19:59:47 +04:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2011-08-03 17:08:04 +04:00
|
|
|
static const VMStateDescription vmstate_ide_error_status = {
|
2011-05-26 17:00:34 +04:00
|
|
|
.name ="ide_bus/error",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.minimum_version_id_old = 1,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_INT32(error_status, IDEBus),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2009-10-07 19:24:31 +04:00
|
|
|
const VMStateDescription vmstate_ide_bus = {
|
|
|
|
.name = "ide_bus",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.minimum_version_id_old = 1,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_UINT8(cmd, IDEBus),
|
|
|
|
VMSTATE_UINT8(unit, IDEBus),
|
|
|
|
VMSTATE_END_OF_LIST()
|
2011-05-26 17:00:34 +04:00
|
|
|
},
|
|
|
|
.subsections = (VMStateSubsection []) {
|
|
|
|
{
|
|
|
|
.vmsd = &vmstate_ide_error_status,
|
|
|
|
.needed = ide_error_needed,
|
|
|
|
}, {
|
|
|
|
/* empty */
|
|
|
|
}
|
2009-10-07 19:24:31 +04:00
|
|
|
}
|
|
|
|
};
|
2011-04-03 15:32:46 +04:00
|
|
|
|
|
|
|
void ide_drive_get(DriveInfo **hd, int max_bus)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (drive_get_max_bus(IF_IDE) >= max_bus) {
|
|
|
|
fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
|
|
|
|
hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
|
|
|
|
}
|
|
|
|
}
|