2007-11-11 03:04:49 +03:00
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/*
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* Arm PrimeCell PL061 General Purpose IO with additional
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* Luminary Micro Stellaris bits.
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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2011-06-26 06:21:35 +04:00
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* This code is licensed under the GPL.
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2021-07-02 13:40:12 +03:00
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*
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* QEMU interface:
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* + sysbus MMIO region 0: the device registers
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* + sysbus IRQ: the GPIOINTR interrupt line
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* + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines
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* + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as
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* outputs
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2007-11-11 03:04:49 +03:00
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*/
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2016-01-26 21:17:05 +03:00
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#include "qemu/osdep.h"
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2019-08-12 08:23:42 +03:00
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#include "hw/irq.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/sysbus.h"
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2019-08-12 08:23:45 +03:00
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#include "migration/vmstate.h"
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2015-12-15 15:16:16 +03:00
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#include "qemu/log.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2020-09-03 23:43:22 +03:00
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#include "qom/object.h"
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2021-07-02 13:40:09 +03:00
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#include "trace.h"
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2007-11-11 03:04:49 +03:00
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static const uint8_t pl061_id[12] =
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2011-02-21 23:57:51 +03:00
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{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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static const uint8_t pl061_id_luminary[12] =
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2007-11-11 03:04:49 +03:00
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{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
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2013-07-26 19:31:46 +04:00
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#define TYPE_PL061 "pl061"
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2020-09-16 21:25:19 +03:00
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OBJECT_DECLARE_SIMPLE_TYPE(PL061State, PL061)
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2013-07-26 19:31:46 +04:00
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2020-05-19 11:51:43 +03:00
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#define N_GPIOS 8
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2020-09-03 23:43:22 +03:00
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struct PL061State {
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2013-07-26 19:31:46 +04:00
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SysBusDevice parent_obj;
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2011-10-10 19:18:44 +04:00
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MemoryRegion iomem;
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2011-08-04 02:13:45 +04:00
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uint32_t locked;
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uint32_t data;
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2014-09-12 17:06:48 +04:00
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uint32_t old_out_data;
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uint32_t old_in_data;
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2011-08-04 02:13:45 +04:00
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uint32_t dir;
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uint32_t isense;
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uint32_t ibe;
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uint32_t iev;
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uint32_t im;
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uint32_t istate;
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uint32_t afsel;
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uint32_t dr2r;
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uint32_t dr4r;
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uint32_t dr8r;
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uint32_t odr;
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uint32_t pur;
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uint32_t pdr;
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uint32_t slr;
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uint32_t den;
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uint32_t cr;
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2011-08-04 02:04:49 +04:00
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uint32_t amsel;
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2007-11-11 03:04:49 +03:00
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qemu_irq irq;
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2020-05-19 11:51:43 +03:00
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qemu_irq out[N_GPIOS];
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2011-02-21 23:57:51 +03:00
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const unsigned char *id;
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2020-09-03 23:43:22 +03:00
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};
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2007-11-11 03:04:49 +03:00
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2011-08-04 02:13:45 +04:00
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static const VMStateDescription vmstate_pl061 = {
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.name = "pl061",
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2016-02-18 17:16:17 +03:00
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.version_id = 4,
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.minimum_version_id = 4,
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2011-08-04 02:13:45 +04:00
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.fields = (VMStateField[]) {
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2013-07-26 19:21:21 +04:00
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VMSTATE_UINT32(locked, PL061State),
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VMSTATE_UINT32(data, PL061State),
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2014-09-12 17:06:48 +04:00
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VMSTATE_UINT32(old_out_data, PL061State),
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VMSTATE_UINT32(old_in_data, PL061State),
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2013-07-26 19:21:21 +04:00
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VMSTATE_UINT32(dir, PL061State),
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VMSTATE_UINT32(isense, PL061State),
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VMSTATE_UINT32(ibe, PL061State),
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VMSTATE_UINT32(iev, PL061State),
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VMSTATE_UINT32(im, PL061State),
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VMSTATE_UINT32(istate, PL061State),
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VMSTATE_UINT32(afsel, PL061State),
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VMSTATE_UINT32(dr2r, PL061State),
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VMSTATE_UINT32(dr4r, PL061State),
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VMSTATE_UINT32(dr8r, PL061State),
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VMSTATE_UINT32(odr, PL061State),
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VMSTATE_UINT32(pur, PL061State),
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VMSTATE_UINT32(pdr, PL061State),
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VMSTATE_UINT32(slr, PL061State),
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VMSTATE_UINT32(den, PL061State),
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VMSTATE_UINT32(cr, PL061State),
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VMSTATE_UINT32_V(amsel, PL061State, 2),
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2011-08-04 02:13:45 +04:00
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VMSTATE_END_OF_LIST()
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}
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};
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2013-07-26 19:21:21 +04:00
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static void pl061_update(PL061State *s)
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2007-11-11 03:04:49 +03:00
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{
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uint8_t changed;
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uint8_t mask;
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2007-11-25 02:35:08 +03:00
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uint8_t out;
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2007-11-11 03:04:49 +03:00
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int i;
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2021-07-02 13:40:09 +03:00
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trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
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2014-09-12 17:06:48 +04:00
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2007-11-25 02:35:08 +03:00
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/* Outputs float high. */
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/* FIXME: This is board dependent. */
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out = (s->data & s->dir) | ~s->dir;
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2014-09-12 17:06:48 +04:00
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changed = s->old_out_data ^ out;
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if (changed) {
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s->old_out_data = out;
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2020-05-19 11:51:43 +03:00
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for (i = 0; i < N_GPIOS; i++) {
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2014-09-12 17:06:48 +04:00
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mask = 1 << i;
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if (changed & mask) {
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2021-07-02 13:40:09 +03:00
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int level = (out & mask) != 0;
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trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
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qemu_set_irq(s->out[i], level);
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2014-09-12 17:06:48 +04:00
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}
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2007-11-11 03:04:49 +03:00
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}
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}
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2014-09-12 17:06:48 +04:00
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/* Inputs */
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changed = (s->old_in_data ^ s->data) & ~s->dir;
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if (changed) {
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s->old_in_data = s->data;
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2020-05-19 11:51:43 +03:00
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for (i = 0; i < N_GPIOS; i++) {
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2014-09-12 17:06:48 +04:00
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mask = 1 << i;
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if (changed & mask) {
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2021-07-02 13:40:09 +03:00
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trace_pl061_input_change(DEVICE(s)->canonical_path, i,
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(s->data & mask) != 0);
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2014-09-12 17:06:48 +04:00
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if (!(s->isense & mask)) {
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/* Edge interrupt */
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if (s->ibe & mask) {
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/* Any edge triggers the interrupt */
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s->istate |= mask;
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} else {
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/* Edge is selected by IEV */
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s->istate |= ~(s->data ^ s->iev) & mask;
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}
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}
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}
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}
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}
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/* Level interrupt */
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s->istate |= ~(s->data ^ s->iev) & s->isense;
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2021-07-02 13:40:09 +03:00
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trace_pl061_update_istate(DEVICE(s)->canonical_path,
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s->istate, s->im, (s->istate & s->im) != 0);
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2014-09-12 17:06:48 +04:00
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qemu_set_irq(s->irq, (s->istate & s->im) != 0);
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2007-11-11 03:04:49 +03:00
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}
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2012-10-23 14:30:10 +04:00
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static uint64_t pl061_read(void *opaque, hwaddr offset,
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2011-10-10 19:18:44 +04:00
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unsigned size)
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2007-11-11 03:04:49 +03:00
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{
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2013-07-26 19:21:21 +04:00
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PL061State *s = (PL061State *)opaque;
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2021-07-02 13:40:11 +03:00
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uint64_t r = 0;
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2007-11-11 03:04:49 +03:00
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switch (offset) {
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2021-07-02 13:40:10 +03:00
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case 0x0 ... 0x3ff: /* Data */
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2021-07-02 13:40:11 +03:00
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r = s->data & (offset >> 2);
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break;
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2007-11-11 03:04:49 +03:00
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case 0x400: /* Direction */
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2021-07-02 13:40:11 +03:00
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r = s->dir;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x404: /* Interrupt sense */
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2021-07-02 13:40:11 +03:00
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r = s->isense;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x408: /* Interrupt both edges */
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2021-07-02 13:40:11 +03:00
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r = s->ibe;
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break;
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2011-04-28 19:20:35 +04:00
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case 0x40c: /* Interrupt event */
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2021-07-02 13:40:11 +03:00
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r = s->iev;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x410: /* Interrupt mask */
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2021-07-02 13:40:11 +03:00
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r = s->im;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x414: /* Raw interrupt status */
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2021-07-02 13:40:11 +03:00
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r = s->istate;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x418: /* Masked interrupt status */
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2021-07-02 13:40:11 +03:00
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r = s->istate & s->im;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x420: /* Alternate function select */
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2021-07-02 13:40:11 +03:00
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r = s->afsel;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x500: /* 2mA drive */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->dr2r;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x504: /* 4mA drive */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->dr4r;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x508: /* 8mA drive */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->dr8r;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x50c: /* Open drain */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->odr;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x510: /* Pull-up */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->pur;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x514: /* Pull-down */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->pdr;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x518: /* Slew rate control */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->slr;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x51c: /* Digital enable */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->den;
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break;
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2007-11-11 03:04:49 +03:00
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case 0x520: /* Lock */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->locked;
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break;
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2007-11-11 03:04:49 +03:00
|
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case 0x524: /* Commit */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->cr;
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break;
|
2011-08-04 02:04:49 +04:00
|
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case 0x528: /* Analog mode select */
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2021-07-02 13:40:10 +03:00
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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2021-07-02 13:40:11 +03:00
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r = s->amsel;
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break;
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2021-07-02 13:40:10 +03:00
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case 0xfd0 ... 0xfff: /* ID registers */
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2021-07-02 13:40:11 +03:00
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r = s->id[(offset - 0xfd0) >> 2];
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break;
|
2007-11-11 03:04:49 +03:00
|
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default:
|
2021-07-02 13:40:10 +03:00
|
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl061_read: Bad offset %x\n", (int)offset);
|
2016-02-18 19:56:20 +03:00
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break;
|
2007-11-11 03:04:49 +03:00
|
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}
|
2021-07-02 13:40:11 +03:00
|
|
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trace_pl061_read(DEVICE(s)->canonical_path, offset, r);
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return r;
|
2007-11-11 03:04:49 +03:00
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static void pl061_write(void *opaque, hwaddr offset,
|
2011-10-10 19:18:44 +04:00
|
|
|
uint64_t value, unsigned size)
|
2007-11-11 03:04:49 +03:00
|
|
|
{
|
2013-07-26 19:21:21 +04:00
|
|
|
PL061State *s = (PL061State *)opaque;
|
2007-11-11 03:04:49 +03:00
|
|
|
uint8_t mask;
|
|
|
|
|
2021-07-02 13:40:11 +03:00
|
|
|
trace_pl061_write(DEVICE(s)->canonical_path, offset, value);
|
|
|
|
|
2021-07-02 13:40:10 +03:00
|
|
|
switch (offset) {
|
|
|
|
case 0 ... 0x3ff:
|
2007-11-11 03:04:49 +03:00
|
|
|
mask = (offset >> 2) & s->dir;
|
|
|
|
s->data = (s->data & ~mask) | (value & mask);
|
|
|
|
pl061_update(s);
|
|
|
|
return;
|
|
|
|
case 0x400: /* Direction */
|
2011-08-04 02:13:45 +04:00
|
|
|
s->dir = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x404: /* Interrupt sense */
|
2011-08-04 02:13:45 +04:00
|
|
|
s->isense = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x408: /* Interrupt both edges */
|
2011-08-04 02:13:45 +04:00
|
|
|
s->ibe = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
2011-04-28 19:20:35 +04:00
|
|
|
case 0x40c: /* Interrupt event */
|
2011-08-04 02:13:45 +04:00
|
|
|
s->iev = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x410: /* Interrupt mask */
|
2011-08-04 02:13:45 +04:00
|
|
|
s->im = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x41c: /* Interrupt clear */
|
|
|
|
s->istate &= ~value;
|
|
|
|
break;
|
|
|
|
case 0x420: /* Alternate function select */
|
|
|
|
mask = s->cr;
|
|
|
|
s->afsel = (s->afsel & ~mask) | (value & mask);
|
|
|
|
break;
|
|
|
|
case 0x500: /* 2mA drive */
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2011-08-04 02:13:45 +04:00
|
|
|
s->dr2r = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x504: /* 4mA drive */
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2011-08-04 02:13:45 +04:00
|
|
|
s->dr4r = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x508: /* 8mA drive */
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2011-08-04 02:13:45 +04:00
|
|
|
s->dr8r = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x50c: /* Open drain */
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2011-08-04 02:13:45 +04:00
|
|
|
s->odr = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x510: /* Pull-up */
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2011-08-04 02:13:45 +04:00
|
|
|
s->pur = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x514: /* Pull-down */
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2011-08-04 02:13:45 +04:00
|
|
|
s->pdr = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x518: /* Slew rate control */
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2011-08-04 02:13:45 +04:00
|
|
|
s->slr = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x51c: /* Digital enable */
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2011-08-04 02:13:45 +04:00
|
|
|
s->den = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
|
|
|
case 0x520: /* Lock */
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2007-11-11 03:04:49 +03:00
|
|
|
s->locked = (value != 0xacce551);
|
|
|
|
break;
|
|
|
|
case 0x524: /* Commit */
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2007-11-11 03:04:49 +03:00
|
|
|
if (!s->locked)
|
2011-08-04 02:13:45 +04:00
|
|
|
s->cr = value & 0xff;
|
2007-11-11 03:04:49 +03:00
|
|
|
break;
|
2011-08-04 02:04:49 +04:00
|
|
|
case 0x528:
|
2021-07-02 13:40:10 +03:00
|
|
|
if (s->id != pl061_id_luminary) {
|
|
|
|
goto bad_offset;
|
|
|
|
}
|
2011-08-04 02:04:49 +04:00
|
|
|
s->amsel = value & 0xff;
|
|
|
|
break;
|
2007-11-11 03:04:49 +03:00
|
|
|
default:
|
2021-07-02 13:40:10 +03:00
|
|
|
bad_offset:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"pl061_write: Bad offset %x\n", (int)offset);
|
|
|
|
return;
|
2007-11-11 03:04:49 +03:00
|
|
|
}
|
|
|
|
pl061_update(s);
|
2016-02-18 19:56:20 +03:00
|
|
|
return;
|
2007-11-11 03:04:49 +03:00
|
|
|
}
|
|
|
|
|
2016-02-18 17:16:17 +03:00
|
|
|
static void pl061_reset(DeviceState *dev)
|
2007-11-11 03:04:49 +03:00
|
|
|
{
|
2016-02-18 17:16:17 +03:00
|
|
|
PL061State *s = PL061(dev);
|
|
|
|
|
|
|
|
/* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
|
|
|
|
s->data = 0;
|
|
|
|
s->old_out_data = 0;
|
|
|
|
s->old_in_data = 0;
|
|
|
|
s->dir = 0;
|
|
|
|
s->isense = 0;
|
|
|
|
s->ibe = 0;
|
|
|
|
s->iev = 0;
|
|
|
|
s->im = 0;
|
|
|
|
s->istate = 0;
|
|
|
|
s->afsel = 0;
|
|
|
|
s->dr2r = 0xff;
|
|
|
|
s->dr4r = 0;
|
|
|
|
s->dr8r = 0;
|
|
|
|
s->odr = 0;
|
|
|
|
s->pur = 0;
|
|
|
|
s->pdr = 0;
|
|
|
|
s->slr = 0;
|
|
|
|
s->den = 0;
|
|
|
|
s->locked = 1;
|
|
|
|
s->cr = 0xff;
|
|
|
|
s->amsel = 0;
|
2007-11-11 03:04:49 +03:00
|
|
|
}
|
|
|
|
|
2007-11-18 04:44:38 +03:00
|
|
|
static void pl061_set_irq(void * opaque, int irq, int level)
|
2007-11-11 03:04:49 +03:00
|
|
|
{
|
2013-07-26 19:21:21 +04:00
|
|
|
PL061State *s = (PL061State *)opaque;
|
2007-11-11 03:04:49 +03:00
|
|
|
uint8_t mask;
|
|
|
|
|
|
|
|
mask = 1 << irq;
|
|
|
|
if ((s->dir & mask) == 0) {
|
|
|
|
s->data &= ~mask;
|
|
|
|
if (level)
|
|
|
|
s->data |= mask;
|
|
|
|
pl061_update(s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-10-10 19:18:44 +04:00
|
|
|
static const MemoryRegionOps pl061_ops = {
|
|
|
|
.read = pl061_read,
|
|
|
|
.write = pl061_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-11-11 03:04:49 +03:00
|
|
|
};
|
|
|
|
|
2013-07-26 19:31:46 +04:00
|
|
|
static void pl061_luminary_init(Object *obj)
|
2011-02-21 23:57:51 +03:00
|
|
|
{
|
2013-07-26 19:31:46 +04:00
|
|
|
PL061State *s = PL061(obj);
|
|
|
|
|
|
|
|
s->id = pl061_id_luminary;
|
2011-02-21 23:57:51 +03:00
|
|
|
}
|
|
|
|
|
2013-07-26 19:31:46 +04:00
|
|
|
static void pl061_init(Object *obj)
|
2011-02-21 23:57:51 +03:00
|
|
|
{
|
2013-07-26 19:31:46 +04:00
|
|
|
PL061State *s = PL061(obj);
|
2016-06-14 17:59:13 +03:00
|
|
|
DeviceState *dev = DEVICE(obj);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
2013-07-26 19:31:46 +04:00
|
|
|
|
|
|
|
s->id = pl061_id;
|
2016-06-14 17:59:13 +03:00
|
|
|
|
|
|
|
memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
|
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
2020-05-19 11:51:43 +03:00
|
|
|
qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS);
|
|
|
|
qdev_init_gpio_out(dev, s->out, N_GPIOS);
|
2011-02-21 23:57:51 +03:00
|
|
|
}
|
|
|
|
|
2012-01-24 23:12:29 +04:00
|
|
|
static void pl061_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 23:12:29 +04:00
|
|
|
|
2011-12-08 07:34:16 +04:00
|
|
|
dc->vmsd = &vmstate_pl061;
|
2016-02-18 17:16:17 +03:00
|
|
|
dc->reset = &pl061_reset;
|
2012-01-24 23:12:29 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo pl061_info = {
|
2013-07-26 19:31:46 +04:00
|
|
|
.name = TYPE_PL061,
|
2011-12-08 07:34:16 +04:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
2013-07-26 19:21:21 +04:00
|
|
|
.instance_size = sizeof(PL061State),
|
2013-07-26 19:31:46 +04:00
|
|
|
.instance_init = pl061_init,
|
2011-12-08 07:34:16 +04:00
|
|
|
.class_init = pl061_class_init,
|
2011-08-04 02:13:45 +04:00
|
|
|
};
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo pl061_luminary_info = {
|
2011-12-08 07:34:16 +04:00
|
|
|
.name = "pl061_luminary",
|
2013-07-26 19:31:46 +04:00
|
|
|
.parent = TYPE_PL061,
|
|
|
|
.instance_init = pl061_luminary_init,
|
2011-08-04 02:13:45 +04:00
|
|
|
};
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
static void pl061_register_types(void)
|
2009-06-03 18:16:49 +04:00
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&pl061_info);
|
|
|
|
type_register_static(&pl061_luminary_info);
|
2009-06-03 18:16:49 +04:00
|
|
|
}
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
type_init(pl061_register_types)
|