hw/gpio/pl061: Add tracepoints for register read and write
Add tracepoints for reads and writes to the PL061 registers. This requires restructuring pl061_read() to only return after the tracepoint, rather than having lots of early-returns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -149,90 +149,114 @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PL061State *s = (PL061State *)opaque;
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uint64_t r = 0;
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switch (offset) {
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case 0x0 ... 0x3ff: /* Data */
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return s->data & (offset >> 2);
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r = s->data & (offset >> 2);
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break;
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case 0x400: /* Direction */
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return s->dir;
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r = s->dir;
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break;
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case 0x404: /* Interrupt sense */
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return s->isense;
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r = s->isense;
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break;
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case 0x408: /* Interrupt both edges */
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return s->ibe;
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r = s->ibe;
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break;
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case 0x40c: /* Interrupt event */
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return s->iev;
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r = s->iev;
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break;
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case 0x410: /* Interrupt mask */
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return s->im;
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r = s->im;
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break;
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case 0x414: /* Raw interrupt status */
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return s->istate;
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r = s->istate;
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break;
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case 0x418: /* Masked interrupt status */
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return s->istate & s->im;
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r = s->istate & s->im;
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break;
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case 0x420: /* Alternate function select */
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return s->afsel;
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r = s->afsel;
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break;
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case 0x500: /* 2mA drive */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->dr2r;
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r = s->dr2r;
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break;
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case 0x504: /* 4mA drive */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->dr4r;
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r = s->dr4r;
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break;
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case 0x508: /* 8mA drive */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->dr8r;
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r = s->dr8r;
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break;
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case 0x50c: /* Open drain */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->odr;
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r = s->odr;
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break;
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case 0x510: /* Pull-up */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->pur;
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r = s->pur;
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break;
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case 0x514: /* Pull-down */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->pdr;
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r = s->pdr;
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break;
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case 0x518: /* Slew rate control */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->slr;
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r = s->slr;
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break;
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case 0x51c: /* Digital enable */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->den;
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r = s->den;
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break;
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case 0x520: /* Lock */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->locked;
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r = s->locked;
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break;
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case 0x524: /* Commit */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->cr;
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r = s->cr;
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break;
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case 0x528: /* Analog mode select */
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if (s->id != pl061_id_luminary) {
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goto bad_offset;
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}
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return s->amsel;
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r = s->amsel;
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break;
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case 0xfd0 ... 0xfff: /* ID registers */
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return s->id[(offset - 0xfd0) >> 2];
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r = s->id[(offset - 0xfd0) >> 2];
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break;
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default:
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl061_read: Bad offset %x\n", (int)offset);
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break;
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}
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return 0;
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trace_pl061_read(DEVICE(s)->canonical_path, offset, r);
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return r;
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}
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static void pl061_write(void *opaque, hwaddr offset,
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@ -241,6 +265,8 @@ static void pl061_write(void *opaque, hwaddr offset,
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PL061State *s = (PL061State *)opaque;
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uint8_t mask;
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trace_pl061_write(DEVICE(s)->canonical_path, offset, value);
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switch (offset) {
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case 0 ... 0x3ff:
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mask = (offset >> 2) & s->dir;
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@ -18,6 +18,8 @@ pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIOD
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pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
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pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
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pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
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pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
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pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
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# sifive_gpio.c
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sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
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