2004-03-14 15:20:30 +03:00
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/*
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* QEMU PC keyboard emulation
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2007-09-17 01:08:06 +04:00
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*
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2004-03-14 15:20:30 +03:00
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* Copyright (c) 2003 Fabrice Bellard
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2007-09-17 01:08:06 +04:00
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*
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2004-03-14 15:20:30 +03:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2013-02-04 18:40:22 +04:00
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#include "hw/hw.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/isa/isa.h"
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#include "hw/i386/pc.h"
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#include "hw/input/ps2.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/sysemu.h"
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2004-03-14 15:20:30 +03:00
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/* debug PC keyboard */
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//#define DEBUG_KBD
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2010-05-22 11:59:06 +04:00
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#ifdef DEBUG_KBD
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#define DPRINTF(fmt, ...) \
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do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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2004-03-14 15:20:30 +03:00
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/* Keyboard Controller Commands */
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#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
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#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
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#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
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#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
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#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
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#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
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#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
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#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
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#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
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#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
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#define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
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#define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
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#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
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#define KBD_CCMD_WRITE_OBUF 0xD2
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#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
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initiated by the auxiliary device */
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#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
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#define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
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#define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
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2010-08-19 16:52:12 +04:00
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#define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */
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#define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */
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#define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */
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2004-03-14 15:20:30 +03:00
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/* Keyboard Commands */
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#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
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#define KBD_CMD_ECHO 0xEE
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#define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
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#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
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#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
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#define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
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#define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
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#define KBD_CMD_RESET 0xFF /* Reset */
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/* Keyboard Replies */
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#define KBD_REPLY_POR 0xAA /* Power on reset */
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#define KBD_REPLY_ACK 0xFA /* Command ACK */
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#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
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/* Status Register Bits */
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#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
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#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
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#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
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#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
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#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
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#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
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#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
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#define KBD_STAT_PERR 0x80 /* Parity error */
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/* Controller Mode Register Bits */
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#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
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#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
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#define KBD_MODE_SYS 0x04 /* The system flag (?) */
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#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
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#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
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#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
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#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
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#define KBD_MODE_RFU 0x80
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2010-05-22 11:59:01 +04:00
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/* Output Port Bits */
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#define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */
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#define KBD_OUT_A20 0x02 /* x86 only */
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#define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
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#define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
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2004-03-14 15:20:30 +03:00
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/* Mouse Commands */
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#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
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#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
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#define AUX_SET_RES 0xE8 /* Set resolution */
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#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
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#define AUX_SET_STREAM 0xEA /* Set stream mode */
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#define AUX_POLL 0xEB /* Poll */
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#define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
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#define AUX_SET_WRAP 0xEE /* Set wrap mode */
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#define AUX_SET_REMOTE 0xF0 /* Set remote mode */
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#define AUX_GET_TYPE 0xF2 /* Get type */
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#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
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#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
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#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
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#define AUX_SET_DEFAULT 0xF6
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#define AUX_RESET 0xFF /* Reset aux device */
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#define AUX_ACK 0xFA /* Command byte ACK. */
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#define MOUSE_STATUS_REMOTE 0x40
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#define MOUSE_STATUS_ENABLED 0x20
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#define MOUSE_STATUS_SCALE21 0x10
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2005-11-26 13:14:03 +03:00
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#define KBD_PENDING_KBD 1
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#define KBD_PENDING_AUX 2
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2004-03-14 15:20:30 +03:00
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typedef struct KBDState {
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uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
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uint8_t status;
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uint8_t mode;
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2010-05-22 11:59:01 +04:00
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uint8_t outport;
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2005-11-26 13:14:03 +03:00
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/* Bitmask of devices with data available. */
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2006-04-08 18:12:31 +04:00
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uint8_t pending;
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2005-11-26 13:14:03 +03:00
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void *kbd;
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void *mouse;
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2007-02-18 03:08:44 +03:00
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2007-04-07 22:14:41 +04:00
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qemu_irq irq_kbd;
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qemu_irq irq_mouse;
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2010-05-22 11:59:01 +04:00
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qemu_irq *a20_out;
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2012-10-23 14:30:10 +04:00
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hwaddr mask;
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2004-03-14 15:20:30 +03:00
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} KBDState;
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/* update irq and KBD_STAT_[MOUSE_]OBF */
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/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
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incorrect, but it avoids having to simulate exact delays */
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static void kbd_update_irq(KBDState *s)
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{
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2007-02-18 03:08:44 +03:00
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int irq_kbd_level, irq_mouse_level;
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2004-03-14 15:20:30 +03:00
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2007-02-18 03:08:44 +03:00
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irq_kbd_level = 0;
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irq_mouse_level = 0;
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2004-03-14 15:20:30 +03:00
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s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
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2010-05-22 11:59:01 +04:00
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s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
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2005-11-26 13:14:03 +03:00
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if (s->pending) {
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2004-03-14 15:20:30 +03:00
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s->status |= KBD_STAT_OBF;
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2010-05-22 11:59:01 +04:00
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s->outport |= KBD_OUT_OBF;
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2007-04-16 21:20:48 +04:00
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/* kbd data takes priority over aux data. */
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2005-11-26 13:14:03 +03:00
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if (s->pending == KBD_PENDING_AUX) {
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2004-03-14 15:20:30 +03:00
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s->status |= KBD_STAT_MOUSE_OBF;
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2010-05-22 11:59:01 +04:00
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s->outport |= KBD_OUT_MOUSE_OBF;
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2004-03-14 15:20:30 +03:00
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if (s->mode & KBD_MODE_MOUSE_INT)
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2007-02-18 03:08:44 +03:00
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irq_mouse_level = 1;
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2004-03-14 15:20:30 +03:00
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} else {
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2007-09-17 01:08:06 +04:00
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if ((s->mode & KBD_MODE_KBD_INT) &&
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2004-03-14 15:20:30 +03:00
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!(s->mode & KBD_MODE_DISABLE_KBD))
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2007-02-18 03:08:44 +03:00
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irq_kbd_level = 1;
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2004-03-14 15:20:30 +03:00
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}
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}
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2007-04-07 22:14:41 +04:00
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qemu_set_irq(s->irq_kbd, irq_kbd_level);
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qemu_set_irq(s->irq_mouse, irq_mouse_level);
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2004-03-14 15:20:30 +03:00
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}
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2005-11-26 13:14:03 +03:00
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static void kbd_update_kbd_irq(void *opaque, int level)
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2004-03-14 15:20:30 +03:00
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{
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2005-11-26 13:14:03 +03:00
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KBDState *s = (KBDState *)opaque;
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2004-03-14 15:20:30 +03:00
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2005-11-26 13:14:03 +03:00
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if (level)
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s->pending |= KBD_PENDING_KBD;
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2004-03-14 15:20:30 +03:00
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else
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2005-11-26 13:14:03 +03:00
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s->pending &= ~KBD_PENDING_KBD;
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2004-03-14 15:20:30 +03:00
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kbd_update_irq(s);
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}
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2005-11-26 13:14:03 +03:00
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static void kbd_update_aux_irq(void *opaque, int level)
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2004-03-14 15:20:30 +03:00
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{
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2005-11-26 13:14:03 +03:00
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KBDState *s = (KBDState *)opaque;
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if (level)
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s->pending |= KBD_PENDING_AUX;
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else
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s->pending &= ~KBD_PENDING_AUX;
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kbd_update_irq(s);
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2004-03-14 15:20:30 +03:00
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}
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2012-10-08 15:30:08 +04:00
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static uint64_t kbd_read_status(void *opaque, hwaddr addr,
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unsigned size)
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2004-03-14 15:20:30 +03:00
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{
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2004-03-15 00:46:48 +03:00
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KBDState *s = opaque;
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2004-03-14 15:20:30 +03:00
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int val;
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val = s->status;
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2010-05-22 11:59:06 +04:00
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DPRINTF("kbd: read status=0x%02x\n", val);
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2004-03-14 15:20:30 +03:00
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return val;
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}
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2005-11-26 13:14:03 +03:00
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static void kbd_queue(KBDState *s, int b, int aux)
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{
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if (aux)
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ps2_queue(s->mouse, b);
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else
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ps2_queue(s->kbd, b);
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}
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2011-01-06 21:24:35 +03:00
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static void outport_write(KBDState *s, uint32_t val)
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2010-05-22 11:59:01 +04:00
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{
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2010-05-22 11:59:06 +04:00
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DPRINTF("kbd: write outport=0x%02x\n", val);
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2010-05-22 11:59:01 +04:00
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s->outport = val;
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if (s->a20_out) {
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qemu_set_irq(*s->a20_out, (val >> 1) & 1);
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}
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if (!(val & 1)) {
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qemu_system_reset_request();
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}
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}
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2012-10-08 15:30:08 +04:00
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static void kbd_write_command(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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2004-03-14 15:20:30 +03:00
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{
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2004-03-15 00:46:48 +03:00
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KBDState *s = opaque;
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2004-03-14 15:20:30 +03:00
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2010-05-22 11:59:06 +04:00
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DPRINTF("kbd: write cmd=0x%02x\n", val);
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2010-08-19 16:52:12 +04:00
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/* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
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* low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
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* command specify the output port bits to be pulsed.
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* 0: Bit should be pulsed. 1: Bit should not be modified.
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* The only useful version of this command is pulsing bit 0,
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* which does a CPU reset.
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*/
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if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
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if(!(val & 1))
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val = KBD_CCMD_RESET;
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else
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val = KBD_CCMD_NO_OP;
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}
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2004-03-14 15:20:30 +03:00
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switch(val) {
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case KBD_CCMD_READ_MODE:
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2008-07-19 18:16:20 +04:00
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kbd_queue(s, s->mode, 0);
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2004-03-14 15:20:30 +03:00
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break;
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case KBD_CCMD_WRITE_MODE:
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case KBD_CCMD_WRITE_OBUF:
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case KBD_CCMD_WRITE_AUX_OBUF:
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case KBD_CCMD_WRITE_MOUSE:
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case KBD_CCMD_WRITE_OUTPORT:
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s->write_cmd = val;
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break;
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case KBD_CCMD_MOUSE_DISABLE:
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s->mode |= KBD_MODE_DISABLE_MOUSE;
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break;
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case KBD_CCMD_MOUSE_ENABLE:
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s->mode &= ~KBD_MODE_DISABLE_MOUSE;
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break;
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case KBD_CCMD_TEST_MOUSE:
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kbd_queue(s, 0x00, 0);
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break;
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case KBD_CCMD_SELF_TEST:
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s->status |= KBD_STAT_SELFTEST;
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kbd_queue(s, 0x55, 0);
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break;
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case KBD_CCMD_KBD_TEST:
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kbd_queue(s, 0x00, 0);
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break;
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|
|
case KBD_CCMD_KBD_DISABLE:
|
|
|
|
s->mode |= KBD_MODE_DISABLE_KBD;
|
|
|
|
kbd_update_irq(s);
|
|
|
|
break;
|
|
|
|
case KBD_CCMD_KBD_ENABLE:
|
|
|
|
s->mode &= ~KBD_MODE_DISABLE_KBD;
|
|
|
|
kbd_update_irq(s);
|
|
|
|
break;
|
|
|
|
case KBD_CCMD_READ_INPORT:
|
|
|
|
kbd_queue(s, 0x00, 0);
|
|
|
|
break;
|
|
|
|
case KBD_CCMD_READ_OUTPORT:
|
2010-05-22 11:59:01 +04:00
|
|
|
kbd_queue(s, s->outport, 0);
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
case KBD_CCMD_ENABLE_A20:
|
2010-05-22 11:59:01 +04:00
|
|
|
if (s->a20_out) {
|
|
|
|
qemu_irq_raise(*s->a20_out);
|
|
|
|
}
|
|
|
|
s->outport |= KBD_OUT_A20;
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
case KBD_CCMD_DISABLE_A20:
|
2010-05-22 11:59:01 +04:00
|
|
|
if (s->a20_out) {
|
|
|
|
qemu_irq_lower(*s->a20_out);
|
|
|
|
}
|
|
|
|
s->outport &= ~KBD_OUT_A20;
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
case KBD_CCMD_RESET:
|
2004-06-20 16:58:36 +04:00
|
|
|
qemu_system_reset_request();
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
2010-08-19 16:52:12 +04:00
|
|
|
case KBD_CCMD_NO_OP:
|
|
|
|
/* ignore that */
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
default:
|
2012-10-08 15:30:08 +04:00
|
|
|
fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", (int)val);
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-08 15:30:08 +04:00
|
|
|
static uint64_t kbd_read_data(void *opaque, hwaddr addr,
|
|
|
|
unsigned size)
|
2004-03-14 15:20:30 +03:00
|
|
|
{
|
2004-06-03 22:45:02 +04:00
|
|
|
KBDState *s = opaque;
|
2008-02-10 16:39:24 +03:00
|
|
|
uint32_t val;
|
2004-03-14 15:20:30 +03:00
|
|
|
|
2005-11-26 13:14:03 +03:00
|
|
|
if (s->pending == KBD_PENDING_AUX)
|
2008-02-10 16:39:24 +03:00
|
|
|
val = ps2_read_data(s->mouse);
|
|
|
|
else
|
|
|
|
val = ps2_read_data(s->kbd);
|
2004-03-14 15:20:30 +03:00
|
|
|
|
2010-05-22 11:59:06 +04:00
|
|
|
DPRINTF("kbd: read data=0x%02x\n", val);
|
2008-02-10 16:39:24 +03:00
|
|
|
return val;
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
|
|
|
|
2012-10-08 15:30:08 +04:00
|
|
|
static void kbd_write_data(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned size)
|
2004-03-14 15:20:30 +03:00
|
|
|
{
|
2004-03-15 00:46:48 +03:00
|
|
|
KBDState *s = opaque;
|
2004-03-14 15:20:30 +03:00
|
|
|
|
2010-05-22 11:59:06 +04:00
|
|
|
DPRINTF("kbd: write data=0x%02x\n", val);
|
2004-03-14 15:20:30 +03:00
|
|
|
|
|
|
|
switch(s->write_cmd) {
|
|
|
|
case 0:
|
2005-11-26 13:14:03 +03:00
|
|
|
ps2_write_keyboard(s->kbd, val);
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
case KBD_CCMD_WRITE_MODE:
|
|
|
|
s->mode = val;
|
2006-02-08 07:42:17 +03:00
|
|
|
ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
|
2005-11-26 13:14:03 +03:00
|
|
|
/* ??? */
|
2004-03-14 15:20:30 +03:00
|
|
|
kbd_update_irq(s);
|
|
|
|
break;
|
|
|
|
case KBD_CCMD_WRITE_OBUF:
|
|
|
|
kbd_queue(s, val, 0);
|
|
|
|
break;
|
|
|
|
case KBD_CCMD_WRITE_AUX_OBUF:
|
|
|
|
kbd_queue(s, val, 1);
|
|
|
|
break;
|
|
|
|
case KBD_CCMD_WRITE_OUTPORT:
|
2011-01-06 21:24:35 +03:00
|
|
|
outport_write(s, val);
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
case KBD_CCMD_WRITE_MOUSE:
|
2005-11-26 13:14:03 +03:00
|
|
|
ps2_write_mouse(s->mouse, val);
|
2004-03-14 15:20:30 +03:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
s->write_cmd = 0;
|
|
|
|
}
|
|
|
|
|
2004-06-20 16:58:36 +04:00
|
|
|
static void kbd_reset(void *opaque)
|
2004-03-14 15:20:30 +03:00
|
|
|
{
|
2004-06-20 16:58:36 +04:00
|
|
|
KBDState *s = opaque;
|
2004-03-14 15:20:30 +03:00
|
|
|
|
|
|
|
s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
|
|
|
|
s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
|
2010-05-22 11:59:01 +04:00
|
|
|
s->outport = KBD_OUT_RESET | KBD_OUT_A20;
|
2004-03-14 15:20:30 +03:00
|
|
|
}
|
|
|
|
|
2009-09-10 05:04:41 +04:00
|
|
|
static const VMStateDescription vmstate_kbd = {
|
|
|
|
.name = "pckbd",
|
|
|
|
.version_id = 3,
|
|
|
|
.minimum_version_id = 3,
|
|
|
|
.minimum_version_id_old = 3,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_UINT8(write_cmd, KBDState),
|
|
|
|
VMSTATE_UINT8(status, KBDState),
|
|
|
|
VMSTATE_UINT8(mode, KBDState),
|
|
|
|
VMSTATE_UINT8(pending, KBDState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2004-07-10 17:39:53 +04:00
|
|
|
|
2007-04-16 21:20:48 +04:00
|
|
|
/* Memory mapped interface */
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint32_t kbd_mm_readb (void *opaque, hwaddr addr)
|
2007-04-16 21:20:48 +04:00
|
|
|
{
|
|
|
|
KBDState *s = opaque;
|
|
|
|
|
2008-12-10 18:02:07 +03:00
|
|
|
if (addr & s->mask)
|
2012-10-08 15:30:08 +04:00
|
|
|
return kbd_read_status(s, 0, 1) & 0xff;
|
2008-12-10 18:02:07 +03:00
|
|
|
else
|
2012-10-08 15:30:08 +04:00
|
|
|
return kbd_read_data(s, 0, 1) & 0xff;
|
2007-04-16 21:20:48 +04:00
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value)
|
2007-04-16 21:20:48 +04:00
|
|
|
{
|
|
|
|
KBDState *s = opaque;
|
|
|
|
|
2008-12-10 18:02:07 +03:00
|
|
|
if (addr & s->mask)
|
2012-10-08 15:30:08 +04:00
|
|
|
kbd_write_command(s, 0, value & 0xff, 1);
|
2008-12-10 18:02:07 +03:00
|
|
|
else
|
2012-10-08 15:30:08 +04:00
|
|
|
kbd_write_data(s, 0, value & 0xff, 1);
|
2007-04-16 21:20:48 +04:00
|
|
|
}
|
|
|
|
|
2011-08-11 02:28:17 +04:00
|
|
|
static const MemoryRegionOps i8042_mmio_ops = {
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.old_mmio = {
|
|
|
|
.read = { kbd_mm_readb, kbd_mm_readb, kbd_mm_readb },
|
|
|
|
.write = { kbd_mm_writeb, kbd_mm_writeb, kbd_mm_writeb },
|
|
|
|
},
|
2007-04-16 21:20:48 +04:00
|
|
|
};
|
|
|
|
|
2007-06-08 20:45:23 +04:00
|
|
|
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
|
2011-08-11 02:28:17 +04:00
|
|
|
MemoryRegion *region, ram_addr_t size,
|
2012-10-23 14:30:10 +04:00
|
|
|
hwaddr mask)
|
2007-04-16 21:20:48 +04:00
|
|
|
{
|
2011-08-21 07:09:37 +04:00
|
|
|
KBDState *s = g_malloc0(sizeof(KBDState));
|
2007-04-16 21:20:48 +04:00
|
|
|
|
|
|
|
s->irq_kbd = kbd_irq;
|
|
|
|
s->irq_mouse = mouse_irq;
|
2008-12-10 18:02:07 +03:00
|
|
|
s->mask = mask;
|
2007-04-16 21:20:48 +04:00
|
|
|
|
2010-06-25 21:09:07 +04:00
|
|
|
vmstate_register(NULL, 0, &vmstate_kbd, s);
|
2011-08-11 02:28:17 +04:00
|
|
|
|
2013-06-06 13:41:28 +04:00
|
|
|
memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);
|
2007-04-16 21:20:48 +04:00
|
|
|
|
|
|
|
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
|
|
|
|
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
|
2009-06-27 11:25:07 +04:00
|
|
|
qemu_register_reset(kbd_reset, s);
|
2007-04-16 21:20:48 +04:00
|
|
|
}
|
2009-07-31 14:30:15 +04:00
|
|
|
|
2013-04-28 00:18:47 +04:00
|
|
|
#define TYPE_I8042 "i8042"
|
|
|
|
#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)
|
|
|
|
|
2009-07-31 14:30:15 +04:00
|
|
|
typedef struct ISAKBDState {
|
2013-04-28 00:18:47 +04:00
|
|
|
ISADevice parent_obj;
|
|
|
|
|
2011-08-11 02:28:17 +04:00
|
|
|
KBDState kbd;
|
|
|
|
MemoryRegion io[2];
|
2009-07-31 14:30:15 +04:00
|
|
|
} ISAKBDState;
|
|
|
|
|
2010-05-22 11:59:01 +04:00
|
|
|
void i8042_isa_mouse_fake_event(void *opaque)
|
|
|
|
{
|
|
|
|
ISADevice *dev = opaque;
|
2013-04-28 00:18:47 +04:00
|
|
|
ISAKBDState *isa = I8042(dev);
|
|
|
|
KBDState *s = &isa->kbd;
|
2010-05-22 11:59:01 +04:00
|
|
|
|
|
|
|
ps2_mouse_fake_event(s->mouse);
|
|
|
|
}
|
|
|
|
|
|
|
|
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out)
|
|
|
|
{
|
2013-04-28 00:18:47 +04:00
|
|
|
ISAKBDState *isa = I8042(dev);
|
|
|
|
KBDState *s = &isa->kbd;
|
2010-05-22 11:59:01 +04:00
|
|
|
|
|
|
|
s->a20_out = a20_out;
|
|
|
|
}
|
|
|
|
|
2009-12-04 23:44:44 +03:00
|
|
|
static const VMStateDescription vmstate_kbd_isa = {
|
2009-12-02 14:36:46 +03:00
|
|
|
.name = "pckbd",
|
|
|
|
.version_id = 3,
|
|
|
|
.minimum_version_id = 3,
|
|
|
|
.minimum_version_id_old = 3,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2011-08-11 02:28:17 +04:00
|
|
|
static const MemoryRegionOps i8042_data_ops = {
|
2012-10-08 15:30:08 +04:00
|
|
|
.read = kbd_read_data,
|
|
|
|
.write = kbd_write_data,
|
|
|
|
.impl = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 1,
|
|
|
|
},
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
2011-08-11 02:28:17 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps i8042_cmd_ops = {
|
2012-10-08 15:30:08 +04:00
|
|
|
.read = kbd_read_status,
|
|
|
|
.write = kbd_write_command,
|
|
|
|
.impl = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 1,
|
|
|
|
},
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
2011-08-11 02:28:17 +04:00
|
|
|
};
|
|
|
|
|
2012-11-25 05:37:14 +04:00
|
|
|
static void i8042_initfn(Object *obj)
|
2009-07-31 14:30:15 +04:00
|
|
|
{
|
2012-11-25 05:37:14 +04:00
|
|
|
ISAKBDState *isa_s = I8042(obj);
|
2011-08-11 02:28:17 +04:00
|
|
|
KBDState *s = &isa_s->kbd;
|
2009-07-31 14:30:15 +04:00
|
|
|
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
|
|
|
|
"i8042-data", 1);
|
|
|
|
memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
|
|
|
|
"i8042-cmd", 1);
|
2012-11-25 05:37:14 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void i8042_realizefn(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
ISADevice *isadev = ISA_DEVICE(dev);
|
|
|
|
ISAKBDState *isa_s = I8042(dev);
|
|
|
|
KBDState *s = &isa_s->kbd;
|
|
|
|
|
|
|
|
isa_init_irq(isadev, &s->irq_kbd, 1);
|
|
|
|
isa_init_irq(isadev, &s->irq_mouse, 12);
|
|
|
|
|
|
|
|
isa_register_ioport(isadev, isa_s->io + 0, 0x60);
|
|
|
|
isa_register_ioport(isadev, isa_s->io + 1, 0x64);
|
2009-07-31 14:30:15 +04:00
|
|
|
|
|
|
|
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
|
|
|
|
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
|
|
|
|
qemu_register_reset(kbd_reset, s);
|
|
|
|
}
|
|
|
|
|
2011-12-04 21:52:49 +04:00
|
|
|
static void i8042_class_initfn(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-11-25 05:37:14 +04:00
|
|
|
|
|
|
|
dc->realize = i8042_realizefn;
|
2011-12-08 07:34:16 +04:00
|
|
|
dc->vmsd = &vmstate_kbd_isa;
|
2011-12-04 21:52:49 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo i8042_info = {
|
2013-04-28 00:18:47 +04:00
|
|
|
.name = TYPE_I8042,
|
2011-12-08 07:34:16 +04:00
|
|
|
.parent = TYPE_ISA_DEVICE,
|
|
|
|
.instance_size = sizeof(ISAKBDState),
|
2012-11-25 05:37:14 +04:00
|
|
|
.instance_init = i8042_initfn,
|
2011-12-08 07:34:16 +04:00
|
|
|
.class_init = i8042_class_initfn,
|
2009-07-31 14:30:15 +04:00
|
|
|
};
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
static void i8042_register_types(void)
|
2009-07-31 14:30:15 +04:00
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&i8042_info);
|
2009-07-31 14:30:15 +04:00
|
|
|
}
|
2012-02-09 18:20:55 +04:00
|
|
|
|
|
|
|
type_init(i8042_register_types)
|